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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
69123184 | 16 | #include <linux/uaccess.h> |
4574910e PM |
17 | #include <asm/reg.h> |
18 | #include <asm/pmc.h> | |
01d0287f | 19 | #include <asm/machdep.h> |
0475f9ea | 20 | #include <asm/firmware.h> |
0bbd0d4b | 21 | #include <asm/ptrace.h> |
69123184 | 22 | #include <asm/code-patching.h> |
4574910e | 23 | |
3925f46b AK |
24 | #define BHRB_MAX_ENTRIES 32 |
25 | #define BHRB_TARGET 0x0000000000000002 | |
26 | #define BHRB_PREDICTION 0x0000000000000001 | |
27 | #define BHRB_EA 0xFFFFFFFFFFFFFFFC | |
28 | ||
cdd6c482 IM |
29 | struct cpu_hw_events { |
30 | int n_events; | |
4574910e PM |
31 | int n_percpu; |
32 | int disabled; | |
33 | int n_added; | |
ab7ef2e5 PM |
34 | int n_limited; |
35 | u8 pmcs_enabled; | |
cdd6c482 IM |
36 | struct perf_event *event[MAX_HWEVENTS]; |
37 | u64 events[MAX_HWEVENTS]; | |
38 | unsigned int flags[MAX_HWEVENTS]; | |
448d64f8 | 39 | unsigned long mmcr[3]; |
a8f90e90 PM |
40 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
41 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
42 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
43 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
44 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 LM |
45 | |
46 | unsigned int group_flag; | |
47 | int n_txn_start; | |
3925f46b AK |
48 | |
49 | /* BHRB bits */ | |
50 | u64 bhrb_filter; /* BHRB HW branch filter */ | |
51 | int bhrb_users; | |
52 | void *bhrb_context; | |
53 | struct perf_branch_stack bhrb_stack; | |
54 | struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; | |
4574910e | 55 | }; |
3925f46b | 56 | |
cdd6c482 | 57 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e PM |
58 | |
59 | struct power_pmu *ppmu; | |
60 | ||
d095cd46 | 61 | /* |
57c0c15b | 62 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
63 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
64 | * hypervisor bit set in the MSR, or if we are running on a processor | |
65 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
66 | * then we need to use the FCHV bit to ignore kernel events. | |
67 | */ | |
cdd6c482 | 68 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 69 | |
98fb1807 PM |
70 | /* |
71 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
72 | * and a few other names are different. | |
73 | */ | |
74 | #ifdef CONFIG_PPC32 | |
75 | ||
76 | #define MMCR0_FCHV 0 | |
77 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
7a7a41f9 | 78 | #define MMCR0_FC56 0 |
378a6ee9 | 79 | #define MMCR0_PMAO 0 |
98fb1807 PM |
80 | |
81 | #define SPRN_MMCRA SPRN_MMCR2 | |
82 | #define MMCRA_SAMPLE_ENABLE 0 | |
83 | ||
84 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
85 | { | |
86 | return 0; | |
87 | } | |
98fb1807 PM |
88 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
89 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
90 | { | |
91 | return 0; | |
92 | } | |
75382aa7 AB |
93 | static inline void perf_read_regs(struct pt_regs *regs) |
94 | { | |
95 | regs->result = 0; | |
96 | } | |
98fb1807 PM |
97 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
98 | { | |
99 | return 0; | |
100 | } | |
101 | ||
e6878835 | 102 | static inline int siar_valid(struct pt_regs *regs) |
103 | { | |
104 | return 1; | |
105 | } | |
106 | ||
d52f2dc4 MN |
107 | static inline void power_pmu_bhrb_enable(struct perf_event *event) {} |
108 | static inline void power_pmu_bhrb_disable(struct perf_event *event) {} | |
109 | void power_pmu_flush_branch_stack(void) {} | |
110 | static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} | |
98fb1807 PM |
111 | #endif /* CONFIG_PPC32 */ |
112 | ||
33904054 ME |
113 | static bool regs_use_siar(struct pt_regs *regs) |
114 | { | |
cbda6aa1 | 115 | return !!regs->result; |
33904054 ME |
116 | } |
117 | ||
98fb1807 PM |
118 | /* |
119 | * Things that are specific to 64-bit implementations. | |
120 | */ | |
121 | #ifdef CONFIG_PPC64 | |
122 | ||
123 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
124 | { | |
125 | unsigned long mmcra = regs->dsisr; | |
126 | ||
7a786832 | 127 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
128 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
129 | if (slot > 1) | |
130 | return 4 * (slot - 1); | |
131 | } | |
7a786832 | 132 | |
98fb1807 PM |
133 | return 0; |
134 | } | |
135 | ||
98fb1807 PM |
136 | /* |
137 | * The user wants a data address recorded. | |
138 | * If we're not doing instruction sampling, give them the SDAR | |
139 | * (sampled data address). If we are doing instruction sampling, then | |
140 | * only give them the SDAR if it corresponds to the instruction | |
58a032c3 ME |
141 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the |
142 | * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. | |
98fb1807 PM |
143 | */ |
144 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
145 | { | |
146 | unsigned long mmcra = regs->dsisr; | |
58a032c3 | 147 | bool sdar_valid; |
e6878835 | 148 | |
58a032c3 ME |
149 | if (ppmu->flags & PPMU_HAS_SIER) |
150 | sdar_valid = regs->dar & SIER_SDAR_VALID; | |
151 | else { | |
152 | unsigned long sdsync; | |
153 | ||
154 | if (ppmu->flags & PPMU_SIAR_VALID) | |
155 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
156 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
157 | sdsync = POWER6_MMCRA_SDSYNC; | |
158 | else | |
159 | sdsync = MMCRA_SDSYNC; | |
160 | ||
161 | sdar_valid = mmcra & sdsync; | |
162 | } | |
98fb1807 | 163 | |
58a032c3 | 164 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) |
98fb1807 PM |
165 | *addrp = mfspr(SPRN_SDAR); |
166 | } | |
167 | ||
5682c460 | 168 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
169 | { |
170 | unsigned long sihv = MMCRA_SIHV; | |
171 | ||
8f61aa32 ME |
172 | if (ppmu->flags & PPMU_HAS_SIER) |
173 | return !!(regs->dar & SIER_SIHV); | |
174 | ||
68b30bb9 AB |
175 | if (ppmu->flags & PPMU_ALT_SIPR) |
176 | sihv = POWER6_MMCRA_SIHV; | |
177 | ||
5682c460 | 178 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
179 | } |
180 | ||
5682c460 | 181 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
182 | { |
183 | unsigned long sipr = MMCRA_SIPR; | |
184 | ||
8f61aa32 ME |
185 | if (ppmu->flags & PPMU_HAS_SIER) |
186 | return !!(regs->dar & SIER_SIPR); | |
187 | ||
68b30bb9 AB |
188 | if (ppmu->flags & PPMU_ALT_SIPR) |
189 | sipr = POWER6_MMCRA_SIPR; | |
190 | ||
5682c460 | 191 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
192 | } |
193 | ||
1ce447b9 BH |
194 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
195 | { | |
196 | if (regs->msr & MSR_PR) | |
197 | return PERF_RECORD_MISC_USER; | |
198 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
199 | return PERF_RECORD_MISC_HYPERVISOR; | |
200 | return PERF_RECORD_MISC_KERNEL; | |
201 | } | |
202 | ||
98fb1807 PM |
203 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
204 | { | |
33904054 | 205 | bool use_siar = regs_use_siar(regs); |
98fb1807 | 206 | |
75382aa7 | 207 | if (!use_siar) |
1ce447b9 BH |
208 | return perf_flags_from_msr(regs); |
209 | ||
210 | /* | |
211 | * If we don't have flags in MMCRA, rather than using | |
212 | * the MSR, we intuit the flags from the address in | |
213 | * SIAR which should give slightly more reliable | |
214 | * results | |
215 | */ | |
cbda6aa1 | 216 | if (ppmu->flags & PPMU_NO_SIPR) { |
1ce447b9 BH |
217 | unsigned long siar = mfspr(SPRN_SIAR); |
218 | if (siar >= PAGE_OFFSET) | |
219 | return PERF_RECORD_MISC_KERNEL; | |
220 | return PERF_RECORD_MISC_USER; | |
221 | } | |
98fb1807 | 222 | |
7abb840b | 223 | /* PR has priority over HV, so order below is important */ |
5682c460 | 224 | if (regs_sipr(regs)) |
7abb840b | 225 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
226 | |
227 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 228 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 229 | |
7abb840b | 230 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
231 | } |
232 | ||
233 | /* | |
234 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
235 | * on each interrupt. | |
8f61aa32 | 236 | * Overload regs->dar to store SIER if we have it. |
75382aa7 AB |
237 | * Overload regs->result to specify whether we should use the MSR (result |
238 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
239 | */ |
240 | static inline void perf_read_regs(struct pt_regs *regs) | |
241 | { | |
75382aa7 AB |
242 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
243 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
244 | int use_siar; | |
245 | ||
5682c460 | 246 | regs->dsisr = mmcra; |
8f61aa32 | 247 | |
cbda6aa1 ME |
248 | if (ppmu->flags & PPMU_HAS_SIER) |
249 | regs->dar = mfspr(SPRN_SIER); | |
8f61aa32 | 250 | |
5c093efa AB |
251 | /* |
252 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
253 | * not valid. Use pt_regs. | |
254 | * | |
255 | * If it is a marked event use the SIAR. | |
256 | * | |
257 | * If the PMU doesn't update the SIAR for non marked events use | |
258 | * pt_regs. | |
259 | * | |
260 | * If the PMU has HV/PR flags then check to see if they | |
261 | * place the exception in userspace. If so, use pt_regs. In | |
262 | * continuous sampling mode the SIAR and the PMU exception are | |
263 | * not synchronised, so they may be many instructions apart. | |
264 | * This can result in confusing backtraces. We still want | |
265 | * hypervisor samples as well as samples in the kernel with | |
266 | * interrupts off hence the userspace check. | |
267 | */ | |
75382aa7 AB |
268 | if (TRAP(regs) != 0xf00) |
269 | use_siar = 0; | |
5c093efa AB |
270 | else if (marked) |
271 | use_siar = 1; | |
272 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
273 | use_siar = 0; | |
cbda6aa1 | 274 | else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) |
75382aa7 AB |
275 | use_siar = 0; |
276 | else | |
277 | use_siar = 1; | |
278 | ||
cbda6aa1 | 279 | regs->result = use_siar; |
98fb1807 PM |
280 | } |
281 | ||
282 | /* | |
283 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
284 | * it as an NMI. | |
285 | */ | |
286 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
287 | { | |
288 | return !regs->softe; | |
289 | } | |
290 | ||
e6878835 | 291 | /* |
292 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
293 | * must be sampled only if the SIAR-valid bit is set. | |
294 | * | |
295 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
296 | * bit, assume that SIAR is valid. | |
297 | */ | |
298 | static inline int siar_valid(struct pt_regs *regs) | |
299 | { | |
300 | unsigned long mmcra = regs->dsisr; | |
301 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
302 | ||
58a032c3 ME |
303 | if (marked) { |
304 | if (ppmu->flags & PPMU_HAS_SIER) | |
305 | return regs->dar & SIER_SIAR_VALID; | |
306 | ||
307 | if (ppmu->flags & PPMU_SIAR_VALID) | |
308 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
309 | } | |
e6878835 | 310 | |
311 | return 1; | |
312 | } | |
313 | ||
d52f2dc4 MN |
314 | |
315 | /* Reset all possible BHRB entries */ | |
316 | static void power_pmu_bhrb_reset(void) | |
317 | { | |
318 | asm volatile(PPC_CLRBHRB); | |
319 | } | |
320 | ||
321 | static void power_pmu_bhrb_enable(struct perf_event *event) | |
322 | { | |
323 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
324 | ||
325 | if (!ppmu->bhrb_nr) | |
326 | return; | |
327 | ||
328 | /* Clear BHRB if we changed task context to avoid data leaks */ | |
329 | if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { | |
330 | power_pmu_bhrb_reset(); | |
331 | cpuhw->bhrb_context = event->ctx; | |
332 | } | |
333 | cpuhw->bhrb_users++; | |
334 | } | |
335 | ||
336 | static void power_pmu_bhrb_disable(struct perf_event *event) | |
337 | { | |
338 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
339 | ||
340 | if (!ppmu->bhrb_nr) | |
341 | return; | |
342 | ||
343 | cpuhw->bhrb_users--; | |
344 | WARN_ON_ONCE(cpuhw->bhrb_users < 0); | |
345 | ||
346 | if (!cpuhw->disabled && !cpuhw->bhrb_users) { | |
347 | /* BHRB cannot be turned off when other | |
348 | * events are active on the PMU. | |
349 | */ | |
350 | ||
351 | /* avoid stale pointer */ | |
352 | cpuhw->bhrb_context = NULL; | |
353 | } | |
354 | } | |
355 | ||
356 | /* Called from ctxsw to prevent one process's branch entries to | |
357 | * mingle with the other process's entries during context switch. | |
358 | */ | |
359 | void power_pmu_flush_branch_stack(void) | |
360 | { | |
361 | if (ppmu->bhrb_nr) | |
362 | power_pmu_bhrb_reset(); | |
363 | } | |
69123184 MN |
364 | /* Calculate the to address for a branch */ |
365 | static __u64 power_pmu_bhrb_to(u64 addr) | |
366 | { | |
367 | unsigned int instr; | |
368 | int ret; | |
369 | __u64 target; | |
370 | ||
371 | if (is_kernel_addr(addr)) | |
372 | return branch_target((unsigned int *)addr); | |
373 | ||
374 | /* Userspace: need copy instruction here then translate it */ | |
375 | pagefault_disable(); | |
376 | ret = __get_user_inatomic(instr, (unsigned int __user *)addr); | |
377 | if (ret) { | |
378 | pagefault_enable(); | |
379 | return 0; | |
380 | } | |
381 | pagefault_enable(); | |
382 | ||
383 | target = branch_target(&instr); | |
384 | if ((!target) || (instr & BRANCH_ABSOLUTE)) | |
385 | return target; | |
386 | ||
387 | /* Translate relative branch target from kernel to user address */ | |
388 | return target - (unsigned long)&instr + addr; | |
389 | } | |
d52f2dc4 | 390 | |
d52f2dc4 | 391 | /* Processing BHRB entries */ |
506e70d1 | 392 | void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) |
d52f2dc4 MN |
393 | { |
394 | u64 val; | |
395 | u64 addr; | |
506e70d1 | 396 | int r_index, u_index, pred; |
d52f2dc4 MN |
397 | |
398 | r_index = 0; | |
399 | u_index = 0; | |
400 | while (r_index < ppmu->bhrb_nr) { | |
401 | /* Assembly read function */ | |
506e70d1 MN |
402 | val = read_bhrb(r_index++); |
403 | if (!val) | |
404 | /* Terminal marker: End of valid BHRB entries */ | |
d52f2dc4 | 405 | break; |
506e70d1 | 406 | else { |
d52f2dc4 MN |
407 | addr = val & BHRB_EA; |
408 | pred = val & BHRB_PREDICTION; | |
d52f2dc4 | 409 | |
506e70d1 MN |
410 | if (!addr) |
411 | /* invalid entry */ | |
d52f2dc4 | 412 | continue; |
d52f2dc4 | 413 | |
506e70d1 MN |
414 | /* Branches are read most recent first (ie. mfbhrb 0 is |
415 | * the most recent branch). | |
416 | * There are two types of valid entries: | |
417 | * 1) a target entry which is the to address of a | |
418 | * computed goto like a blr,bctr,btar. The next | |
419 | * entry read from the bhrb will be branch | |
420 | * corresponding to this target (ie. the actual | |
421 | * blr/bctr/btar instruction). | |
422 | * 2) a from address which is an actual branch. If a | |
423 | * target entry proceeds this, then this is the | |
424 | * matching branch for that target. If this is not | |
425 | * following a target entry, then this is a branch | |
426 | * where the target is given as an immediate field | |
427 | * in the instruction (ie. an i or b form branch). | |
428 | * In this case we need to read the instruction from | |
429 | * memory to determine the target/to address. | |
430 | */ | |
d52f2dc4 | 431 | |
d52f2dc4 | 432 | if (val & BHRB_TARGET) { |
506e70d1 MN |
433 | /* Target branches use two entries |
434 | * (ie. computed gotos/XL form) | |
435 | */ | |
436 | cpuhw->bhrb_entries[u_index].to = addr; | |
437 | cpuhw->bhrb_entries[u_index].mispred = pred; | |
438 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 439 | |
506e70d1 MN |
440 | /* Get from address in next entry */ |
441 | val = read_bhrb(r_index++); | |
442 | addr = val & BHRB_EA; | |
443 | if (val & BHRB_TARGET) { | |
444 | /* Shouldn't have two targets in a | |
445 | row.. Reset index and try again */ | |
446 | r_index--; | |
447 | addr = 0; | |
448 | } | |
449 | cpuhw->bhrb_entries[u_index].from = addr; | |
d52f2dc4 | 450 | } else { |
506e70d1 MN |
451 | /* Branches to immediate field |
452 | (ie I or B form) */ | |
d52f2dc4 | 453 | cpuhw->bhrb_entries[u_index].from = addr; |
69123184 MN |
454 | cpuhw->bhrb_entries[u_index].to = |
455 | power_pmu_bhrb_to(addr); | |
d52f2dc4 MN |
456 | cpuhw->bhrb_entries[u_index].mispred = pred; |
457 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 458 | } |
506e70d1 MN |
459 | u_index++; |
460 | ||
d52f2dc4 MN |
461 | } |
462 | } | |
463 | cpuhw->bhrb_stack.nr = u_index; | |
464 | return; | |
465 | } | |
466 | ||
98fb1807 PM |
467 | #endif /* CONFIG_PPC64 */ |
468 | ||
cdd6c482 | 469 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 470 | |
cdd6c482 | 471 | void perf_event_print_debug(void) |
4574910e PM |
472 | { |
473 | } | |
474 | ||
4574910e | 475 | /* |
57c0c15b | 476 | * Read one performance monitor counter (PMC). |
4574910e PM |
477 | */ |
478 | static unsigned long read_pmc(int idx) | |
479 | { | |
480 | unsigned long val; | |
481 | ||
482 | switch (idx) { | |
483 | case 1: | |
484 | val = mfspr(SPRN_PMC1); | |
485 | break; | |
486 | case 2: | |
487 | val = mfspr(SPRN_PMC2); | |
488 | break; | |
489 | case 3: | |
490 | val = mfspr(SPRN_PMC3); | |
491 | break; | |
492 | case 4: | |
493 | val = mfspr(SPRN_PMC4); | |
494 | break; | |
495 | case 5: | |
496 | val = mfspr(SPRN_PMC5); | |
497 | break; | |
498 | case 6: | |
499 | val = mfspr(SPRN_PMC6); | |
500 | break; | |
98fb1807 | 501 | #ifdef CONFIG_PPC64 |
4574910e PM |
502 | case 7: |
503 | val = mfspr(SPRN_PMC7); | |
504 | break; | |
505 | case 8: | |
506 | val = mfspr(SPRN_PMC8); | |
507 | break; | |
98fb1807 | 508 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
509 | default: |
510 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
511 | val = 0; | |
512 | } | |
513 | return val; | |
514 | } | |
515 | ||
516 | /* | |
517 | * Write one PMC. | |
518 | */ | |
519 | static void write_pmc(int idx, unsigned long val) | |
520 | { | |
521 | switch (idx) { | |
522 | case 1: | |
523 | mtspr(SPRN_PMC1, val); | |
524 | break; | |
525 | case 2: | |
526 | mtspr(SPRN_PMC2, val); | |
527 | break; | |
528 | case 3: | |
529 | mtspr(SPRN_PMC3, val); | |
530 | break; | |
531 | case 4: | |
532 | mtspr(SPRN_PMC4, val); | |
533 | break; | |
534 | case 5: | |
535 | mtspr(SPRN_PMC5, val); | |
536 | break; | |
537 | case 6: | |
538 | mtspr(SPRN_PMC6, val); | |
539 | break; | |
98fb1807 | 540 | #ifdef CONFIG_PPC64 |
4574910e PM |
541 | case 7: |
542 | mtspr(SPRN_PMC7, val); | |
543 | break; | |
544 | case 8: | |
545 | mtspr(SPRN_PMC8, val); | |
546 | break; | |
98fb1807 | 547 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
548 | default: |
549 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
550 | } | |
551 | } | |
552 | ||
553 | /* | |
554 | * Check if a set of events can all go on the PMU at once. | |
555 | * If they can't, this will look at alternative codes for the events | |
556 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 557 | * The feasible set is returned in event_id[]. |
4574910e | 558 | */ |
cdd6c482 IM |
559 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
560 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 561 | int n_ev) |
4574910e | 562 | { |
448d64f8 | 563 | unsigned long mask, value, nv; |
cdd6c482 IM |
564 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
565 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 566 | int i, j; |
448d64f8 PM |
567 | unsigned long addf = ppmu->add_fields; |
568 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 569 | |
a8f90e90 | 570 | if (n_ev > ppmu->n_counter) |
4574910e PM |
571 | return -1; |
572 | ||
573 | /* First see if the events will go on as-is */ | |
574 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 575 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
576 | && !ppmu->limited_pmc_event(event_id[i])) { |
577 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 578 | cpuhw->alternatives[i]); |
cdd6c482 | 579 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 580 | } |
cdd6c482 | 581 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 582 | &cpuhw->avalues[i][0])) |
4574910e | 583 | return -1; |
4574910e PM |
584 | } |
585 | value = mask = 0; | |
586 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
587 | nv = (value | cpuhw->avalues[i][0]) + |
588 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 589 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
590 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
591 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
592 | break; |
593 | value = nv; | |
e51ee31e | 594 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
595 | } |
596 | if (i == n_ev) | |
597 | return 0; /* all OK */ | |
598 | ||
599 | /* doesn't work, gather alternatives... */ | |
600 | if (!ppmu->get_alternatives) | |
601 | return -1; | |
602 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 603 | choice[i] = 0; |
cdd6c482 | 604 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 605 | cpuhw->alternatives[i]); |
4574910e | 606 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
607 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
608 | &cpuhw->amasks[i][j], | |
609 | &cpuhw->avalues[i][j]); | |
4574910e PM |
610 | } |
611 | ||
612 | /* enumerate all possibilities and see if any will work */ | |
613 | i = 0; | |
614 | j = -1; | |
615 | value = mask = nv = 0; | |
616 | while (i < n_ev) { | |
617 | if (j >= 0) { | |
618 | /* we're backtracking, restore context */ | |
619 | value = svalues[i]; | |
620 | mask = smasks[i]; | |
621 | j = choice[i]; | |
622 | } | |
623 | /* | |
cdd6c482 | 624 | * See if any alternative k for event_id i, |
4574910e PM |
625 | * where k > j, will satisfy the constraints. |
626 | */ | |
627 | while (++j < n_alt[i]) { | |
e51ee31e PM |
628 | nv = (value | cpuhw->avalues[i][j]) + |
629 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 630 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
631 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
632 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
633 | break; |
634 | } | |
635 | if (j >= n_alt[i]) { | |
636 | /* | |
637 | * No feasible alternative, backtrack | |
cdd6c482 | 638 | * to event_id i-1 and continue enumerating its |
4574910e PM |
639 | * alternatives from where we got up to. |
640 | */ | |
641 | if (--i < 0) | |
642 | return -1; | |
643 | } else { | |
644 | /* | |
cdd6c482 IM |
645 | * Found a feasible alternative for event_id i, |
646 | * remember where we got up to with this event_id, | |
647 | * go on to the next event_id, and start with | |
4574910e PM |
648 | * the first alternative for it. |
649 | */ | |
650 | choice[i] = j; | |
651 | svalues[i] = value; | |
652 | smasks[i] = mask; | |
653 | value = nv; | |
e51ee31e | 654 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
655 | ++i; |
656 | j = -1; | |
657 | } | |
658 | } | |
659 | ||
660 | /* OK, we have a feasible combination, tell the caller the solution */ | |
661 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 662 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
663 | return 0; |
664 | } | |
665 | ||
0475f9ea | 666 | /* |
cdd6c482 | 667 | * Check if newly-added events have consistent settings for |
0475f9ea | 668 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 669 | * added events. |
0475f9ea | 670 | */ |
cdd6c482 | 671 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 672 | int n_prev, int n_new) |
0475f9ea | 673 | { |
ab7ef2e5 PM |
674 | int eu = 0, ek = 0, eh = 0; |
675 | int i, n, first; | |
cdd6c482 | 676 | struct perf_event *event; |
0475f9ea PM |
677 | |
678 | n = n_prev + n_new; | |
679 | if (n <= 1) | |
680 | return 0; | |
681 | ||
ab7ef2e5 PM |
682 | first = 1; |
683 | for (i = 0; i < n; ++i) { | |
684 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
685 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
686 | continue; | |
687 | } | |
cdd6c482 | 688 | event = ctrs[i]; |
ab7ef2e5 | 689 | if (first) { |
cdd6c482 IM |
690 | eu = event->attr.exclude_user; |
691 | ek = event->attr.exclude_kernel; | |
692 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 693 | first = 0; |
cdd6c482 IM |
694 | } else if (event->attr.exclude_user != eu || |
695 | event->attr.exclude_kernel != ek || | |
696 | event->attr.exclude_hv != eh) { | |
0475f9ea | 697 | return -EAGAIN; |
ab7ef2e5 | 698 | } |
0475f9ea | 699 | } |
ab7ef2e5 PM |
700 | |
701 | if (eu || ek || eh) | |
702 | for (i = 0; i < n; ++i) | |
703 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
704 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
705 | ||
0475f9ea PM |
706 | return 0; |
707 | } | |
708 | ||
86c74ab3 EM |
709 | static u64 check_and_compute_delta(u64 prev, u64 val) |
710 | { | |
711 | u64 delta = (val - prev) & 0xfffffffful; | |
712 | ||
713 | /* | |
714 | * POWER7 can roll back counter values, if the new value is smaller | |
715 | * than the previous value it will cause the delta and the counter to | |
716 | * have bogus values unless we rolled a counter over. If a coutner is | |
717 | * rolled back, it will be smaller, but within 256, which is the maximum | |
718 | * number of events to rollback at once. If we dectect a rollback | |
719 | * return 0. This can lead to a small lack of precision in the | |
720 | * counters. | |
721 | */ | |
722 | if (prev > val && (prev - val) < 256) | |
723 | delta = 0; | |
724 | ||
725 | return delta; | |
726 | } | |
727 | ||
cdd6c482 | 728 | static void power_pmu_read(struct perf_event *event) |
4574910e | 729 | { |
98fb1807 | 730 | s64 val, delta, prev; |
4574910e | 731 | |
a4eaf7f1 PZ |
732 | if (event->hw.state & PERF_HES_STOPPED) |
733 | return; | |
734 | ||
cdd6c482 | 735 | if (!event->hw.idx) |
4574910e PM |
736 | return; |
737 | /* | |
738 | * Performance monitor interrupts come even when interrupts | |
739 | * are soft-disabled, as long as interrupts are hard-enabled. | |
740 | * Therefore we treat them like NMIs. | |
741 | */ | |
742 | do { | |
e7850595 | 743 | prev = local64_read(&event->hw.prev_count); |
4574910e | 744 | barrier(); |
cdd6c482 | 745 | val = read_pmc(event->hw.idx); |
86c74ab3 EM |
746 | delta = check_and_compute_delta(prev, val); |
747 | if (!delta) | |
748 | return; | |
e7850595 | 749 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 750 | |
e7850595 PZ |
751 | local64_add(delta, &event->count); |
752 | local64_sub(delta, &event->hw.period_left); | |
4574910e PM |
753 | } |
754 | ||
ab7ef2e5 PM |
755 | /* |
756 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
757 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 758 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
759 | */ |
760 | static int is_limited_pmc(int pmcnum) | |
761 | { | |
0bbd0d4b PM |
762 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
763 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
764 | } |
765 | ||
a8f90e90 | 766 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
767 | unsigned long pmc5, unsigned long pmc6) |
768 | { | |
cdd6c482 | 769 | struct perf_event *event; |
ab7ef2e5 PM |
770 | u64 val, prev, delta; |
771 | int i; | |
772 | ||
773 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 774 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 775 | if (!event->hw.idx) |
ab7ef2e5 | 776 | continue; |
cdd6c482 | 777 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 778 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 779 | event->hw.idx = 0; |
86c74ab3 EM |
780 | delta = check_and_compute_delta(prev, val); |
781 | if (delta) | |
782 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
783 | } |
784 | } | |
785 | ||
a8f90e90 | 786 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
787 | unsigned long pmc5, unsigned long pmc6) |
788 | { | |
cdd6c482 | 789 | struct perf_event *event; |
86c74ab3 | 790 | u64 val, prev; |
ab7ef2e5 PM |
791 | int i; |
792 | ||
793 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 794 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
795 | event->hw.idx = cpuhw->limited_hwidx[i]; |
796 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
797 | prev = local64_read(&event->hw.prev_count); |
798 | if (check_and_compute_delta(prev, val)) | |
799 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 800 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
801 | } |
802 | } | |
803 | ||
804 | /* | |
cdd6c482 | 805 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 806 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
807 | * other events. We try to keep the values from the limited |
808 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 809 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
810 | * the limited events as small and consistent as possible. |
811 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
812 | * both, and always in the same order, to minimize variability, |
813 | * and do it inside the same asm that writes MMCR0. | |
814 | */ | |
cdd6c482 | 815 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
816 | { |
817 | unsigned long pmc5, pmc6; | |
818 | ||
819 | if (!cpuhw->n_limited) { | |
820 | mtspr(SPRN_MMCR0, mmcr0); | |
821 | return; | |
822 | } | |
823 | ||
824 | /* | |
825 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
826 | * To ensure we don't get a performance monitor interrupt |
827 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 828 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 829 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
830 | */ |
831 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
832 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
833 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
834 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
835 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
836 | ||
837 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 838 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 839 | else |
a8f90e90 | 840 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
841 | |
842 | /* | |
cdd6c482 | 843 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
844 | * enable bits, if necessary. |
845 | */ | |
846 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
847 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
848 | } |
849 | ||
4574910e | 850 | /* |
cdd6c482 IM |
851 | * Disable all events to prevent PMU interrupts and to allow |
852 | * events to be added or removed. | |
4574910e | 853 | */ |
a4eaf7f1 | 854 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 855 | { |
cdd6c482 | 856 | struct cpu_hw_events *cpuhw; |
378a6ee9 | 857 | unsigned long flags, val; |
4574910e | 858 | |
f36a1a13 PM |
859 | if (!ppmu) |
860 | return; | |
4574910e | 861 | local_irq_save(flags); |
cdd6c482 | 862 | cpuhw = &__get_cpu_var(cpu_hw_events); |
4574910e | 863 | |
448d64f8 | 864 | if (!cpuhw->disabled) { |
01d0287f PM |
865 | /* |
866 | * Check if we ever enabled the PMU on this cpu. | |
867 | */ | |
868 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 869 | ppc_enable_pmcs(); |
01d0287f PM |
870 | cpuhw->pmcs_enabled = 1; |
871 | } | |
872 | ||
378a6ee9 | 873 | /* |
7a7a41f9 | 874 | * Set the 'freeze counters' bit, clear PMAO/FC56. |
378a6ee9 ME |
875 | */ |
876 | val = mfspr(SPRN_MMCR0); | |
877 | val |= MMCR0_FC; | |
7a7a41f9 | 878 | val &= ~(MMCR0_PMAO | MMCR0_FC56); |
378a6ee9 ME |
879 | |
880 | /* | |
881 | * The barrier is to make sure the mtspr has been | |
882 | * executed and the PMU has frozen the events etc. | |
883 | * before we return. | |
884 | */ | |
885 | write_mmcr0(cpuhw, val); | |
886 | mb(); | |
887 | ||
f708223d PM |
888 | /* |
889 | * Disable instruction sampling if it was enabled | |
890 | */ | |
891 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
892 | mtspr(SPRN_MMCRA, | |
893 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
894 | mb(); | |
895 | } | |
896 | ||
378a6ee9 ME |
897 | cpuhw->disabled = 1; |
898 | cpuhw->n_added = 0; | |
4574910e PM |
899 | } |
900 | local_irq_restore(flags); | |
4574910e PM |
901 | } |
902 | ||
903 | /* | |
cdd6c482 IM |
904 | * Re-enable all events if disable == 0. |
905 | * If we were previously disabled and events were added, then | |
4574910e PM |
906 | * put the new config on the PMU. |
907 | */ | |
a4eaf7f1 | 908 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 909 | { |
cdd6c482 IM |
910 | struct perf_event *event; |
911 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
912 | unsigned long flags; |
913 | long i; | |
914 | unsigned long val; | |
915 | s64 left; | |
cdd6c482 | 916 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
917 | int n_lim; |
918 | int idx; | |
4574910e | 919 | |
f36a1a13 PM |
920 | if (!ppmu) |
921 | return; | |
0a48843d | 922 | |
4574910e | 923 | local_irq_save(flags); |
0a48843d | 924 | |
cdd6c482 | 925 | cpuhw = &__get_cpu_var(cpu_hw_events); |
0a48843d ME |
926 | if (!cpuhw->disabled) |
927 | goto out; | |
928 | ||
4574910e PM |
929 | cpuhw->disabled = 0; |
930 | ||
931 | /* | |
cdd6c482 | 932 | * If we didn't change anything, or only removed events, |
4574910e PM |
933 | * no need to recalculate MMCR* settings and reset the PMCs. |
934 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 935 | * (possibly updated for removal of events). |
4574910e PM |
936 | */ |
937 | if (!cpuhw->n_added) { | |
f708223d | 938 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 939 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
cdd6c482 | 940 | if (cpuhw->n_events == 0) |
a6dbf93a | 941 | ppc_set_pmu_inuse(0); |
f708223d | 942 | goto out_enable; |
4574910e PM |
943 | } |
944 | ||
945 | /* | |
cdd6c482 | 946 | * Compute MMCR* values for the new set of events |
4574910e | 947 | */ |
cdd6c482 | 948 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
4574910e PM |
949 | cpuhw->mmcr)) { |
950 | /* shouldn't ever get here */ | |
951 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
952 | goto out; | |
953 | } | |
954 | ||
0475f9ea PM |
955 | /* |
956 | * Add in MMCR0 freeze bits corresponding to the | |
cdd6c482 IM |
957 | * attr.exclude_* bits for the first event. |
958 | * We have already checked that all events have the | |
959 | * same values for these bits as the first event. | |
0475f9ea | 960 | */ |
cdd6c482 IM |
961 | event = cpuhw->event[0]; |
962 | if (event->attr.exclude_user) | |
0475f9ea | 963 | cpuhw->mmcr[0] |= MMCR0_FCP; |
cdd6c482 IM |
964 | if (event->attr.exclude_kernel) |
965 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
966 | if (event->attr.exclude_hv) | |
0475f9ea PM |
967 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
968 | ||
4574910e PM |
969 | /* |
970 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
971 | * bit set and set the hardware events to their initial values. |
972 | * Then unfreeze the events. | |
4574910e | 973 | */ |
a6dbf93a | 974 | ppc_set_pmu_inuse(1); |
f708223d | 975 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
976 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
977 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
978 | | MMCR0_FC); | |
979 | ||
980 | /* | |
cdd6c482 | 981 | * Read off any pre-existing events that need to move |
4574910e PM |
982 | * to another PMC. |
983 | */ | |
cdd6c482 IM |
984 | for (i = 0; i < cpuhw->n_events; ++i) { |
985 | event = cpuhw->event[i]; | |
986 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
987 | power_pmu_read(event); | |
988 | write_pmc(event->hw.idx, 0); | |
989 | event->hw.idx = 0; | |
4574910e PM |
990 | } |
991 | } | |
992 | ||
993 | /* | |
cdd6c482 | 994 | * Initialize the PMCs for all the new and moved events. |
4574910e | 995 | */ |
ab7ef2e5 | 996 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
997 | for (i = 0; i < cpuhw->n_events; ++i) { |
998 | event = cpuhw->event[i]; | |
999 | if (event->hw.idx) | |
4574910e | 1000 | continue; |
ab7ef2e5 PM |
1001 | idx = hwc_index[i] + 1; |
1002 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 1003 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
1004 | cpuhw->limited_hwidx[n_lim] = idx; |
1005 | ++n_lim; | |
1006 | continue; | |
1007 | } | |
4574910e | 1008 | val = 0; |
cdd6c482 | 1009 | if (event->hw.sample_period) { |
e7850595 | 1010 | left = local64_read(&event->hw.period_left); |
4574910e PM |
1011 | if (left < 0x80000000L) |
1012 | val = 0x80000000L - left; | |
1013 | } | |
e7850595 | 1014 | local64_set(&event->hw.prev_count, val); |
cdd6c482 | 1015 | event->hw.idx = idx; |
a4eaf7f1 PZ |
1016 | if (event->hw.state & PERF_HES_STOPPED) |
1017 | val = 0; | |
ab7ef2e5 | 1018 | write_pmc(idx, val); |
cdd6c482 | 1019 | perf_event_update_userpage(event); |
4574910e | 1020 | } |
ab7ef2e5 | 1021 | cpuhw->n_limited = n_lim; |
4574910e | 1022 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
1023 | |
1024 | out_enable: | |
1025 | mb(); | |
ab7ef2e5 | 1026 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1027 | |
f708223d PM |
1028 | /* |
1029 | * Enable instruction sampling if necessary | |
1030 | */ | |
1031 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1032 | mb(); | |
1033 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
1034 | } | |
1035 | ||
4574910e | 1036 | out: |
3925f46b AK |
1037 | if (cpuhw->bhrb_users) |
1038 | ppmu->config_bhrb(cpuhw->bhrb_filter); | |
1039 | ||
4574910e PM |
1040 | local_irq_restore(flags); |
1041 | } | |
1042 | ||
cdd6c482 IM |
1043 | static int collect_events(struct perf_event *group, int max_count, |
1044 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 1045 | unsigned int *flags) |
4574910e PM |
1046 | { |
1047 | int n = 0; | |
cdd6c482 | 1048 | struct perf_event *event; |
4574910e | 1049 | |
cdd6c482 | 1050 | if (!is_software_event(group)) { |
4574910e PM |
1051 | if (n >= max_count) |
1052 | return -1; | |
1053 | ctrs[n] = group; | |
cdd6c482 | 1054 | flags[n] = group->hw.event_base; |
4574910e PM |
1055 | events[n++] = group->hw.config; |
1056 | } | |
a8f90e90 | 1057 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
1058 | if (!is_software_event(event) && |
1059 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
1060 | if (n >= max_count) |
1061 | return -1; | |
cdd6c482 IM |
1062 | ctrs[n] = event; |
1063 | flags[n] = event->hw.event_base; | |
1064 | events[n++] = event->hw.config; | |
4574910e PM |
1065 | } |
1066 | } | |
1067 | return n; | |
1068 | } | |
1069 | ||
4574910e | 1070 | /* |
cdd6c482 IM |
1071 | * Add a event to the PMU. |
1072 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 1073 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
1074 | * actual work of reconfiguring the PMU. |
1075 | */ | |
a4eaf7f1 | 1076 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 1077 | { |
cdd6c482 | 1078 | struct cpu_hw_events *cpuhw; |
4574910e | 1079 | unsigned long flags; |
4574910e PM |
1080 | int n0; |
1081 | int ret = -EAGAIN; | |
1082 | ||
1083 | local_irq_save(flags); | |
33696fc0 | 1084 | perf_pmu_disable(event->pmu); |
4574910e PM |
1085 | |
1086 | /* | |
cdd6c482 | 1087 | * Add the event to the list (if there is room) |
4574910e PM |
1088 | * and check whether the total set is still feasible. |
1089 | */ | |
cdd6c482 IM |
1090 | cpuhw = &__get_cpu_var(cpu_hw_events); |
1091 | n0 = cpuhw->n_events; | |
a8f90e90 | 1092 | if (n0 >= ppmu->n_counter) |
4574910e | 1093 | goto out; |
cdd6c482 IM |
1094 | cpuhw->event[n0] = event; |
1095 | cpuhw->events[n0] = event->hw.config; | |
1096 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 1097 | |
f53d168c | 1098 | /* |
1099 | * This event may have been disabled/stopped in record_and_restart() | |
1100 | * because we exceeded the ->event_limit. If re-starting the event, | |
1101 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
1102 | * notification is re-enabled. | |
1103 | */ | |
a4eaf7f1 PZ |
1104 | if (!(ef_flags & PERF_EF_START)) |
1105 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 1106 | else |
1107 | event->hw.state = 0; | |
a4eaf7f1 | 1108 | |
8e6d5573 LM |
1109 | /* |
1110 | * If group events scheduling transaction was started, | |
25985edc | 1111 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
1112 | * at commit time(->commit_txn) as a whole |
1113 | */ | |
8d2cacbb | 1114 | if (cpuhw->group_flag & PERF_EVENT_TXN) |
8e6d5573 LM |
1115 | goto nocheck; |
1116 | ||
cdd6c482 | 1117 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 1118 | goto out; |
e51ee31e | 1119 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 1120 | goto out; |
cdd6c482 | 1121 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
1122 | |
1123 | nocheck: | |
cdd6c482 | 1124 | ++cpuhw->n_events; |
4574910e PM |
1125 | ++cpuhw->n_added; |
1126 | ||
1127 | ret = 0; | |
1128 | out: | |
3925f46b AK |
1129 | if (has_branch_stack(event)) |
1130 | power_pmu_bhrb_enable(event); | |
1131 | ||
33696fc0 | 1132 | perf_pmu_enable(event->pmu); |
4574910e PM |
1133 | local_irq_restore(flags); |
1134 | return ret; | |
1135 | } | |
1136 | ||
1137 | /* | |
cdd6c482 | 1138 | * Remove a event from the PMU. |
4574910e | 1139 | */ |
a4eaf7f1 | 1140 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 1141 | { |
cdd6c482 | 1142 | struct cpu_hw_events *cpuhw; |
4574910e | 1143 | long i; |
4574910e PM |
1144 | unsigned long flags; |
1145 | ||
1146 | local_irq_save(flags); | |
33696fc0 | 1147 | perf_pmu_disable(event->pmu); |
4574910e | 1148 | |
cdd6c482 IM |
1149 | power_pmu_read(event); |
1150 | ||
1151 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1152 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1153 | if (event == cpuhw->event[i]) { | |
219a92a4 | 1154 | while (++i < cpuhw->n_events) { |
cdd6c482 | 1155 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
1156 | cpuhw->events[i-1] = cpuhw->events[i]; |
1157 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
1158 | } | |
cdd6c482 IM |
1159 | --cpuhw->n_events; |
1160 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
1161 | if (event->hw.idx) { | |
1162 | write_pmc(event->hw.idx, 0); | |
1163 | event->hw.idx = 0; | |
ab7ef2e5 | 1164 | } |
cdd6c482 | 1165 | perf_event_update_userpage(event); |
4574910e PM |
1166 | break; |
1167 | } | |
1168 | } | |
ab7ef2e5 | 1169 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 1170 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
1171 | break; |
1172 | if (i < cpuhw->n_limited) { | |
1173 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 1174 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
1175 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
1176 | } | |
1177 | --cpuhw->n_limited; | |
1178 | } | |
cdd6c482 IM |
1179 | if (cpuhw->n_events == 0) { |
1180 | /* disable exceptions if no events are running */ | |
4574910e PM |
1181 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
1182 | } | |
1183 | ||
3925f46b AK |
1184 | if (has_branch_stack(event)) |
1185 | power_pmu_bhrb_disable(event); | |
1186 | ||
33696fc0 | 1187 | perf_pmu_enable(event->pmu); |
4574910e PM |
1188 | local_irq_restore(flags); |
1189 | } | |
1190 | ||
8a7b8cb9 | 1191 | /* |
a4eaf7f1 PZ |
1192 | * POWER-PMU does not support disabling individual counters, hence |
1193 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 1194 | */ |
a4eaf7f1 PZ |
1195 | |
1196 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 1197 | { |
8a7b8cb9 | 1198 | unsigned long flags; |
a4eaf7f1 | 1199 | s64 left; |
9a45a940 | 1200 | unsigned long val; |
8a7b8cb9 | 1201 | |
cdd6c482 | 1202 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 1203 | return; |
a4eaf7f1 PZ |
1204 | |
1205 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
1206 | return; | |
1207 | ||
1208 | if (ef_flags & PERF_EF_RELOAD) | |
1209 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1210 | ||
1211 | local_irq_save(flags); | |
1212 | perf_pmu_disable(event->pmu); | |
1213 | ||
1214 | event->hw.state = 0; | |
1215 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
1216 | |
1217 | val = 0; | |
1218 | if (left < 0x80000000L) | |
1219 | val = 0x80000000L - left; | |
1220 | ||
1221 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1222 | |
1223 | perf_event_update_userpage(event); | |
1224 | perf_pmu_enable(event->pmu); | |
1225 | local_irq_restore(flags); | |
1226 | } | |
1227 | ||
1228 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1229 | { | |
1230 | unsigned long flags; | |
1231 | ||
1232 | if (!event->hw.idx || !event->hw.sample_period) | |
1233 | return; | |
1234 | ||
1235 | if (event->hw.state & PERF_HES_STOPPED) | |
1236 | return; | |
1237 | ||
8a7b8cb9 | 1238 | local_irq_save(flags); |
33696fc0 | 1239 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1240 | |
cdd6c482 | 1241 | power_pmu_read(event); |
a4eaf7f1 PZ |
1242 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1243 | write_pmc(event->hw.idx, 0); | |
1244 | ||
cdd6c482 | 1245 | perf_event_update_userpage(event); |
33696fc0 | 1246 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1247 | local_irq_restore(flags); |
1248 | } | |
1249 | ||
8e6d5573 LM |
1250 | /* |
1251 | * Start group events scheduling transaction | |
1252 | * Set the flag to make pmu::enable() not perform the | |
1253 | * schedulability test, it will be performed at commit time | |
1254 | */ | |
51b0fe39 | 1255 | void power_pmu_start_txn(struct pmu *pmu) |
8e6d5573 LM |
1256 | { |
1257 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1258 | ||
33696fc0 | 1259 | perf_pmu_disable(pmu); |
8d2cacbb | 1260 | cpuhw->group_flag |= PERF_EVENT_TXN; |
8e6d5573 LM |
1261 | cpuhw->n_txn_start = cpuhw->n_events; |
1262 | } | |
1263 | ||
1264 | /* | |
1265 | * Stop group events scheduling transaction | |
1266 | * Clear the flag and pmu::enable() will perform the | |
1267 | * schedulability test. | |
1268 | */ | |
51b0fe39 | 1269 | void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 LM |
1270 | { |
1271 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1272 | ||
8d2cacbb | 1273 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1274 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1275 | } |
1276 | ||
1277 | /* | |
1278 | * Commit group events scheduling transaction | |
1279 | * Perform the group schedulability test as a whole | |
1280 | * Return 0 if success | |
1281 | */ | |
51b0fe39 | 1282 | int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1283 | { |
1284 | struct cpu_hw_events *cpuhw; | |
1285 | long i, n; | |
1286 | ||
1287 | if (!ppmu) | |
1288 | return -EAGAIN; | |
1289 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1290 | n = cpuhw->n_events; | |
1291 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1292 | return -EAGAIN; | |
1293 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1294 | if (i < 0) | |
1295 | return -EAGAIN; | |
1296 | ||
1297 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1298 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1299 | ||
8d2cacbb | 1300 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1301 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1302 | return 0; |
1303 | } | |
1304 | ||
ab7ef2e5 | 1305 | /* |
cdd6c482 | 1306 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1307 | * or 0 if not. |
cdd6c482 | 1308 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1309 | * that a limited PMC can count, doesn't require interrupts, and |
1310 | * doesn't exclude any processor mode. | |
1311 | */ | |
cdd6c482 | 1312 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1313 | unsigned int flags) |
1314 | { | |
1315 | int n; | |
ef923214 | 1316 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1317 | |
cdd6c482 IM |
1318 | if (event->attr.exclude_user |
1319 | || event->attr.exclude_kernel | |
1320 | || event->attr.exclude_hv | |
1321 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1322 | return 0; |
1323 | ||
1324 | if (ppmu->limited_pmc_event(ev)) | |
1325 | return 1; | |
1326 | ||
1327 | /* | |
cdd6c482 | 1328 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1329 | * see if any alternative code goes on a limited PMC. |
1330 | */ | |
1331 | if (!ppmu->get_alternatives) | |
1332 | return 0; | |
1333 | ||
1334 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1335 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1336 | |
ef923214 | 1337 | return n > 0; |
ab7ef2e5 PM |
1338 | } |
1339 | ||
1340 | /* | |
cdd6c482 IM |
1341 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1342 | * and return the event_id code, or 0 if there is no such alternative. | |
1343 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1344 | */ |
ef923214 | 1345 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1346 | { |
ef923214 | 1347 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1348 | int n; |
1349 | ||
1350 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1351 | n = ppmu->get_alternatives(ev, flags, alt); | |
1352 | if (!n) | |
1353 | return 0; | |
1354 | return alt[0]; | |
1355 | } | |
1356 | ||
cdd6c482 IM |
1357 | /* Number of perf_events counting hardware events */ |
1358 | static atomic_t num_events; | |
7595d63b PM |
1359 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1360 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1361 | ||
1362 | /* | |
cdd6c482 | 1363 | * Release the PMU if this is the last perf_event. |
7595d63b | 1364 | */ |
cdd6c482 | 1365 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1366 | { |
cdd6c482 | 1367 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1368 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1369 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1370 | release_pmc_hardware(); |
1371 | mutex_unlock(&pmc_reserve_mutex); | |
1372 | } | |
1373 | } | |
1374 | ||
106b506c | 1375 | /* |
cdd6c482 | 1376 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1377 | */ |
1378 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1379 | { | |
1380 | unsigned long type, op, result; | |
1381 | int ev; | |
1382 | ||
1383 | if (!ppmu->cache_events) | |
1384 | return -EINVAL; | |
1385 | ||
1386 | /* unpack config */ | |
1387 | type = config & 0xff; | |
1388 | op = (config >> 8) & 0xff; | |
1389 | result = (config >> 16) & 0xff; | |
1390 | ||
1391 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1392 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1393 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1394 | return -EINVAL; | |
1395 | ||
1396 | ev = (*ppmu->cache_events)[type][op][result]; | |
1397 | if (ev == 0) | |
1398 | return -EOPNOTSUPP; | |
1399 | if (ev == -1) | |
1400 | return -EINVAL; | |
1401 | *eventp = ev; | |
1402 | return 0; | |
1403 | } | |
1404 | ||
b0a873eb | 1405 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1406 | { |
ef923214 PM |
1407 | u64 ev; |
1408 | unsigned long flags; | |
cdd6c482 IM |
1409 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1410 | u64 events[MAX_HWEVENTS]; | |
1411 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1412 | int n; |
7595d63b | 1413 | int err; |
cdd6c482 | 1414 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1415 | |
1416 | if (!ppmu) | |
b0a873eb PZ |
1417 | return -ENOENT; |
1418 | ||
3925f46b AK |
1419 | if (has_branch_stack(event)) { |
1420 | /* PMU has BHRB enabled */ | |
1421 | if (!(ppmu->flags & PPMU_BHRB)) | |
1422 | return -EOPNOTSUPP; | |
1423 | } | |
2481c5fa | 1424 | |
cdd6c482 | 1425 | switch (event->attr.type) { |
106b506c | 1426 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1427 | ev = event->attr.config; |
9aaa131a | 1428 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1429 | return -EOPNOTSUPP; |
4574910e | 1430 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1431 | break; |
1432 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1433 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1434 | if (err) |
b0a873eb | 1435 | return err; |
106b506c PM |
1436 | break; |
1437 | case PERF_TYPE_RAW: | |
cdd6c482 | 1438 | ev = event->attr.config; |
106b506c | 1439 | break; |
90c8f954 | 1440 | default: |
b0a873eb | 1441 | return -ENOENT; |
4574910e | 1442 | } |
b0a873eb | 1443 | |
cdd6c482 IM |
1444 | event->hw.config_base = ev; |
1445 | event->hw.idx = 0; | |
4574910e | 1446 | |
0475f9ea PM |
1447 | /* |
1448 | * If we are not running on a hypervisor, force the | |
1449 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1450 | * the user set it to. |
0475f9ea PM |
1451 | */ |
1452 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1453 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1454 | |
1455 | /* | |
cdd6c482 | 1456 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1457 | * PM_RUN_* events interchangeably with their non RUN_* |
1458 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1459 | * XXX we should check if the task is an idle task. | |
1460 | */ | |
1461 | flags = 0; | |
57fa7214 | 1462 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1463 | flags |= PPMU_ONLY_COUNT_RUN; |
1464 | ||
1465 | /* | |
cdd6c482 IM |
1466 | * If this machine has limited events, check whether this |
1467 | * event_id could go on a limited event. | |
ab7ef2e5 | 1468 | */ |
0bbd0d4b | 1469 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1470 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1471 | flags |= PPMU_LIMITED_PMC_OK; |
1472 | } else if (ppmu->limited_pmc_event(ev)) { | |
1473 | /* | |
cdd6c482 | 1474 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1475 | * but we can't use a limited PMC; see if any |
1476 | * alternative goes on a normal PMC. | |
1477 | */ | |
1478 | ev = normal_pmc_alternative(ev, flags); | |
1479 | if (!ev) | |
b0a873eb | 1480 | return -EINVAL; |
ab7ef2e5 PM |
1481 | } |
1482 | } | |
1483 | ||
4574910e PM |
1484 | /* |
1485 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1486 | * other hardware events in the group. We assume the event |
4574910e PM |
1487 | * hasn't been linked into its leader's sibling list at this point. |
1488 | */ | |
1489 | n = 0; | |
cdd6c482 | 1490 | if (event->group_leader != event) { |
a8f90e90 | 1491 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1492 | ctrs, events, cflags); |
4574910e | 1493 | if (n < 0) |
b0a873eb | 1494 | return -EINVAL; |
4574910e | 1495 | } |
0475f9ea | 1496 | events[n] = ev; |
cdd6c482 | 1497 | ctrs[n] = event; |
ab7ef2e5 PM |
1498 | cflags[n] = flags; |
1499 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1500 | return -EINVAL; |
e51ee31e | 1501 | |
cdd6c482 | 1502 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1503 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
3925f46b AK |
1504 | |
1505 | if (has_branch_stack(event)) { | |
1506 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( | |
1507 | event->attr.branch_sample_type); | |
1508 | ||
1509 | if(cpuhw->bhrb_filter == -1) | |
1510 | return -EOPNOTSUPP; | |
1511 | } | |
1512 | ||
cdd6c482 | 1513 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1514 | if (err) |
b0a873eb | 1515 | return -EINVAL; |
4574910e | 1516 | |
cdd6c482 IM |
1517 | event->hw.config = events[n]; |
1518 | event->hw.event_base = cflags[n]; | |
1519 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1520 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b PM |
1521 | |
1522 | /* | |
1523 | * See if we need to reserve the PMU. | |
cdd6c482 | 1524 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1525 | * mutex to ensure that we don't race with another task doing |
1526 | * reserve_pmc_hardware or release_pmc_hardware. | |
1527 | */ | |
1528 | err = 0; | |
cdd6c482 | 1529 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1530 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1531 | if (atomic_read(&num_events) == 0 && |
1532 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1533 | err = -EBUSY; |
1534 | else | |
cdd6c482 | 1535 | atomic_inc(&num_events); |
7595d63b PM |
1536 | mutex_unlock(&pmc_reserve_mutex); |
1537 | } | |
cdd6c482 | 1538 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1539 | |
b0a873eb | 1540 | return err; |
4574910e PM |
1541 | } |
1542 | ||
35edc2a5 PZ |
1543 | static int power_pmu_event_idx(struct perf_event *event) |
1544 | { | |
1545 | return event->hw.idx; | |
1546 | } | |
1547 | ||
1c53a270 SB |
1548 | ssize_t power_events_sysfs_show(struct device *dev, |
1549 | struct device_attribute *attr, char *page) | |
1550 | { | |
1551 | struct perf_pmu_events_attr *pmu_attr; | |
1552 | ||
1553 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
1554 | ||
1555 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
1556 | } | |
1557 | ||
b0a873eb | 1558 | struct pmu power_pmu = { |
a4eaf7f1 PZ |
1559 | .pmu_enable = power_pmu_enable, |
1560 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1561 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1562 | .add = power_pmu_add, |
1563 | .del = power_pmu_del, | |
1564 | .start = power_pmu_start, | |
1565 | .stop = power_pmu_stop, | |
b0a873eb | 1566 | .read = power_pmu_read, |
b0a873eb PZ |
1567 | .start_txn = power_pmu_start_txn, |
1568 | .cancel_txn = power_pmu_cancel_txn, | |
1569 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1570 | .event_idx = power_pmu_event_idx, |
3925f46b | 1571 | .flush_branch_stack = power_pmu_flush_branch_stack, |
b0a873eb PZ |
1572 | }; |
1573 | ||
4574910e | 1574 | /* |
57c0c15b | 1575 | * A counter has overflowed; update its count and record |
4574910e PM |
1576 | * things if requested. Note that interrupts are hard-disabled |
1577 | * here so there is no possibility of being interrupted. | |
1578 | */ | |
cdd6c482 | 1579 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1580 | struct pt_regs *regs) |
4574910e | 1581 | { |
cdd6c482 | 1582 | u64 period = event->hw.sample_period; |
4574910e PM |
1583 | s64 prev, delta, left; |
1584 | int record = 0; | |
1585 | ||
a4eaf7f1 PZ |
1586 | if (event->hw.state & PERF_HES_STOPPED) { |
1587 | write_pmc(event->hw.idx, 0); | |
1588 | return; | |
1589 | } | |
1590 | ||
4574910e | 1591 | /* we don't have to worry about interrupts here */ |
e7850595 | 1592 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 1593 | delta = check_and_compute_delta(prev, val); |
e7850595 | 1594 | local64_add(delta, &event->count); |
4574910e PM |
1595 | |
1596 | /* | |
cdd6c482 | 1597 | * See if the total period for this event has expired, |
4574910e PM |
1598 | * and update for the next period. |
1599 | */ | |
1600 | val = 0; | |
e7850595 | 1601 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
1602 | if (delta == 0) |
1603 | left++; | |
60db5e09 | 1604 | if (period) { |
4574910e | 1605 | if (left <= 0) { |
60db5e09 | 1606 | left += period; |
4574910e | 1607 | if (left <= 0) |
60db5e09 | 1608 | left = period; |
e6878835 | 1609 | record = siar_valid(regs); |
4bca770e | 1610 | event->hw.last_period = event->hw.sample_period; |
4574910e | 1611 | } |
98fb1807 PM |
1612 | if (left < 0x80000000LL) |
1613 | val = 0x80000000LL - left; | |
4574910e | 1614 | } |
4574910e | 1615 | |
a4eaf7f1 PZ |
1616 | write_pmc(event->hw.idx, val); |
1617 | local64_set(&event->hw.prev_count, val); | |
1618 | local64_set(&event->hw.period_left, left); | |
1619 | perf_event_update_userpage(event); | |
1620 | ||
4574910e PM |
1621 | /* |
1622 | * Finally record data if requested. | |
1623 | */ | |
0bbd0d4b | 1624 | if (record) { |
dc1d628a PZ |
1625 | struct perf_sample_data data; |
1626 | ||
fd0d000b | 1627 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 1628 | |
cdd6c482 | 1629 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
1630 | perf_get_data_addr(regs, &data.addr); |
1631 | ||
3925f46b AK |
1632 | if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { |
1633 | struct cpu_hw_events *cpuhw; | |
1634 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1635 | power_pmu_bhrb_read(cpuhw); | |
1636 | data.br_stack = &cpuhw->bhrb_stack; | |
1637 | } | |
1638 | ||
a8b0ca17 | 1639 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1640 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
1641 | } |
1642 | } | |
1643 | ||
1644 | /* | |
1645 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 1646 | * for an event_id. |
0bbd0d4b PM |
1647 | */ |
1648 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1649 | { | |
98fb1807 | 1650 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 1651 | |
98fb1807 PM |
1652 | if (flags) |
1653 | return flags; | |
cdd6c482 IM |
1654 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
1655 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
1656 | } |
1657 | ||
1658 | /* | |
1659 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 1660 | * for an event_id. |
0bbd0d4b PM |
1661 | */ |
1662 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1663 | { | |
33904054 | 1664 | bool use_siar = regs_use_siar(regs); |
0bbd0d4b | 1665 | |
e6878835 | 1666 | if (use_siar && siar_valid(regs)) |
75382aa7 | 1667 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 1668 | else if (use_siar) |
1669 | return 0; // no valid instruction pointer | |
75382aa7 | 1670 | else |
1ce447b9 | 1671 | return regs->nip; |
4574910e PM |
1672 | } |
1673 | ||
bc09c219 | 1674 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 1675 | { |
0837e324 AB |
1676 | /* |
1677 | * Events on POWER7 can roll back if a speculative event doesn't | |
1678 | * eventually complete. Unfortunately in some rare cases they will | |
1679 | * raise a performance monitor exception. We need to catch this to | |
1680 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
1681 | * cycles from overflow. | |
1682 | * | |
1683 | * We only do this if the first pass fails to find any overflowing | |
1684 | * PMCs because a user might set a period of less than 256 and we | |
1685 | * don't want to mistakenly reset them. | |
1686 | */ | |
bc09c219 MN |
1687 | if ((0x80000000 - val) <= 256) |
1688 | return true; | |
1689 | ||
1690 | return false; | |
1691 | } | |
1692 | ||
1693 | static bool pmc_overflow(unsigned long val) | |
1694 | { | |
1695 | if ((int)val < 0) | |
0837e324 AB |
1696 | return true; |
1697 | ||
1698 | return false; | |
1699 | } | |
1700 | ||
4574910e PM |
1701 | /* |
1702 | * Performance monitor interrupt stuff | |
1703 | */ | |
cdd6c482 | 1704 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 1705 | { |
bc09c219 | 1706 | int i, j; |
cdd6c482 IM |
1707 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); |
1708 | struct perf_event *event; | |
bc09c219 MN |
1709 | unsigned long val[8]; |
1710 | int found, active; | |
ca8f2d7f PM |
1711 | int nmi; |
1712 | ||
ab7ef2e5 | 1713 | if (cpuhw->n_limited) |
a8f90e90 | 1714 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
1715 | mfspr(SPRN_PMC6)); |
1716 | ||
98fb1807 | 1717 | perf_read_regs(regs); |
0bbd0d4b | 1718 | |
98fb1807 | 1719 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
1720 | if (nmi) |
1721 | nmi_enter(); | |
1722 | else | |
1723 | irq_enter(); | |
4574910e | 1724 | |
bc09c219 MN |
1725 | /* Read all the PMCs since we'll need them a bunch of times */ |
1726 | for (i = 0; i < ppmu->n_counter; ++i) | |
1727 | val[i] = read_pmc(i + 1); | |
1728 | ||
1729 | /* Try to find what caused the IRQ */ | |
1730 | found = 0; | |
1731 | for (i = 0; i < ppmu->n_counter; ++i) { | |
1732 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 1733 | continue; |
bc09c219 MN |
1734 | if (is_limited_pmc(i + 1)) |
1735 | continue; /* these won't generate IRQs */ | |
1736 | /* | |
1737 | * We've found one that's overflowed. For active | |
1738 | * counters we need to log this. For inactive | |
1739 | * counters, we need to reset it anyway | |
1740 | */ | |
1741 | found = 1; | |
1742 | active = 0; | |
1743 | for (j = 0; j < cpuhw->n_events; ++j) { | |
1744 | event = cpuhw->event[j]; | |
1745 | if (event->hw.idx == (i + 1)) { | |
1746 | active = 1; | |
1747 | record_and_restart(event, val[i], regs); | |
1748 | break; | |
1749 | } | |
4574910e | 1750 | } |
bc09c219 MN |
1751 | if (!active) |
1752 | /* reset non active counters that have overflowed */ | |
1753 | write_pmc(i + 1, 0); | |
4574910e | 1754 | } |
bc09c219 MN |
1755 | if (!found && pvr_version_is(PVR_POWER7)) { |
1756 | /* check active counters for special buggy p7 overflow */ | |
1757 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1758 | event = cpuhw->event[i]; | |
1759 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 1760 | continue; |
bc09c219 MN |
1761 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
1762 | /* event has overflowed in a buggy way*/ | |
1763 | found = 1; | |
1764 | record_and_restart(event, | |
1765 | val[event->hw.idx - 1], | |
1766 | regs); | |
1767 | } | |
4574910e PM |
1768 | } |
1769 | } | |
6772faa1 | 1770 | if (!found && !nmi && printk_ratelimit()) |
bc09c219 | 1771 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); |
4574910e PM |
1772 | |
1773 | /* | |
1774 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 1775 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 1776 | * and thus allow interrupts to occur again. |
cdd6c482 | 1777 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
1778 | * we get back out of this interrupt. |
1779 | */ | |
ab7ef2e5 | 1780 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1781 | |
ca8f2d7f PM |
1782 | if (nmi) |
1783 | nmi_exit(); | |
1784 | else | |
db4fb5ac | 1785 | irq_exit(); |
4574910e PM |
1786 | } |
1787 | ||
3f6da390 | 1788 | static void power_pmu_setup(int cpu) |
01d0287f | 1789 | { |
cdd6c482 | 1790 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 1791 | |
f36a1a13 PM |
1792 | if (!ppmu) |
1793 | return; | |
01d0287f PM |
1794 | memset(cpuhw, 0, sizeof(*cpuhw)); |
1795 | cpuhw->mmcr[0] = MMCR0_FC; | |
1796 | } | |
1797 | ||
061d19f2 | 1798 | static int |
85cfabbc | 1799 | power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
3f6da390 PZ |
1800 | { |
1801 | unsigned int cpu = (long)hcpu; | |
1802 | ||
1803 | switch (action & ~CPU_TASKS_FROZEN) { | |
1804 | case CPU_UP_PREPARE: | |
1805 | power_pmu_setup(cpu); | |
1806 | break; | |
1807 | ||
1808 | default: | |
1809 | break; | |
1810 | } | |
1811 | ||
1812 | return NOTIFY_OK; | |
1813 | } | |
1814 | ||
061d19f2 | 1815 | int register_power_pmu(struct power_pmu *pmu) |
4574910e | 1816 | { |
079b3c56 PM |
1817 | if (ppmu) |
1818 | return -EBUSY; /* something's already registered */ | |
1819 | ||
1820 | ppmu = pmu; | |
1821 | pr_info("%s performance monitor hardware support registered\n", | |
1822 | pmu->name); | |
d095cd46 | 1823 | |
1c53a270 SB |
1824 | power_pmu.attr_groups = ppmu->attr_groups; |
1825 | ||
98fb1807 | 1826 | #ifdef MSR_HV |
d095cd46 PM |
1827 | /* |
1828 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
1829 | */ | |
1830 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 1831 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 1832 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 1833 | |
2e80a82a | 1834 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 PZ |
1835 | perf_cpu_notifier(power_pmu_notifier); |
1836 | ||
4574910e PM |
1837 | return 0; |
1838 | } |