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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
69123184 | 16 | #include <linux/uaccess.h> |
4574910e PM |
17 | #include <asm/reg.h> |
18 | #include <asm/pmc.h> | |
01d0287f | 19 | #include <asm/machdep.h> |
0475f9ea | 20 | #include <asm/firmware.h> |
0bbd0d4b | 21 | #include <asm/ptrace.h> |
69123184 | 22 | #include <asm/code-patching.h> |
4574910e | 23 | |
3925f46b AK |
24 | #define BHRB_MAX_ENTRIES 32 |
25 | #define BHRB_TARGET 0x0000000000000002 | |
26 | #define BHRB_PREDICTION 0x0000000000000001 | |
27 | #define BHRB_EA 0xFFFFFFFFFFFFFFFC | |
28 | ||
cdd6c482 IM |
29 | struct cpu_hw_events { |
30 | int n_events; | |
4574910e PM |
31 | int n_percpu; |
32 | int disabled; | |
33 | int n_added; | |
ab7ef2e5 PM |
34 | int n_limited; |
35 | u8 pmcs_enabled; | |
cdd6c482 IM |
36 | struct perf_event *event[MAX_HWEVENTS]; |
37 | u64 events[MAX_HWEVENTS]; | |
38 | unsigned int flags[MAX_HWEVENTS]; | |
448d64f8 | 39 | unsigned long mmcr[3]; |
a8f90e90 PM |
40 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
41 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
42 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
43 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
44 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 LM |
45 | |
46 | unsigned int group_flag; | |
47 | int n_txn_start; | |
3925f46b AK |
48 | |
49 | /* BHRB bits */ | |
50 | u64 bhrb_filter; /* BHRB HW branch filter */ | |
51 | int bhrb_users; | |
52 | void *bhrb_context; | |
53 | struct perf_branch_stack bhrb_stack; | |
54 | struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; | |
4574910e | 55 | }; |
3925f46b | 56 | |
cdd6c482 | 57 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e PM |
58 | |
59 | struct power_pmu *ppmu; | |
60 | ||
d095cd46 | 61 | /* |
57c0c15b | 62 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
63 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
64 | * hypervisor bit set in the MSR, or if we are running on a processor | |
65 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
66 | * then we need to use the FCHV bit to ignore kernel events. | |
67 | */ | |
cdd6c482 | 68 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 69 | |
98fb1807 PM |
70 | /* |
71 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
72 | * and a few other names are different. | |
73 | */ | |
74 | #ifdef CONFIG_PPC32 | |
75 | ||
76 | #define MMCR0_FCHV 0 | |
77 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
378a6ee9 | 78 | #define MMCR0_PMAO 0 |
98fb1807 PM |
79 | |
80 | #define SPRN_MMCRA SPRN_MMCR2 | |
81 | #define MMCRA_SAMPLE_ENABLE 0 | |
82 | ||
83 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
84 | { | |
85 | return 0; | |
86 | } | |
98fb1807 PM |
87 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
88 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
89 | { | |
90 | return 0; | |
91 | } | |
75382aa7 AB |
92 | static inline void perf_read_regs(struct pt_regs *regs) |
93 | { | |
94 | regs->result = 0; | |
95 | } | |
98fb1807 PM |
96 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
97 | { | |
98 | return 0; | |
99 | } | |
100 | ||
e6878835 | 101 | static inline int siar_valid(struct pt_regs *regs) |
102 | { | |
103 | return 1; | |
104 | } | |
105 | ||
d52f2dc4 MN |
106 | static inline void power_pmu_bhrb_enable(struct perf_event *event) {} |
107 | static inline void power_pmu_bhrb_disable(struct perf_event *event) {} | |
108 | void power_pmu_flush_branch_stack(void) {} | |
109 | static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} | |
98fb1807 PM |
110 | #endif /* CONFIG_PPC32 */ |
111 | ||
33904054 ME |
112 | static bool regs_use_siar(struct pt_regs *regs) |
113 | { | |
cbda6aa1 | 114 | return !!regs->result; |
33904054 ME |
115 | } |
116 | ||
98fb1807 PM |
117 | /* |
118 | * Things that are specific to 64-bit implementations. | |
119 | */ | |
120 | #ifdef CONFIG_PPC64 | |
121 | ||
122 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
123 | { | |
124 | unsigned long mmcra = regs->dsisr; | |
125 | ||
7a786832 | 126 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
127 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
128 | if (slot > 1) | |
129 | return 4 * (slot - 1); | |
130 | } | |
7a786832 | 131 | |
98fb1807 PM |
132 | return 0; |
133 | } | |
134 | ||
98fb1807 PM |
135 | /* |
136 | * The user wants a data address recorded. | |
137 | * If we're not doing instruction sampling, give them the SDAR | |
138 | * (sampled data address). If we are doing instruction sampling, then | |
139 | * only give them the SDAR if it corresponds to the instruction | |
58a032c3 ME |
140 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the |
141 | * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. | |
98fb1807 PM |
142 | */ |
143 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
144 | { | |
145 | unsigned long mmcra = regs->dsisr; | |
58a032c3 | 146 | bool sdar_valid; |
e6878835 | 147 | |
58a032c3 ME |
148 | if (ppmu->flags & PPMU_HAS_SIER) |
149 | sdar_valid = regs->dar & SIER_SDAR_VALID; | |
150 | else { | |
151 | unsigned long sdsync; | |
152 | ||
153 | if (ppmu->flags & PPMU_SIAR_VALID) | |
154 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
155 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
156 | sdsync = POWER6_MMCRA_SDSYNC; | |
157 | else | |
158 | sdsync = MMCRA_SDSYNC; | |
159 | ||
160 | sdar_valid = mmcra & sdsync; | |
161 | } | |
98fb1807 | 162 | |
58a032c3 | 163 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) |
98fb1807 PM |
164 | *addrp = mfspr(SPRN_SDAR); |
165 | } | |
166 | ||
5682c460 | 167 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
168 | { |
169 | unsigned long sihv = MMCRA_SIHV; | |
170 | ||
8f61aa32 ME |
171 | if (ppmu->flags & PPMU_HAS_SIER) |
172 | return !!(regs->dar & SIER_SIHV); | |
173 | ||
68b30bb9 AB |
174 | if (ppmu->flags & PPMU_ALT_SIPR) |
175 | sihv = POWER6_MMCRA_SIHV; | |
176 | ||
5682c460 | 177 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
178 | } |
179 | ||
5682c460 | 180 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
181 | { |
182 | unsigned long sipr = MMCRA_SIPR; | |
183 | ||
8f61aa32 ME |
184 | if (ppmu->flags & PPMU_HAS_SIER) |
185 | return !!(regs->dar & SIER_SIPR); | |
186 | ||
68b30bb9 AB |
187 | if (ppmu->flags & PPMU_ALT_SIPR) |
188 | sipr = POWER6_MMCRA_SIPR; | |
189 | ||
5682c460 | 190 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
191 | } |
192 | ||
1ce447b9 BH |
193 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
194 | { | |
195 | if (regs->msr & MSR_PR) | |
196 | return PERF_RECORD_MISC_USER; | |
197 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
198 | return PERF_RECORD_MISC_HYPERVISOR; | |
199 | return PERF_RECORD_MISC_KERNEL; | |
200 | } | |
201 | ||
98fb1807 PM |
202 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
203 | { | |
33904054 | 204 | bool use_siar = regs_use_siar(regs); |
98fb1807 | 205 | |
75382aa7 | 206 | if (!use_siar) |
1ce447b9 BH |
207 | return perf_flags_from_msr(regs); |
208 | ||
209 | /* | |
210 | * If we don't have flags in MMCRA, rather than using | |
211 | * the MSR, we intuit the flags from the address in | |
212 | * SIAR which should give slightly more reliable | |
213 | * results | |
214 | */ | |
cbda6aa1 | 215 | if (ppmu->flags & PPMU_NO_SIPR) { |
1ce447b9 BH |
216 | unsigned long siar = mfspr(SPRN_SIAR); |
217 | if (siar >= PAGE_OFFSET) | |
218 | return PERF_RECORD_MISC_KERNEL; | |
219 | return PERF_RECORD_MISC_USER; | |
220 | } | |
98fb1807 | 221 | |
7abb840b | 222 | /* PR has priority over HV, so order below is important */ |
5682c460 | 223 | if (regs_sipr(regs)) |
7abb840b | 224 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
225 | |
226 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 227 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 228 | |
7abb840b | 229 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
230 | } |
231 | ||
232 | /* | |
233 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
234 | * on each interrupt. | |
8f61aa32 | 235 | * Overload regs->dar to store SIER if we have it. |
75382aa7 AB |
236 | * Overload regs->result to specify whether we should use the MSR (result |
237 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
238 | */ |
239 | static inline void perf_read_regs(struct pt_regs *regs) | |
240 | { | |
75382aa7 AB |
241 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
242 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
243 | int use_siar; | |
244 | ||
5682c460 | 245 | regs->dsisr = mmcra; |
8f61aa32 | 246 | |
cbda6aa1 ME |
247 | if (ppmu->flags & PPMU_HAS_SIER) |
248 | regs->dar = mfspr(SPRN_SIER); | |
8f61aa32 | 249 | |
5c093efa AB |
250 | /* |
251 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
252 | * not valid. Use pt_regs. | |
253 | * | |
254 | * If it is a marked event use the SIAR. | |
255 | * | |
256 | * If the PMU doesn't update the SIAR for non marked events use | |
257 | * pt_regs. | |
258 | * | |
259 | * If the PMU has HV/PR flags then check to see if they | |
260 | * place the exception in userspace. If so, use pt_regs. In | |
261 | * continuous sampling mode the SIAR and the PMU exception are | |
262 | * not synchronised, so they may be many instructions apart. | |
263 | * This can result in confusing backtraces. We still want | |
264 | * hypervisor samples as well as samples in the kernel with | |
265 | * interrupts off hence the userspace check. | |
266 | */ | |
75382aa7 AB |
267 | if (TRAP(regs) != 0xf00) |
268 | use_siar = 0; | |
5c093efa AB |
269 | else if (marked) |
270 | use_siar = 1; | |
271 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
272 | use_siar = 0; | |
cbda6aa1 | 273 | else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) |
75382aa7 AB |
274 | use_siar = 0; |
275 | else | |
276 | use_siar = 1; | |
277 | ||
cbda6aa1 | 278 | regs->result = use_siar; |
98fb1807 PM |
279 | } |
280 | ||
281 | /* | |
282 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
283 | * it as an NMI. | |
284 | */ | |
285 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
286 | { | |
287 | return !regs->softe; | |
288 | } | |
289 | ||
e6878835 | 290 | /* |
291 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
292 | * must be sampled only if the SIAR-valid bit is set. | |
293 | * | |
294 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
295 | * bit, assume that SIAR is valid. | |
296 | */ | |
297 | static inline int siar_valid(struct pt_regs *regs) | |
298 | { | |
299 | unsigned long mmcra = regs->dsisr; | |
300 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
301 | ||
58a032c3 ME |
302 | if (marked) { |
303 | if (ppmu->flags & PPMU_HAS_SIER) | |
304 | return regs->dar & SIER_SIAR_VALID; | |
305 | ||
306 | if (ppmu->flags & PPMU_SIAR_VALID) | |
307 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
308 | } | |
e6878835 | 309 | |
310 | return 1; | |
311 | } | |
312 | ||
d52f2dc4 MN |
313 | |
314 | /* Reset all possible BHRB entries */ | |
315 | static void power_pmu_bhrb_reset(void) | |
316 | { | |
317 | asm volatile(PPC_CLRBHRB); | |
318 | } | |
319 | ||
320 | static void power_pmu_bhrb_enable(struct perf_event *event) | |
321 | { | |
322 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
323 | ||
324 | if (!ppmu->bhrb_nr) | |
325 | return; | |
326 | ||
327 | /* Clear BHRB if we changed task context to avoid data leaks */ | |
328 | if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { | |
329 | power_pmu_bhrb_reset(); | |
330 | cpuhw->bhrb_context = event->ctx; | |
331 | } | |
332 | cpuhw->bhrb_users++; | |
333 | } | |
334 | ||
335 | static void power_pmu_bhrb_disable(struct perf_event *event) | |
336 | { | |
337 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
338 | ||
339 | if (!ppmu->bhrb_nr) | |
340 | return; | |
341 | ||
342 | cpuhw->bhrb_users--; | |
343 | WARN_ON_ONCE(cpuhw->bhrb_users < 0); | |
344 | ||
345 | if (!cpuhw->disabled && !cpuhw->bhrb_users) { | |
346 | /* BHRB cannot be turned off when other | |
347 | * events are active on the PMU. | |
348 | */ | |
349 | ||
350 | /* avoid stale pointer */ | |
351 | cpuhw->bhrb_context = NULL; | |
352 | } | |
353 | } | |
354 | ||
355 | /* Called from ctxsw to prevent one process's branch entries to | |
356 | * mingle with the other process's entries during context switch. | |
357 | */ | |
358 | void power_pmu_flush_branch_stack(void) | |
359 | { | |
360 | if (ppmu->bhrb_nr) | |
361 | power_pmu_bhrb_reset(); | |
362 | } | |
69123184 MN |
363 | /* Calculate the to address for a branch */ |
364 | static __u64 power_pmu_bhrb_to(u64 addr) | |
365 | { | |
366 | unsigned int instr; | |
367 | int ret; | |
368 | __u64 target; | |
369 | ||
370 | if (is_kernel_addr(addr)) | |
371 | return branch_target((unsigned int *)addr); | |
372 | ||
373 | /* Userspace: need copy instruction here then translate it */ | |
374 | pagefault_disable(); | |
375 | ret = __get_user_inatomic(instr, (unsigned int __user *)addr); | |
376 | if (ret) { | |
377 | pagefault_enable(); | |
378 | return 0; | |
379 | } | |
380 | pagefault_enable(); | |
381 | ||
382 | target = branch_target(&instr); | |
383 | if ((!target) || (instr & BRANCH_ABSOLUTE)) | |
384 | return target; | |
385 | ||
386 | /* Translate relative branch target from kernel to user address */ | |
387 | return target - (unsigned long)&instr + addr; | |
388 | } | |
d52f2dc4 | 389 | |
d52f2dc4 | 390 | /* Processing BHRB entries */ |
506e70d1 | 391 | void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) |
d52f2dc4 MN |
392 | { |
393 | u64 val; | |
394 | u64 addr; | |
506e70d1 | 395 | int r_index, u_index, pred; |
d52f2dc4 MN |
396 | |
397 | r_index = 0; | |
398 | u_index = 0; | |
399 | while (r_index < ppmu->bhrb_nr) { | |
400 | /* Assembly read function */ | |
506e70d1 MN |
401 | val = read_bhrb(r_index++); |
402 | if (!val) | |
403 | /* Terminal marker: End of valid BHRB entries */ | |
d52f2dc4 | 404 | break; |
506e70d1 | 405 | else { |
d52f2dc4 MN |
406 | addr = val & BHRB_EA; |
407 | pred = val & BHRB_PREDICTION; | |
d52f2dc4 | 408 | |
506e70d1 MN |
409 | if (!addr) |
410 | /* invalid entry */ | |
d52f2dc4 | 411 | continue; |
d52f2dc4 | 412 | |
506e70d1 MN |
413 | /* Branches are read most recent first (ie. mfbhrb 0 is |
414 | * the most recent branch). | |
415 | * There are two types of valid entries: | |
416 | * 1) a target entry which is the to address of a | |
417 | * computed goto like a blr,bctr,btar. The next | |
418 | * entry read from the bhrb will be branch | |
419 | * corresponding to this target (ie. the actual | |
420 | * blr/bctr/btar instruction). | |
421 | * 2) a from address which is an actual branch. If a | |
422 | * target entry proceeds this, then this is the | |
423 | * matching branch for that target. If this is not | |
424 | * following a target entry, then this is a branch | |
425 | * where the target is given as an immediate field | |
426 | * in the instruction (ie. an i or b form branch). | |
427 | * In this case we need to read the instruction from | |
428 | * memory to determine the target/to address. | |
429 | */ | |
d52f2dc4 | 430 | |
d52f2dc4 | 431 | if (val & BHRB_TARGET) { |
506e70d1 MN |
432 | /* Target branches use two entries |
433 | * (ie. computed gotos/XL form) | |
434 | */ | |
435 | cpuhw->bhrb_entries[u_index].to = addr; | |
436 | cpuhw->bhrb_entries[u_index].mispred = pred; | |
437 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 438 | |
506e70d1 MN |
439 | /* Get from address in next entry */ |
440 | val = read_bhrb(r_index++); | |
441 | addr = val & BHRB_EA; | |
442 | if (val & BHRB_TARGET) { | |
443 | /* Shouldn't have two targets in a | |
444 | row.. Reset index and try again */ | |
445 | r_index--; | |
446 | addr = 0; | |
447 | } | |
448 | cpuhw->bhrb_entries[u_index].from = addr; | |
d52f2dc4 | 449 | } else { |
506e70d1 MN |
450 | /* Branches to immediate field |
451 | (ie I or B form) */ | |
d52f2dc4 | 452 | cpuhw->bhrb_entries[u_index].from = addr; |
69123184 MN |
453 | cpuhw->bhrb_entries[u_index].to = |
454 | power_pmu_bhrb_to(addr); | |
d52f2dc4 MN |
455 | cpuhw->bhrb_entries[u_index].mispred = pred; |
456 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 457 | } |
506e70d1 MN |
458 | u_index++; |
459 | ||
d52f2dc4 MN |
460 | } |
461 | } | |
462 | cpuhw->bhrb_stack.nr = u_index; | |
463 | return; | |
464 | } | |
465 | ||
98fb1807 PM |
466 | #endif /* CONFIG_PPC64 */ |
467 | ||
cdd6c482 | 468 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 469 | |
cdd6c482 | 470 | void perf_event_print_debug(void) |
4574910e PM |
471 | { |
472 | } | |
473 | ||
4574910e | 474 | /* |
57c0c15b | 475 | * Read one performance monitor counter (PMC). |
4574910e PM |
476 | */ |
477 | static unsigned long read_pmc(int idx) | |
478 | { | |
479 | unsigned long val; | |
480 | ||
481 | switch (idx) { | |
482 | case 1: | |
483 | val = mfspr(SPRN_PMC1); | |
484 | break; | |
485 | case 2: | |
486 | val = mfspr(SPRN_PMC2); | |
487 | break; | |
488 | case 3: | |
489 | val = mfspr(SPRN_PMC3); | |
490 | break; | |
491 | case 4: | |
492 | val = mfspr(SPRN_PMC4); | |
493 | break; | |
494 | case 5: | |
495 | val = mfspr(SPRN_PMC5); | |
496 | break; | |
497 | case 6: | |
498 | val = mfspr(SPRN_PMC6); | |
499 | break; | |
98fb1807 | 500 | #ifdef CONFIG_PPC64 |
4574910e PM |
501 | case 7: |
502 | val = mfspr(SPRN_PMC7); | |
503 | break; | |
504 | case 8: | |
505 | val = mfspr(SPRN_PMC8); | |
506 | break; | |
98fb1807 | 507 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
508 | default: |
509 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
510 | val = 0; | |
511 | } | |
512 | return val; | |
513 | } | |
514 | ||
515 | /* | |
516 | * Write one PMC. | |
517 | */ | |
518 | static void write_pmc(int idx, unsigned long val) | |
519 | { | |
520 | switch (idx) { | |
521 | case 1: | |
522 | mtspr(SPRN_PMC1, val); | |
523 | break; | |
524 | case 2: | |
525 | mtspr(SPRN_PMC2, val); | |
526 | break; | |
527 | case 3: | |
528 | mtspr(SPRN_PMC3, val); | |
529 | break; | |
530 | case 4: | |
531 | mtspr(SPRN_PMC4, val); | |
532 | break; | |
533 | case 5: | |
534 | mtspr(SPRN_PMC5, val); | |
535 | break; | |
536 | case 6: | |
537 | mtspr(SPRN_PMC6, val); | |
538 | break; | |
98fb1807 | 539 | #ifdef CONFIG_PPC64 |
4574910e PM |
540 | case 7: |
541 | mtspr(SPRN_PMC7, val); | |
542 | break; | |
543 | case 8: | |
544 | mtspr(SPRN_PMC8, val); | |
545 | break; | |
98fb1807 | 546 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
547 | default: |
548 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
549 | } | |
550 | } | |
551 | ||
552 | /* | |
553 | * Check if a set of events can all go on the PMU at once. | |
554 | * If they can't, this will look at alternative codes for the events | |
555 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 556 | * The feasible set is returned in event_id[]. |
4574910e | 557 | */ |
cdd6c482 IM |
558 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
559 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 560 | int n_ev) |
4574910e | 561 | { |
448d64f8 | 562 | unsigned long mask, value, nv; |
cdd6c482 IM |
563 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
564 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 565 | int i, j; |
448d64f8 PM |
566 | unsigned long addf = ppmu->add_fields; |
567 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 568 | |
a8f90e90 | 569 | if (n_ev > ppmu->n_counter) |
4574910e PM |
570 | return -1; |
571 | ||
572 | /* First see if the events will go on as-is */ | |
573 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 574 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
575 | && !ppmu->limited_pmc_event(event_id[i])) { |
576 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 577 | cpuhw->alternatives[i]); |
cdd6c482 | 578 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 579 | } |
cdd6c482 | 580 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 581 | &cpuhw->avalues[i][0])) |
4574910e | 582 | return -1; |
4574910e PM |
583 | } |
584 | value = mask = 0; | |
585 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
586 | nv = (value | cpuhw->avalues[i][0]) + |
587 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 588 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
589 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
590 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
591 | break; |
592 | value = nv; | |
e51ee31e | 593 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
594 | } |
595 | if (i == n_ev) | |
596 | return 0; /* all OK */ | |
597 | ||
598 | /* doesn't work, gather alternatives... */ | |
599 | if (!ppmu->get_alternatives) | |
600 | return -1; | |
601 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 602 | choice[i] = 0; |
cdd6c482 | 603 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 604 | cpuhw->alternatives[i]); |
4574910e | 605 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
606 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
607 | &cpuhw->amasks[i][j], | |
608 | &cpuhw->avalues[i][j]); | |
4574910e PM |
609 | } |
610 | ||
611 | /* enumerate all possibilities and see if any will work */ | |
612 | i = 0; | |
613 | j = -1; | |
614 | value = mask = nv = 0; | |
615 | while (i < n_ev) { | |
616 | if (j >= 0) { | |
617 | /* we're backtracking, restore context */ | |
618 | value = svalues[i]; | |
619 | mask = smasks[i]; | |
620 | j = choice[i]; | |
621 | } | |
622 | /* | |
cdd6c482 | 623 | * See if any alternative k for event_id i, |
4574910e PM |
624 | * where k > j, will satisfy the constraints. |
625 | */ | |
626 | while (++j < n_alt[i]) { | |
e51ee31e PM |
627 | nv = (value | cpuhw->avalues[i][j]) + |
628 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 629 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
630 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
631 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
632 | break; |
633 | } | |
634 | if (j >= n_alt[i]) { | |
635 | /* | |
636 | * No feasible alternative, backtrack | |
cdd6c482 | 637 | * to event_id i-1 and continue enumerating its |
4574910e PM |
638 | * alternatives from where we got up to. |
639 | */ | |
640 | if (--i < 0) | |
641 | return -1; | |
642 | } else { | |
643 | /* | |
cdd6c482 IM |
644 | * Found a feasible alternative for event_id i, |
645 | * remember where we got up to with this event_id, | |
646 | * go on to the next event_id, and start with | |
4574910e PM |
647 | * the first alternative for it. |
648 | */ | |
649 | choice[i] = j; | |
650 | svalues[i] = value; | |
651 | smasks[i] = mask; | |
652 | value = nv; | |
e51ee31e | 653 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
654 | ++i; |
655 | j = -1; | |
656 | } | |
657 | } | |
658 | ||
659 | /* OK, we have a feasible combination, tell the caller the solution */ | |
660 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 661 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
662 | return 0; |
663 | } | |
664 | ||
0475f9ea | 665 | /* |
cdd6c482 | 666 | * Check if newly-added events have consistent settings for |
0475f9ea | 667 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 668 | * added events. |
0475f9ea | 669 | */ |
cdd6c482 | 670 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 671 | int n_prev, int n_new) |
0475f9ea | 672 | { |
ab7ef2e5 PM |
673 | int eu = 0, ek = 0, eh = 0; |
674 | int i, n, first; | |
cdd6c482 | 675 | struct perf_event *event; |
0475f9ea PM |
676 | |
677 | n = n_prev + n_new; | |
678 | if (n <= 1) | |
679 | return 0; | |
680 | ||
ab7ef2e5 PM |
681 | first = 1; |
682 | for (i = 0; i < n; ++i) { | |
683 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
684 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
685 | continue; | |
686 | } | |
cdd6c482 | 687 | event = ctrs[i]; |
ab7ef2e5 | 688 | if (first) { |
cdd6c482 IM |
689 | eu = event->attr.exclude_user; |
690 | ek = event->attr.exclude_kernel; | |
691 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 692 | first = 0; |
cdd6c482 IM |
693 | } else if (event->attr.exclude_user != eu || |
694 | event->attr.exclude_kernel != ek || | |
695 | event->attr.exclude_hv != eh) { | |
0475f9ea | 696 | return -EAGAIN; |
ab7ef2e5 | 697 | } |
0475f9ea | 698 | } |
ab7ef2e5 PM |
699 | |
700 | if (eu || ek || eh) | |
701 | for (i = 0; i < n; ++i) | |
702 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
703 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
704 | ||
0475f9ea PM |
705 | return 0; |
706 | } | |
707 | ||
86c74ab3 EM |
708 | static u64 check_and_compute_delta(u64 prev, u64 val) |
709 | { | |
710 | u64 delta = (val - prev) & 0xfffffffful; | |
711 | ||
712 | /* | |
713 | * POWER7 can roll back counter values, if the new value is smaller | |
714 | * than the previous value it will cause the delta and the counter to | |
715 | * have bogus values unless we rolled a counter over. If a coutner is | |
716 | * rolled back, it will be smaller, but within 256, which is the maximum | |
717 | * number of events to rollback at once. If we dectect a rollback | |
718 | * return 0. This can lead to a small lack of precision in the | |
719 | * counters. | |
720 | */ | |
721 | if (prev > val && (prev - val) < 256) | |
722 | delta = 0; | |
723 | ||
724 | return delta; | |
725 | } | |
726 | ||
cdd6c482 | 727 | static void power_pmu_read(struct perf_event *event) |
4574910e | 728 | { |
98fb1807 | 729 | s64 val, delta, prev; |
4574910e | 730 | |
a4eaf7f1 PZ |
731 | if (event->hw.state & PERF_HES_STOPPED) |
732 | return; | |
733 | ||
cdd6c482 | 734 | if (!event->hw.idx) |
4574910e PM |
735 | return; |
736 | /* | |
737 | * Performance monitor interrupts come even when interrupts | |
738 | * are soft-disabled, as long as interrupts are hard-enabled. | |
739 | * Therefore we treat them like NMIs. | |
740 | */ | |
741 | do { | |
e7850595 | 742 | prev = local64_read(&event->hw.prev_count); |
4574910e | 743 | barrier(); |
cdd6c482 | 744 | val = read_pmc(event->hw.idx); |
86c74ab3 EM |
745 | delta = check_and_compute_delta(prev, val); |
746 | if (!delta) | |
747 | return; | |
e7850595 | 748 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 749 | |
e7850595 PZ |
750 | local64_add(delta, &event->count); |
751 | local64_sub(delta, &event->hw.period_left); | |
4574910e PM |
752 | } |
753 | ||
ab7ef2e5 PM |
754 | /* |
755 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
756 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 757 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
758 | */ |
759 | static int is_limited_pmc(int pmcnum) | |
760 | { | |
0bbd0d4b PM |
761 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
762 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
763 | } |
764 | ||
a8f90e90 | 765 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
766 | unsigned long pmc5, unsigned long pmc6) |
767 | { | |
cdd6c482 | 768 | struct perf_event *event; |
ab7ef2e5 PM |
769 | u64 val, prev, delta; |
770 | int i; | |
771 | ||
772 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 773 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 774 | if (!event->hw.idx) |
ab7ef2e5 | 775 | continue; |
cdd6c482 | 776 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 777 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 778 | event->hw.idx = 0; |
86c74ab3 EM |
779 | delta = check_and_compute_delta(prev, val); |
780 | if (delta) | |
781 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
782 | } |
783 | } | |
784 | ||
a8f90e90 | 785 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
786 | unsigned long pmc5, unsigned long pmc6) |
787 | { | |
cdd6c482 | 788 | struct perf_event *event; |
86c74ab3 | 789 | u64 val, prev; |
ab7ef2e5 PM |
790 | int i; |
791 | ||
792 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 793 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
794 | event->hw.idx = cpuhw->limited_hwidx[i]; |
795 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
796 | prev = local64_read(&event->hw.prev_count); |
797 | if (check_and_compute_delta(prev, val)) | |
798 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 799 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
800 | } |
801 | } | |
802 | ||
803 | /* | |
cdd6c482 | 804 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 805 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
806 | * other events. We try to keep the values from the limited |
807 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 808 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
809 | * the limited events as small and consistent as possible. |
810 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
811 | * both, and always in the same order, to minimize variability, |
812 | * and do it inside the same asm that writes MMCR0. | |
813 | */ | |
cdd6c482 | 814 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
815 | { |
816 | unsigned long pmc5, pmc6; | |
817 | ||
818 | if (!cpuhw->n_limited) { | |
819 | mtspr(SPRN_MMCR0, mmcr0); | |
820 | return; | |
821 | } | |
822 | ||
823 | /* | |
824 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
825 | * To ensure we don't get a performance monitor interrupt |
826 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 827 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 828 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
829 | */ |
830 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
831 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
832 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
833 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
834 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
835 | ||
836 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 837 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 838 | else |
a8f90e90 | 839 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
840 | |
841 | /* | |
cdd6c482 | 842 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
843 | * enable bits, if necessary. |
844 | */ | |
845 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
846 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
847 | } |
848 | ||
4574910e | 849 | /* |
cdd6c482 IM |
850 | * Disable all events to prevent PMU interrupts and to allow |
851 | * events to be added or removed. | |
4574910e | 852 | */ |
a4eaf7f1 | 853 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 854 | { |
cdd6c482 | 855 | struct cpu_hw_events *cpuhw; |
378a6ee9 | 856 | unsigned long flags, val; |
4574910e | 857 | |
f36a1a13 PM |
858 | if (!ppmu) |
859 | return; | |
4574910e | 860 | local_irq_save(flags); |
cdd6c482 | 861 | cpuhw = &__get_cpu_var(cpu_hw_events); |
4574910e | 862 | |
448d64f8 | 863 | if (!cpuhw->disabled) { |
01d0287f PM |
864 | /* |
865 | * Check if we ever enabled the PMU on this cpu. | |
866 | */ | |
867 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 868 | ppc_enable_pmcs(); |
01d0287f PM |
869 | cpuhw->pmcs_enabled = 1; |
870 | } | |
871 | ||
378a6ee9 ME |
872 | /* |
873 | * Set the 'freeze counters' bit, clear PMAO. | |
874 | */ | |
875 | val = mfspr(SPRN_MMCR0); | |
876 | val |= MMCR0_FC; | |
877 | val &= ~MMCR0_PMAO; | |
878 | ||
879 | /* | |
880 | * The barrier is to make sure the mtspr has been | |
881 | * executed and the PMU has frozen the events etc. | |
882 | * before we return. | |
883 | */ | |
884 | write_mmcr0(cpuhw, val); | |
885 | mb(); | |
886 | ||
f708223d PM |
887 | /* |
888 | * Disable instruction sampling if it was enabled | |
889 | */ | |
890 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
891 | mtspr(SPRN_MMCRA, | |
892 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
893 | mb(); | |
894 | } | |
895 | ||
378a6ee9 ME |
896 | cpuhw->disabled = 1; |
897 | cpuhw->n_added = 0; | |
4574910e PM |
898 | } |
899 | local_irq_restore(flags); | |
4574910e PM |
900 | } |
901 | ||
902 | /* | |
cdd6c482 IM |
903 | * Re-enable all events if disable == 0. |
904 | * If we were previously disabled and events were added, then | |
4574910e PM |
905 | * put the new config on the PMU. |
906 | */ | |
a4eaf7f1 | 907 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 908 | { |
cdd6c482 IM |
909 | struct perf_event *event; |
910 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
911 | unsigned long flags; |
912 | long i; | |
913 | unsigned long val; | |
914 | s64 left; | |
cdd6c482 | 915 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
916 | int n_lim; |
917 | int idx; | |
4574910e | 918 | |
f36a1a13 PM |
919 | if (!ppmu) |
920 | return; | |
4574910e | 921 | local_irq_save(flags); |
cdd6c482 | 922 | cpuhw = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
923 | if (!cpuhw->disabled) { |
924 | local_irq_restore(flags); | |
925 | return; | |
926 | } | |
4574910e PM |
927 | cpuhw->disabled = 0; |
928 | ||
929 | /* | |
cdd6c482 | 930 | * If we didn't change anything, or only removed events, |
4574910e PM |
931 | * no need to recalculate MMCR* settings and reset the PMCs. |
932 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 933 | * (possibly updated for removal of events). |
4574910e PM |
934 | */ |
935 | if (!cpuhw->n_added) { | |
f708223d | 936 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 937 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
cdd6c482 | 938 | if (cpuhw->n_events == 0) |
a6dbf93a | 939 | ppc_set_pmu_inuse(0); |
f708223d | 940 | goto out_enable; |
4574910e PM |
941 | } |
942 | ||
943 | /* | |
cdd6c482 | 944 | * Compute MMCR* values for the new set of events |
4574910e | 945 | */ |
cdd6c482 | 946 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
4574910e PM |
947 | cpuhw->mmcr)) { |
948 | /* shouldn't ever get here */ | |
949 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
950 | goto out; | |
951 | } | |
952 | ||
0475f9ea PM |
953 | /* |
954 | * Add in MMCR0 freeze bits corresponding to the | |
cdd6c482 IM |
955 | * attr.exclude_* bits for the first event. |
956 | * We have already checked that all events have the | |
957 | * same values for these bits as the first event. | |
0475f9ea | 958 | */ |
cdd6c482 IM |
959 | event = cpuhw->event[0]; |
960 | if (event->attr.exclude_user) | |
0475f9ea | 961 | cpuhw->mmcr[0] |= MMCR0_FCP; |
cdd6c482 IM |
962 | if (event->attr.exclude_kernel) |
963 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
964 | if (event->attr.exclude_hv) | |
0475f9ea PM |
965 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
966 | ||
4574910e PM |
967 | /* |
968 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
969 | * bit set and set the hardware events to their initial values. |
970 | * Then unfreeze the events. | |
4574910e | 971 | */ |
a6dbf93a | 972 | ppc_set_pmu_inuse(1); |
f708223d | 973 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
974 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
975 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
976 | | MMCR0_FC); | |
977 | ||
978 | /* | |
cdd6c482 | 979 | * Read off any pre-existing events that need to move |
4574910e PM |
980 | * to another PMC. |
981 | */ | |
cdd6c482 IM |
982 | for (i = 0; i < cpuhw->n_events; ++i) { |
983 | event = cpuhw->event[i]; | |
984 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
985 | power_pmu_read(event); | |
986 | write_pmc(event->hw.idx, 0); | |
987 | event->hw.idx = 0; | |
4574910e PM |
988 | } |
989 | } | |
990 | ||
991 | /* | |
cdd6c482 | 992 | * Initialize the PMCs for all the new and moved events. |
4574910e | 993 | */ |
ab7ef2e5 | 994 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
995 | for (i = 0; i < cpuhw->n_events; ++i) { |
996 | event = cpuhw->event[i]; | |
997 | if (event->hw.idx) | |
4574910e | 998 | continue; |
ab7ef2e5 PM |
999 | idx = hwc_index[i] + 1; |
1000 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 1001 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
1002 | cpuhw->limited_hwidx[n_lim] = idx; |
1003 | ++n_lim; | |
1004 | continue; | |
1005 | } | |
4574910e | 1006 | val = 0; |
cdd6c482 | 1007 | if (event->hw.sample_period) { |
e7850595 | 1008 | left = local64_read(&event->hw.period_left); |
4574910e PM |
1009 | if (left < 0x80000000L) |
1010 | val = 0x80000000L - left; | |
1011 | } | |
e7850595 | 1012 | local64_set(&event->hw.prev_count, val); |
cdd6c482 | 1013 | event->hw.idx = idx; |
a4eaf7f1 PZ |
1014 | if (event->hw.state & PERF_HES_STOPPED) |
1015 | val = 0; | |
ab7ef2e5 | 1016 | write_pmc(idx, val); |
cdd6c482 | 1017 | perf_event_update_userpage(event); |
4574910e | 1018 | } |
ab7ef2e5 | 1019 | cpuhw->n_limited = n_lim; |
4574910e | 1020 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
1021 | |
1022 | out_enable: | |
1023 | mb(); | |
ab7ef2e5 | 1024 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1025 | |
f708223d PM |
1026 | /* |
1027 | * Enable instruction sampling if necessary | |
1028 | */ | |
1029 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1030 | mb(); | |
1031 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
1032 | } | |
1033 | ||
4574910e | 1034 | out: |
3925f46b AK |
1035 | if (cpuhw->bhrb_users) |
1036 | ppmu->config_bhrb(cpuhw->bhrb_filter); | |
1037 | ||
4574910e PM |
1038 | local_irq_restore(flags); |
1039 | } | |
1040 | ||
cdd6c482 IM |
1041 | static int collect_events(struct perf_event *group, int max_count, |
1042 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 1043 | unsigned int *flags) |
4574910e PM |
1044 | { |
1045 | int n = 0; | |
cdd6c482 | 1046 | struct perf_event *event; |
4574910e | 1047 | |
cdd6c482 | 1048 | if (!is_software_event(group)) { |
4574910e PM |
1049 | if (n >= max_count) |
1050 | return -1; | |
1051 | ctrs[n] = group; | |
cdd6c482 | 1052 | flags[n] = group->hw.event_base; |
4574910e PM |
1053 | events[n++] = group->hw.config; |
1054 | } | |
a8f90e90 | 1055 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
1056 | if (!is_software_event(event) && |
1057 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
1058 | if (n >= max_count) |
1059 | return -1; | |
cdd6c482 IM |
1060 | ctrs[n] = event; |
1061 | flags[n] = event->hw.event_base; | |
1062 | events[n++] = event->hw.config; | |
4574910e PM |
1063 | } |
1064 | } | |
1065 | return n; | |
1066 | } | |
1067 | ||
4574910e | 1068 | /* |
cdd6c482 IM |
1069 | * Add a event to the PMU. |
1070 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 1071 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
1072 | * actual work of reconfiguring the PMU. |
1073 | */ | |
a4eaf7f1 | 1074 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 1075 | { |
cdd6c482 | 1076 | struct cpu_hw_events *cpuhw; |
4574910e | 1077 | unsigned long flags; |
4574910e PM |
1078 | int n0; |
1079 | int ret = -EAGAIN; | |
1080 | ||
1081 | local_irq_save(flags); | |
33696fc0 | 1082 | perf_pmu_disable(event->pmu); |
4574910e PM |
1083 | |
1084 | /* | |
cdd6c482 | 1085 | * Add the event to the list (if there is room) |
4574910e PM |
1086 | * and check whether the total set is still feasible. |
1087 | */ | |
cdd6c482 IM |
1088 | cpuhw = &__get_cpu_var(cpu_hw_events); |
1089 | n0 = cpuhw->n_events; | |
a8f90e90 | 1090 | if (n0 >= ppmu->n_counter) |
4574910e | 1091 | goto out; |
cdd6c482 IM |
1092 | cpuhw->event[n0] = event; |
1093 | cpuhw->events[n0] = event->hw.config; | |
1094 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 1095 | |
f53d168c | 1096 | /* |
1097 | * This event may have been disabled/stopped in record_and_restart() | |
1098 | * because we exceeded the ->event_limit. If re-starting the event, | |
1099 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
1100 | * notification is re-enabled. | |
1101 | */ | |
a4eaf7f1 PZ |
1102 | if (!(ef_flags & PERF_EF_START)) |
1103 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 1104 | else |
1105 | event->hw.state = 0; | |
a4eaf7f1 | 1106 | |
8e6d5573 LM |
1107 | /* |
1108 | * If group events scheduling transaction was started, | |
25985edc | 1109 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
1110 | * at commit time(->commit_txn) as a whole |
1111 | */ | |
8d2cacbb | 1112 | if (cpuhw->group_flag & PERF_EVENT_TXN) |
8e6d5573 LM |
1113 | goto nocheck; |
1114 | ||
cdd6c482 | 1115 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 1116 | goto out; |
e51ee31e | 1117 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 1118 | goto out; |
cdd6c482 | 1119 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
1120 | |
1121 | nocheck: | |
cdd6c482 | 1122 | ++cpuhw->n_events; |
4574910e PM |
1123 | ++cpuhw->n_added; |
1124 | ||
1125 | ret = 0; | |
1126 | out: | |
3925f46b AK |
1127 | if (has_branch_stack(event)) |
1128 | power_pmu_bhrb_enable(event); | |
1129 | ||
33696fc0 | 1130 | perf_pmu_enable(event->pmu); |
4574910e PM |
1131 | local_irq_restore(flags); |
1132 | return ret; | |
1133 | } | |
1134 | ||
1135 | /* | |
cdd6c482 | 1136 | * Remove a event from the PMU. |
4574910e | 1137 | */ |
a4eaf7f1 | 1138 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 1139 | { |
cdd6c482 | 1140 | struct cpu_hw_events *cpuhw; |
4574910e | 1141 | long i; |
4574910e PM |
1142 | unsigned long flags; |
1143 | ||
1144 | local_irq_save(flags); | |
33696fc0 | 1145 | perf_pmu_disable(event->pmu); |
4574910e | 1146 | |
cdd6c482 IM |
1147 | power_pmu_read(event); |
1148 | ||
1149 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1150 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1151 | if (event == cpuhw->event[i]) { | |
219a92a4 | 1152 | while (++i < cpuhw->n_events) { |
cdd6c482 | 1153 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
1154 | cpuhw->events[i-1] = cpuhw->events[i]; |
1155 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
1156 | } | |
cdd6c482 IM |
1157 | --cpuhw->n_events; |
1158 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
1159 | if (event->hw.idx) { | |
1160 | write_pmc(event->hw.idx, 0); | |
1161 | event->hw.idx = 0; | |
ab7ef2e5 | 1162 | } |
cdd6c482 | 1163 | perf_event_update_userpage(event); |
4574910e PM |
1164 | break; |
1165 | } | |
1166 | } | |
ab7ef2e5 | 1167 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 1168 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
1169 | break; |
1170 | if (i < cpuhw->n_limited) { | |
1171 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 1172 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
1173 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
1174 | } | |
1175 | --cpuhw->n_limited; | |
1176 | } | |
cdd6c482 IM |
1177 | if (cpuhw->n_events == 0) { |
1178 | /* disable exceptions if no events are running */ | |
4574910e PM |
1179 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
1180 | } | |
1181 | ||
3925f46b AK |
1182 | if (has_branch_stack(event)) |
1183 | power_pmu_bhrb_disable(event); | |
1184 | ||
33696fc0 | 1185 | perf_pmu_enable(event->pmu); |
4574910e PM |
1186 | local_irq_restore(flags); |
1187 | } | |
1188 | ||
8a7b8cb9 | 1189 | /* |
a4eaf7f1 PZ |
1190 | * POWER-PMU does not support disabling individual counters, hence |
1191 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 1192 | */ |
a4eaf7f1 PZ |
1193 | |
1194 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 1195 | { |
8a7b8cb9 | 1196 | unsigned long flags; |
a4eaf7f1 | 1197 | s64 left; |
9a45a940 | 1198 | unsigned long val; |
8a7b8cb9 | 1199 | |
cdd6c482 | 1200 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 1201 | return; |
a4eaf7f1 PZ |
1202 | |
1203 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
1204 | return; | |
1205 | ||
1206 | if (ef_flags & PERF_EF_RELOAD) | |
1207 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1208 | ||
1209 | local_irq_save(flags); | |
1210 | perf_pmu_disable(event->pmu); | |
1211 | ||
1212 | event->hw.state = 0; | |
1213 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
1214 | |
1215 | val = 0; | |
1216 | if (left < 0x80000000L) | |
1217 | val = 0x80000000L - left; | |
1218 | ||
1219 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1220 | |
1221 | perf_event_update_userpage(event); | |
1222 | perf_pmu_enable(event->pmu); | |
1223 | local_irq_restore(flags); | |
1224 | } | |
1225 | ||
1226 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1227 | { | |
1228 | unsigned long flags; | |
1229 | ||
1230 | if (!event->hw.idx || !event->hw.sample_period) | |
1231 | return; | |
1232 | ||
1233 | if (event->hw.state & PERF_HES_STOPPED) | |
1234 | return; | |
1235 | ||
8a7b8cb9 | 1236 | local_irq_save(flags); |
33696fc0 | 1237 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1238 | |
cdd6c482 | 1239 | power_pmu_read(event); |
a4eaf7f1 PZ |
1240 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1241 | write_pmc(event->hw.idx, 0); | |
1242 | ||
cdd6c482 | 1243 | perf_event_update_userpage(event); |
33696fc0 | 1244 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1245 | local_irq_restore(flags); |
1246 | } | |
1247 | ||
8e6d5573 LM |
1248 | /* |
1249 | * Start group events scheduling transaction | |
1250 | * Set the flag to make pmu::enable() not perform the | |
1251 | * schedulability test, it will be performed at commit time | |
1252 | */ | |
51b0fe39 | 1253 | void power_pmu_start_txn(struct pmu *pmu) |
8e6d5573 LM |
1254 | { |
1255 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1256 | ||
33696fc0 | 1257 | perf_pmu_disable(pmu); |
8d2cacbb | 1258 | cpuhw->group_flag |= PERF_EVENT_TXN; |
8e6d5573 LM |
1259 | cpuhw->n_txn_start = cpuhw->n_events; |
1260 | } | |
1261 | ||
1262 | /* | |
1263 | * Stop group events scheduling transaction | |
1264 | * Clear the flag and pmu::enable() will perform the | |
1265 | * schedulability test. | |
1266 | */ | |
51b0fe39 | 1267 | void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 LM |
1268 | { |
1269 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1270 | ||
8d2cacbb | 1271 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1272 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1273 | } |
1274 | ||
1275 | /* | |
1276 | * Commit group events scheduling transaction | |
1277 | * Perform the group schedulability test as a whole | |
1278 | * Return 0 if success | |
1279 | */ | |
51b0fe39 | 1280 | int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1281 | { |
1282 | struct cpu_hw_events *cpuhw; | |
1283 | long i, n; | |
1284 | ||
1285 | if (!ppmu) | |
1286 | return -EAGAIN; | |
1287 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1288 | n = cpuhw->n_events; | |
1289 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1290 | return -EAGAIN; | |
1291 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1292 | if (i < 0) | |
1293 | return -EAGAIN; | |
1294 | ||
1295 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1296 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1297 | ||
8d2cacbb | 1298 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1299 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1300 | return 0; |
1301 | } | |
1302 | ||
ab7ef2e5 | 1303 | /* |
cdd6c482 | 1304 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1305 | * or 0 if not. |
cdd6c482 | 1306 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1307 | * that a limited PMC can count, doesn't require interrupts, and |
1308 | * doesn't exclude any processor mode. | |
1309 | */ | |
cdd6c482 | 1310 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1311 | unsigned int flags) |
1312 | { | |
1313 | int n; | |
ef923214 | 1314 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1315 | |
cdd6c482 IM |
1316 | if (event->attr.exclude_user |
1317 | || event->attr.exclude_kernel | |
1318 | || event->attr.exclude_hv | |
1319 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1320 | return 0; |
1321 | ||
1322 | if (ppmu->limited_pmc_event(ev)) | |
1323 | return 1; | |
1324 | ||
1325 | /* | |
cdd6c482 | 1326 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1327 | * see if any alternative code goes on a limited PMC. |
1328 | */ | |
1329 | if (!ppmu->get_alternatives) | |
1330 | return 0; | |
1331 | ||
1332 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1333 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1334 | |
ef923214 | 1335 | return n > 0; |
ab7ef2e5 PM |
1336 | } |
1337 | ||
1338 | /* | |
cdd6c482 IM |
1339 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1340 | * and return the event_id code, or 0 if there is no such alternative. | |
1341 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1342 | */ |
ef923214 | 1343 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1344 | { |
ef923214 | 1345 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1346 | int n; |
1347 | ||
1348 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1349 | n = ppmu->get_alternatives(ev, flags, alt); | |
1350 | if (!n) | |
1351 | return 0; | |
1352 | return alt[0]; | |
1353 | } | |
1354 | ||
cdd6c482 IM |
1355 | /* Number of perf_events counting hardware events */ |
1356 | static atomic_t num_events; | |
7595d63b PM |
1357 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1358 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1359 | ||
1360 | /* | |
cdd6c482 | 1361 | * Release the PMU if this is the last perf_event. |
7595d63b | 1362 | */ |
cdd6c482 | 1363 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1364 | { |
cdd6c482 | 1365 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1366 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1367 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1368 | release_pmc_hardware(); |
1369 | mutex_unlock(&pmc_reserve_mutex); | |
1370 | } | |
1371 | } | |
1372 | ||
106b506c | 1373 | /* |
cdd6c482 | 1374 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1375 | */ |
1376 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1377 | { | |
1378 | unsigned long type, op, result; | |
1379 | int ev; | |
1380 | ||
1381 | if (!ppmu->cache_events) | |
1382 | return -EINVAL; | |
1383 | ||
1384 | /* unpack config */ | |
1385 | type = config & 0xff; | |
1386 | op = (config >> 8) & 0xff; | |
1387 | result = (config >> 16) & 0xff; | |
1388 | ||
1389 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1390 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1391 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1392 | return -EINVAL; | |
1393 | ||
1394 | ev = (*ppmu->cache_events)[type][op][result]; | |
1395 | if (ev == 0) | |
1396 | return -EOPNOTSUPP; | |
1397 | if (ev == -1) | |
1398 | return -EINVAL; | |
1399 | *eventp = ev; | |
1400 | return 0; | |
1401 | } | |
1402 | ||
b0a873eb | 1403 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1404 | { |
ef923214 PM |
1405 | u64 ev; |
1406 | unsigned long flags; | |
cdd6c482 IM |
1407 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1408 | u64 events[MAX_HWEVENTS]; | |
1409 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1410 | int n; |
7595d63b | 1411 | int err; |
cdd6c482 | 1412 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1413 | |
1414 | if (!ppmu) | |
b0a873eb PZ |
1415 | return -ENOENT; |
1416 | ||
3925f46b AK |
1417 | if (has_branch_stack(event)) { |
1418 | /* PMU has BHRB enabled */ | |
1419 | if (!(ppmu->flags & PPMU_BHRB)) | |
1420 | return -EOPNOTSUPP; | |
1421 | } | |
2481c5fa | 1422 | |
cdd6c482 | 1423 | switch (event->attr.type) { |
106b506c | 1424 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1425 | ev = event->attr.config; |
9aaa131a | 1426 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1427 | return -EOPNOTSUPP; |
4574910e | 1428 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1429 | break; |
1430 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1431 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1432 | if (err) |
b0a873eb | 1433 | return err; |
106b506c PM |
1434 | break; |
1435 | case PERF_TYPE_RAW: | |
cdd6c482 | 1436 | ev = event->attr.config; |
106b506c | 1437 | break; |
90c8f954 | 1438 | default: |
b0a873eb | 1439 | return -ENOENT; |
4574910e | 1440 | } |
b0a873eb | 1441 | |
cdd6c482 IM |
1442 | event->hw.config_base = ev; |
1443 | event->hw.idx = 0; | |
4574910e | 1444 | |
0475f9ea PM |
1445 | /* |
1446 | * If we are not running on a hypervisor, force the | |
1447 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1448 | * the user set it to. |
0475f9ea PM |
1449 | */ |
1450 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1451 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1452 | |
1453 | /* | |
cdd6c482 | 1454 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1455 | * PM_RUN_* events interchangeably with their non RUN_* |
1456 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1457 | * XXX we should check if the task is an idle task. | |
1458 | */ | |
1459 | flags = 0; | |
57fa7214 | 1460 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1461 | flags |= PPMU_ONLY_COUNT_RUN; |
1462 | ||
1463 | /* | |
cdd6c482 IM |
1464 | * If this machine has limited events, check whether this |
1465 | * event_id could go on a limited event. | |
ab7ef2e5 | 1466 | */ |
0bbd0d4b | 1467 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1468 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1469 | flags |= PPMU_LIMITED_PMC_OK; |
1470 | } else if (ppmu->limited_pmc_event(ev)) { | |
1471 | /* | |
cdd6c482 | 1472 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1473 | * but we can't use a limited PMC; see if any |
1474 | * alternative goes on a normal PMC. | |
1475 | */ | |
1476 | ev = normal_pmc_alternative(ev, flags); | |
1477 | if (!ev) | |
b0a873eb | 1478 | return -EINVAL; |
ab7ef2e5 PM |
1479 | } |
1480 | } | |
1481 | ||
4574910e PM |
1482 | /* |
1483 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1484 | * other hardware events in the group. We assume the event |
4574910e PM |
1485 | * hasn't been linked into its leader's sibling list at this point. |
1486 | */ | |
1487 | n = 0; | |
cdd6c482 | 1488 | if (event->group_leader != event) { |
a8f90e90 | 1489 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1490 | ctrs, events, cflags); |
4574910e | 1491 | if (n < 0) |
b0a873eb | 1492 | return -EINVAL; |
4574910e | 1493 | } |
0475f9ea | 1494 | events[n] = ev; |
cdd6c482 | 1495 | ctrs[n] = event; |
ab7ef2e5 PM |
1496 | cflags[n] = flags; |
1497 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1498 | return -EINVAL; |
e51ee31e | 1499 | |
cdd6c482 | 1500 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1501 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
3925f46b AK |
1502 | |
1503 | if (has_branch_stack(event)) { | |
1504 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( | |
1505 | event->attr.branch_sample_type); | |
1506 | ||
1507 | if(cpuhw->bhrb_filter == -1) | |
1508 | return -EOPNOTSUPP; | |
1509 | } | |
1510 | ||
cdd6c482 | 1511 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1512 | if (err) |
b0a873eb | 1513 | return -EINVAL; |
4574910e | 1514 | |
cdd6c482 IM |
1515 | event->hw.config = events[n]; |
1516 | event->hw.event_base = cflags[n]; | |
1517 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1518 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b PM |
1519 | |
1520 | /* | |
1521 | * See if we need to reserve the PMU. | |
cdd6c482 | 1522 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1523 | * mutex to ensure that we don't race with another task doing |
1524 | * reserve_pmc_hardware or release_pmc_hardware. | |
1525 | */ | |
1526 | err = 0; | |
cdd6c482 | 1527 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1528 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1529 | if (atomic_read(&num_events) == 0 && |
1530 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1531 | err = -EBUSY; |
1532 | else | |
cdd6c482 | 1533 | atomic_inc(&num_events); |
7595d63b PM |
1534 | mutex_unlock(&pmc_reserve_mutex); |
1535 | } | |
cdd6c482 | 1536 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1537 | |
b0a873eb | 1538 | return err; |
4574910e PM |
1539 | } |
1540 | ||
35edc2a5 PZ |
1541 | static int power_pmu_event_idx(struct perf_event *event) |
1542 | { | |
1543 | return event->hw.idx; | |
1544 | } | |
1545 | ||
1c53a270 SB |
1546 | ssize_t power_events_sysfs_show(struct device *dev, |
1547 | struct device_attribute *attr, char *page) | |
1548 | { | |
1549 | struct perf_pmu_events_attr *pmu_attr; | |
1550 | ||
1551 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
1552 | ||
1553 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
1554 | } | |
1555 | ||
b0a873eb | 1556 | struct pmu power_pmu = { |
a4eaf7f1 PZ |
1557 | .pmu_enable = power_pmu_enable, |
1558 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1559 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1560 | .add = power_pmu_add, |
1561 | .del = power_pmu_del, | |
1562 | .start = power_pmu_start, | |
1563 | .stop = power_pmu_stop, | |
b0a873eb | 1564 | .read = power_pmu_read, |
b0a873eb PZ |
1565 | .start_txn = power_pmu_start_txn, |
1566 | .cancel_txn = power_pmu_cancel_txn, | |
1567 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1568 | .event_idx = power_pmu_event_idx, |
3925f46b | 1569 | .flush_branch_stack = power_pmu_flush_branch_stack, |
b0a873eb PZ |
1570 | }; |
1571 | ||
4574910e | 1572 | /* |
57c0c15b | 1573 | * A counter has overflowed; update its count and record |
4574910e PM |
1574 | * things if requested. Note that interrupts are hard-disabled |
1575 | * here so there is no possibility of being interrupted. | |
1576 | */ | |
cdd6c482 | 1577 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1578 | struct pt_regs *regs) |
4574910e | 1579 | { |
cdd6c482 | 1580 | u64 period = event->hw.sample_period; |
4574910e PM |
1581 | s64 prev, delta, left; |
1582 | int record = 0; | |
1583 | ||
a4eaf7f1 PZ |
1584 | if (event->hw.state & PERF_HES_STOPPED) { |
1585 | write_pmc(event->hw.idx, 0); | |
1586 | return; | |
1587 | } | |
1588 | ||
4574910e | 1589 | /* we don't have to worry about interrupts here */ |
e7850595 | 1590 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 1591 | delta = check_and_compute_delta(prev, val); |
e7850595 | 1592 | local64_add(delta, &event->count); |
4574910e PM |
1593 | |
1594 | /* | |
cdd6c482 | 1595 | * See if the total period for this event has expired, |
4574910e PM |
1596 | * and update for the next period. |
1597 | */ | |
1598 | val = 0; | |
e7850595 | 1599 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
1600 | if (delta == 0) |
1601 | left++; | |
60db5e09 | 1602 | if (period) { |
4574910e | 1603 | if (left <= 0) { |
60db5e09 | 1604 | left += period; |
4574910e | 1605 | if (left <= 0) |
60db5e09 | 1606 | left = period; |
e6878835 | 1607 | record = siar_valid(regs); |
4bca770e | 1608 | event->hw.last_period = event->hw.sample_period; |
4574910e | 1609 | } |
98fb1807 PM |
1610 | if (left < 0x80000000LL) |
1611 | val = 0x80000000LL - left; | |
4574910e | 1612 | } |
4574910e | 1613 | |
a4eaf7f1 PZ |
1614 | write_pmc(event->hw.idx, val); |
1615 | local64_set(&event->hw.prev_count, val); | |
1616 | local64_set(&event->hw.period_left, left); | |
1617 | perf_event_update_userpage(event); | |
1618 | ||
4574910e PM |
1619 | /* |
1620 | * Finally record data if requested. | |
1621 | */ | |
0bbd0d4b | 1622 | if (record) { |
dc1d628a PZ |
1623 | struct perf_sample_data data; |
1624 | ||
fd0d000b | 1625 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 1626 | |
cdd6c482 | 1627 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
1628 | perf_get_data_addr(regs, &data.addr); |
1629 | ||
3925f46b AK |
1630 | if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { |
1631 | struct cpu_hw_events *cpuhw; | |
1632 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1633 | power_pmu_bhrb_read(cpuhw); | |
1634 | data.br_stack = &cpuhw->bhrb_stack; | |
1635 | } | |
1636 | ||
a8b0ca17 | 1637 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1638 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
1639 | } |
1640 | } | |
1641 | ||
1642 | /* | |
1643 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 1644 | * for an event_id. |
0bbd0d4b PM |
1645 | */ |
1646 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1647 | { | |
98fb1807 | 1648 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 1649 | |
98fb1807 PM |
1650 | if (flags) |
1651 | return flags; | |
cdd6c482 IM |
1652 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
1653 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
1654 | } |
1655 | ||
1656 | /* | |
1657 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 1658 | * for an event_id. |
0bbd0d4b PM |
1659 | */ |
1660 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1661 | { | |
33904054 | 1662 | bool use_siar = regs_use_siar(regs); |
0bbd0d4b | 1663 | |
e6878835 | 1664 | if (use_siar && siar_valid(regs)) |
75382aa7 | 1665 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 1666 | else if (use_siar) |
1667 | return 0; // no valid instruction pointer | |
75382aa7 | 1668 | else |
1ce447b9 | 1669 | return regs->nip; |
4574910e PM |
1670 | } |
1671 | ||
bc09c219 | 1672 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 1673 | { |
0837e324 AB |
1674 | /* |
1675 | * Events on POWER7 can roll back if a speculative event doesn't | |
1676 | * eventually complete. Unfortunately in some rare cases they will | |
1677 | * raise a performance monitor exception. We need to catch this to | |
1678 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
1679 | * cycles from overflow. | |
1680 | * | |
1681 | * We only do this if the first pass fails to find any overflowing | |
1682 | * PMCs because a user might set a period of less than 256 and we | |
1683 | * don't want to mistakenly reset them. | |
1684 | */ | |
bc09c219 MN |
1685 | if ((0x80000000 - val) <= 256) |
1686 | return true; | |
1687 | ||
1688 | return false; | |
1689 | } | |
1690 | ||
1691 | static bool pmc_overflow(unsigned long val) | |
1692 | { | |
1693 | if ((int)val < 0) | |
0837e324 AB |
1694 | return true; |
1695 | ||
1696 | return false; | |
1697 | } | |
1698 | ||
4574910e PM |
1699 | /* |
1700 | * Performance monitor interrupt stuff | |
1701 | */ | |
cdd6c482 | 1702 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 1703 | { |
bc09c219 | 1704 | int i, j; |
cdd6c482 IM |
1705 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); |
1706 | struct perf_event *event; | |
bc09c219 MN |
1707 | unsigned long val[8]; |
1708 | int found, active; | |
ca8f2d7f PM |
1709 | int nmi; |
1710 | ||
ab7ef2e5 | 1711 | if (cpuhw->n_limited) |
a8f90e90 | 1712 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
1713 | mfspr(SPRN_PMC6)); |
1714 | ||
98fb1807 | 1715 | perf_read_regs(regs); |
0bbd0d4b | 1716 | |
98fb1807 | 1717 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
1718 | if (nmi) |
1719 | nmi_enter(); | |
1720 | else | |
1721 | irq_enter(); | |
4574910e | 1722 | |
bc09c219 MN |
1723 | /* Read all the PMCs since we'll need them a bunch of times */ |
1724 | for (i = 0; i < ppmu->n_counter; ++i) | |
1725 | val[i] = read_pmc(i + 1); | |
1726 | ||
1727 | /* Try to find what caused the IRQ */ | |
1728 | found = 0; | |
1729 | for (i = 0; i < ppmu->n_counter; ++i) { | |
1730 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 1731 | continue; |
bc09c219 MN |
1732 | if (is_limited_pmc(i + 1)) |
1733 | continue; /* these won't generate IRQs */ | |
1734 | /* | |
1735 | * We've found one that's overflowed. For active | |
1736 | * counters we need to log this. For inactive | |
1737 | * counters, we need to reset it anyway | |
1738 | */ | |
1739 | found = 1; | |
1740 | active = 0; | |
1741 | for (j = 0; j < cpuhw->n_events; ++j) { | |
1742 | event = cpuhw->event[j]; | |
1743 | if (event->hw.idx == (i + 1)) { | |
1744 | active = 1; | |
1745 | record_and_restart(event, val[i], regs); | |
1746 | break; | |
1747 | } | |
4574910e | 1748 | } |
bc09c219 MN |
1749 | if (!active) |
1750 | /* reset non active counters that have overflowed */ | |
1751 | write_pmc(i + 1, 0); | |
4574910e | 1752 | } |
bc09c219 MN |
1753 | if (!found && pvr_version_is(PVR_POWER7)) { |
1754 | /* check active counters for special buggy p7 overflow */ | |
1755 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1756 | event = cpuhw->event[i]; | |
1757 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 1758 | continue; |
bc09c219 MN |
1759 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
1760 | /* event has overflowed in a buggy way*/ | |
1761 | found = 1; | |
1762 | record_and_restart(event, | |
1763 | val[event->hw.idx - 1], | |
1764 | regs); | |
1765 | } | |
4574910e PM |
1766 | } |
1767 | } | |
6772faa1 | 1768 | if (!found && !nmi && printk_ratelimit()) |
bc09c219 | 1769 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); |
4574910e PM |
1770 | |
1771 | /* | |
1772 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 1773 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 1774 | * and thus allow interrupts to occur again. |
cdd6c482 | 1775 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
1776 | * we get back out of this interrupt. |
1777 | */ | |
ab7ef2e5 | 1778 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1779 | |
ca8f2d7f PM |
1780 | if (nmi) |
1781 | nmi_exit(); | |
1782 | else | |
db4fb5ac | 1783 | irq_exit(); |
4574910e PM |
1784 | } |
1785 | ||
3f6da390 | 1786 | static void power_pmu_setup(int cpu) |
01d0287f | 1787 | { |
cdd6c482 | 1788 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 1789 | |
f36a1a13 PM |
1790 | if (!ppmu) |
1791 | return; | |
01d0287f PM |
1792 | memset(cpuhw, 0, sizeof(*cpuhw)); |
1793 | cpuhw->mmcr[0] = MMCR0_FC; | |
1794 | } | |
1795 | ||
061d19f2 | 1796 | static int |
85cfabbc | 1797 | power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
3f6da390 PZ |
1798 | { |
1799 | unsigned int cpu = (long)hcpu; | |
1800 | ||
1801 | switch (action & ~CPU_TASKS_FROZEN) { | |
1802 | case CPU_UP_PREPARE: | |
1803 | power_pmu_setup(cpu); | |
1804 | break; | |
1805 | ||
1806 | default: | |
1807 | break; | |
1808 | } | |
1809 | ||
1810 | return NOTIFY_OK; | |
1811 | } | |
1812 | ||
061d19f2 | 1813 | int register_power_pmu(struct power_pmu *pmu) |
4574910e | 1814 | { |
079b3c56 PM |
1815 | if (ppmu) |
1816 | return -EBUSY; /* something's already registered */ | |
1817 | ||
1818 | ppmu = pmu; | |
1819 | pr_info("%s performance monitor hardware support registered\n", | |
1820 | pmu->name); | |
d095cd46 | 1821 | |
1c53a270 SB |
1822 | power_pmu.attr_groups = ppmu->attr_groups; |
1823 | ||
98fb1807 | 1824 | #ifdef MSR_HV |
d095cd46 PM |
1825 | /* |
1826 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
1827 | */ | |
1828 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 1829 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 1830 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 1831 | |
2e80a82a | 1832 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 PZ |
1833 | perf_cpu_notifier(power_pmu_notifier); |
1834 | ||
4574910e PM |
1835 | return 0; |
1836 | } |