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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
16 | #include <asm/reg.h> | |
17 | #include <asm/pmc.h> | |
01d0287f | 18 | #include <asm/machdep.h> |
0475f9ea | 19 | #include <asm/firmware.h> |
0bbd0d4b | 20 | #include <asm/ptrace.h> |
4574910e | 21 | |
cdd6c482 IM |
22 | struct cpu_hw_events { |
23 | int n_events; | |
4574910e PM |
24 | int n_percpu; |
25 | int disabled; | |
26 | int n_added; | |
ab7ef2e5 PM |
27 | int n_limited; |
28 | u8 pmcs_enabled; | |
cdd6c482 IM |
29 | struct perf_event *event[MAX_HWEVENTS]; |
30 | u64 events[MAX_HWEVENTS]; | |
31 | unsigned int flags[MAX_HWEVENTS]; | |
448d64f8 | 32 | unsigned long mmcr[3]; |
a8f90e90 PM |
33 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
34 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
35 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
36 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
37 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 LM |
38 | |
39 | unsigned int group_flag; | |
40 | int n_txn_start; | |
4574910e | 41 | }; |
cdd6c482 | 42 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e PM |
43 | |
44 | struct power_pmu *ppmu; | |
45 | ||
d095cd46 | 46 | /* |
57c0c15b | 47 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
48 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
49 | * hypervisor bit set in the MSR, or if we are running on a processor | |
50 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
51 | * then we need to use the FCHV bit to ignore kernel events. | |
52 | */ | |
cdd6c482 | 53 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 54 | |
98fb1807 PM |
55 | /* |
56 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
57 | * and a few other names are different. | |
58 | */ | |
59 | #ifdef CONFIG_PPC32 | |
60 | ||
61 | #define MMCR0_FCHV 0 | |
62 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
63 | ||
64 | #define SPRN_MMCRA SPRN_MMCR2 | |
65 | #define MMCRA_SAMPLE_ENABLE 0 | |
66 | ||
67 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
68 | { | |
69 | return 0; | |
70 | } | |
98fb1807 PM |
71 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
72 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
73 | { | |
74 | return 0; | |
75 | } | |
75382aa7 AB |
76 | static inline void perf_read_regs(struct pt_regs *regs) |
77 | { | |
78 | regs->result = 0; | |
79 | } | |
98fb1807 PM |
80 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
81 | { | |
82 | return 0; | |
83 | } | |
84 | ||
e6878835 | 85 | static inline int siar_valid(struct pt_regs *regs) |
86 | { | |
87 | return 1; | |
88 | } | |
89 | ||
98fb1807 PM |
90 | #endif /* CONFIG_PPC32 */ |
91 | ||
92 | /* | |
93 | * Things that are specific to 64-bit implementations. | |
94 | */ | |
95 | #ifdef CONFIG_PPC64 | |
96 | ||
97 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
98 | { | |
99 | unsigned long mmcra = regs->dsisr; | |
100 | ||
7a786832 | 101 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
102 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
103 | if (slot > 1) | |
104 | return 4 * (slot - 1); | |
105 | } | |
7a786832 | 106 | |
98fb1807 PM |
107 | return 0; |
108 | } | |
109 | ||
98fb1807 PM |
110 | /* |
111 | * The user wants a data address recorded. | |
112 | * If we're not doing instruction sampling, give them the SDAR | |
113 | * (sampled data address). If we are doing instruction sampling, then | |
114 | * only give them the SDAR if it corresponds to the instruction | |
e6878835 | 115 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC or |
116 | * the [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA. | |
98fb1807 PM |
117 | */ |
118 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
119 | { | |
120 | unsigned long mmcra = regs->dsisr; | |
e6878835 | 121 | unsigned long sdsync; |
122 | ||
123 | if (ppmu->flags & PPMU_SIAR_VALID) | |
124 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
125 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
126 | sdsync = POWER6_MMCRA_SDSYNC; | |
127 | else | |
128 | sdsync = MMCRA_SDSYNC; | |
98fb1807 PM |
129 | |
130 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) | |
131 | *addrp = mfspr(SPRN_SDAR); | |
132 | } | |
133 | ||
5682c460 | 134 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
135 | { |
136 | unsigned long sihv = MMCRA_SIHV; | |
137 | ||
138 | if (ppmu->flags & PPMU_ALT_SIPR) | |
139 | sihv = POWER6_MMCRA_SIHV; | |
140 | ||
5682c460 | 141 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
142 | } |
143 | ||
5682c460 | 144 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
145 | { |
146 | unsigned long sipr = MMCRA_SIPR; | |
147 | ||
148 | if (ppmu->flags & PPMU_ALT_SIPR) | |
149 | sipr = POWER6_MMCRA_SIPR; | |
150 | ||
5682c460 | 151 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
152 | } |
153 | ||
1ce447b9 BH |
154 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
155 | { | |
156 | if (regs->msr & MSR_PR) | |
157 | return PERF_RECORD_MISC_USER; | |
158 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
159 | return PERF_RECORD_MISC_HYPERVISOR; | |
160 | return PERF_RECORD_MISC_KERNEL; | |
161 | } | |
162 | ||
98fb1807 PM |
163 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
164 | { | |
75382aa7 | 165 | unsigned long use_siar = regs->result; |
98fb1807 | 166 | |
75382aa7 | 167 | if (!use_siar) |
1ce447b9 BH |
168 | return perf_flags_from_msr(regs); |
169 | ||
170 | /* | |
171 | * If we don't have flags in MMCRA, rather than using | |
172 | * the MSR, we intuit the flags from the address in | |
173 | * SIAR which should give slightly more reliable | |
174 | * results | |
175 | */ | |
176 | if (ppmu->flags & PPMU_NO_SIPR) { | |
177 | unsigned long siar = mfspr(SPRN_SIAR); | |
178 | if (siar >= PAGE_OFFSET) | |
179 | return PERF_RECORD_MISC_KERNEL; | |
180 | return PERF_RECORD_MISC_USER; | |
181 | } | |
98fb1807 | 182 | |
7abb840b | 183 | /* PR has priority over HV, so order below is important */ |
5682c460 | 184 | if (regs_sipr(regs)) |
7abb840b | 185 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
186 | |
187 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 188 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 189 | |
7abb840b | 190 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
191 | } |
192 | ||
193 | /* | |
194 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
195 | * on each interrupt. | |
75382aa7 AB |
196 | * Overload regs->result to specify whether we should use the MSR (result |
197 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
198 | */ |
199 | static inline void perf_read_regs(struct pt_regs *regs) | |
200 | { | |
75382aa7 AB |
201 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
202 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
203 | int use_siar; | |
204 | ||
5682c460 ME |
205 | regs->dsisr = mmcra; |
206 | ||
5c093efa AB |
207 | /* |
208 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
209 | * not valid. Use pt_regs. | |
210 | * | |
211 | * If it is a marked event use the SIAR. | |
212 | * | |
213 | * If the PMU doesn't update the SIAR for non marked events use | |
214 | * pt_regs. | |
215 | * | |
216 | * If the PMU has HV/PR flags then check to see if they | |
217 | * place the exception in userspace. If so, use pt_regs. In | |
218 | * continuous sampling mode the SIAR and the PMU exception are | |
219 | * not synchronised, so they may be many instructions apart. | |
220 | * This can result in confusing backtraces. We still want | |
221 | * hypervisor samples as well as samples in the kernel with | |
222 | * interrupts off hence the userspace check. | |
223 | */ | |
75382aa7 AB |
224 | if (TRAP(regs) != 0xf00) |
225 | use_siar = 0; | |
5c093efa AB |
226 | else if (marked) |
227 | use_siar = 1; | |
228 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
229 | use_siar = 0; | |
5682c460 | 230 | else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) |
75382aa7 AB |
231 | use_siar = 0; |
232 | else | |
233 | use_siar = 1; | |
234 | ||
75382aa7 | 235 | regs->result = use_siar; |
98fb1807 PM |
236 | } |
237 | ||
238 | /* | |
239 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
240 | * it as an NMI. | |
241 | */ | |
242 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
243 | { | |
244 | return !regs->softe; | |
245 | } | |
246 | ||
e6878835 | 247 | /* |
248 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
249 | * must be sampled only if the SIAR-valid bit is set. | |
250 | * | |
251 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
252 | * bit, assume that SIAR is valid. | |
253 | */ | |
254 | static inline int siar_valid(struct pt_regs *regs) | |
255 | { | |
256 | unsigned long mmcra = regs->dsisr; | |
257 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
258 | ||
259 | if ((ppmu->flags & PPMU_SIAR_VALID) && marked) | |
260 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
261 | ||
262 | return 1; | |
263 | } | |
264 | ||
98fb1807 PM |
265 | #endif /* CONFIG_PPC64 */ |
266 | ||
cdd6c482 | 267 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 268 | |
cdd6c482 | 269 | void perf_event_print_debug(void) |
4574910e PM |
270 | { |
271 | } | |
272 | ||
4574910e | 273 | /* |
57c0c15b | 274 | * Read one performance monitor counter (PMC). |
4574910e PM |
275 | */ |
276 | static unsigned long read_pmc(int idx) | |
277 | { | |
278 | unsigned long val; | |
279 | ||
280 | switch (idx) { | |
281 | case 1: | |
282 | val = mfspr(SPRN_PMC1); | |
283 | break; | |
284 | case 2: | |
285 | val = mfspr(SPRN_PMC2); | |
286 | break; | |
287 | case 3: | |
288 | val = mfspr(SPRN_PMC3); | |
289 | break; | |
290 | case 4: | |
291 | val = mfspr(SPRN_PMC4); | |
292 | break; | |
293 | case 5: | |
294 | val = mfspr(SPRN_PMC5); | |
295 | break; | |
296 | case 6: | |
297 | val = mfspr(SPRN_PMC6); | |
298 | break; | |
98fb1807 | 299 | #ifdef CONFIG_PPC64 |
4574910e PM |
300 | case 7: |
301 | val = mfspr(SPRN_PMC7); | |
302 | break; | |
303 | case 8: | |
304 | val = mfspr(SPRN_PMC8); | |
305 | break; | |
98fb1807 | 306 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
307 | default: |
308 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
309 | val = 0; | |
310 | } | |
311 | return val; | |
312 | } | |
313 | ||
314 | /* | |
315 | * Write one PMC. | |
316 | */ | |
317 | static void write_pmc(int idx, unsigned long val) | |
318 | { | |
319 | switch (idx) { | |
320 | case 1: | |
321 | mtspr(SPRN_PMC1, val); | |
322 | break; | |
323 | case 2: | |
324 | mtspr(SPRN_PMC2, val); | |
325 | break; | |
326 | case 3: | |
327 | mtspr(SPRN_PMC3, val); | |
328 | break; | |
329 | case 4: | |
330 | mtspr(SPRN_PMC4, val); | |
331 | break; | |
332 | case 5: | |
333 | mtspr(SPRN_PMC5, val); | |
334 | break; | |
335 | case 6: | |
336 | mtspr(SPRN_PMC6, val); | |
337 | break; | |
98fb1807 | 338 | #ifdef CONFIG_PPC64 |
4574910e PM |
339 | case 7: |
340 | mtspr(SPRN_PMC7, val); | |
341 | break; | |
342 | case 8: | |
343 | mtspr(SPRN_PMC8, val); | |
344 | break; | |
98fb1807 | 345 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
346 | default: |
347 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
348 | } | |
349 | } | |
350 | ||
351 | /* | |
352 | * Check if a set of events can all go on the PMU at once. | |
353 | * If they can't, this will look at alternative codes for the events | |
354 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 355 | * The feasible set is returned in event_id[]. |
4574910e | 356 | */ |
cdd6c482 IM |
357 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
358 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 359 | int n_ev) |
4574910e | 360 | { |
448d64f8 | 361 | unsigned long mask, value, nv; |
cdd6c482 IM |
362 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
363 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 364 | int i, j; |
448d64f8 PM |
365 | unsigned long addf = ppmu->add_fields; |
366 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 367 | |
a8f90e90 | 368 | if (n_ev > ppmu->n_counter) |
4574910e PM |
369 | return -1; |
370 | ||
371 | /* First see if the events will go on as-is */ | |
372 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 373 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
374 | && !ppmu->limited_pmc_event(event_id[i])) { |
375 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 376 | cpuhw->alternatives[i]); |
cdd6c482 | 377 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 378 | } |
cdd6c482 | 379 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 380 | &cpuhw->avalues[i][0])) |
4574910e | 381 | return -1; |
4574910e PM |
382 | } |
383 | value = mask = 0; | |
384 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
385 | nv = (value | cpuhw->avalues[i][0]) + |
386 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 387 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
388 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
389 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
390 | break; |
391 | value = nv; | |
e51ee31e | 392 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
393 | } |
394 | if (i == n_ev) | |
395 | return 0; /* all OK */ | |
396 | ||
397 | /* doesn't work, gather alternatives... */ | |
398 | if (!ppmu->get_alternatives) | |
399 | return -1; | |
400 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 401 | choice[i] = 0; |
cdd6c482 | 402 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 403 | cpuhw->alternatives[i]); |
4574910e | 404 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
405 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
406 | &cpuhw->amasks[i][j], | |
407 | &cpuhw->avalues[i][j]); | |
4574910e PM |
408 | } |
409 | ||
410 | /* enumerate all possibilities and see if any will work */ | |
411 | i = 0; | |
412 | j = -1; | |
413 | value = mask = nv = 0; | |
414 | while (i < n_ev) { | |
415 | if (j >= 0) { | |
416 | /* we're backtracking, restore context */ | |
417 | value = svalues[i]; | |
418 | mask = smasks[i]; | |
419 | j = choice[i]; | |
420 | } | |
421 | /* | |
cdd6c482 | 422 | * See if any alternative k for event_id i, |
4574910e PM |
423 | * where k > j, will satisfy the constraints. |
424 | */ | |
425 | while (++j < n_alt[i]) { | |
e51ee31e PM |
426 | nv = (value | cpuhw->avalues[i][j]) + |
427 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 428 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
429 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
430 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
431 | break; |
432 | } | |
433 | if (j >= n_alt[i]) { | |
434 | /* | |
435 | * No feasible alternative, backtrack | |
cdd6c482 | 436 | * to event_id i-1 and continue enumerating its |
4574910e PM |
437 | * alternatives from where we got up to. |
438 | */ | |
439 | if (--i < 0) | |
440 | return -1; | |
441 | } else { | |
442 | /* | |
cdd6c482 IM |
443 | * Found a feasible alternative for event_id i, |
444 | * remember where we got up to with this event_id, | |
445 | * go on to the next event_id, and start with | |
4574910e PM |
446 | * the first alternative for it. |
447 | */ | |
448 | choice[i] = j; | |
449 | svalues[i] = value; | |
450 | smasks[i] = mask; | |
451 | value = nv; | |
e51ee31e | 452 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
453 | ++i; |
454 | j = -1; | |
455 | } | |
456 | } | |
457 | ||
458 | /* OK, we have a feasible combination, tell the caller the solution */ | |
459 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 460 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
461 | return 0; |
462 | } | |
463 | ||
0475f9ea | 464 | /* |
cdd6c482 | 465 | * Check if newly-added events have consistent settings for |
0475f9ea | 466 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 467 | * added events. |
0475f9ea | 468 | */ |
cdd6c482 | 469 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 470 | int n_prev, int n_new) |
0475f9ea | 471 | { |
ab7ef2e5 PM |
472 | int eu = 0, ek = 0, eh = 0; |
473 | int i, n, first; | |
cdd6c482 | 474 | struct perf_event *event; |
0475f9ea PM |
475 | |
476 | n = n_prev + n_new; | |
477 | if (n <= 1) | |
478 | return 0; | |
479 | ||
ab7ef2e5 PM |
480 | first = 1; |
481 | for (i = 0; i < n; ++i) { | |
482 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
483 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
484 | continue; | |
485 | } | |
cdd6c482 | 486 | event = ctrs[i]; |
ab7ef2e5 | 487 | if (first) { |
cdd6c482 IM |
488 | eu = event->attr.exclude_user; |
489 | ek = event->attr.exclude_kernel; | |
490 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 491 | first = 0; |
cdd6c482 IM |
492 | } else if (event->attr.exclude_user != eu || |
493 | event->attr.exclude_kernel != ek || | |
494 | event->attr.exclude_hv != eh) { | |
0475f9ea | 495 | return -EAGAIN; |
ab7ef2e5 | 496 | } |
0475f9ea | 497 | } |
ab7ef2e5 PM |
498 | |
499 | if (eu || ek || eh) | |
500 | for (i = 0; i < n; ++i) | |
501 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
502 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
503 | ||
0475f9ea PM |
504 | return 0; |
505 | } | |
506 | ||
86c74ab3 EM |
507 | static u64 check_and_compute_delta(u64 prev, u64 val) |
508 | { | |
509 | u64 delta = (val - prev) & 0xfffffffful; | |
510 | ||
511 | /* | |
512 | * POWER7 can roll back counter values, if the new value is smaller | |
513 | * than the previous value it will cause the delta and the counter to | |
514 | * have bogus values unless we rolled a counter over. If a coutner is | |
515 | * rolled back, it will be smaller, but within 256, which is the maximum | |
516 | * number of events to rollback at once. If we dectect a rollback | |
517 | * return 0. This can lead to a small lack of precision in the | |
518 | * counters. | |
519 | */ | |
520 | if (prev > val && (prev - val) < 256) | |
521 | delta = 0; | |
522 | ||
523 | return delta; | |
524 | } | |
525 | ||
cdd6c482 | 526 | static void power_pmu_read(struct perf_event *event) |
4574910e | 527 | { |
98fb1807 | 528 | s64 val, delta, prev; |
4574910e | 529 | |
a4eaf7f1 PZ |
530 | if (event->hw.state & PERF_HES_STOPPED) |
531 | return; | |
532 | ||
cdd6c482 | 533 | if (!event->hw.idx) |
4574910e PM |
534 | return; |
535 | /* | |
536 | * Performance monitor interrupts come even when interrupts | |
537 | * are soft-disabled, as long as interrupts are hard-enabled. | |
538 | * Therefore we treat them like NMIs. | |
539 | */ | |
540 | do { | |
e7850595 | 541 | prev = local64_read(&event->hw.prev_count); |
4574910e | 542 | barrier(); |
cdd6c482 | 543 | val = read_pmc(event->hw.idx); |
86c74ab3 EM |
544 | delta = check_and_compute_delta(prev, val); |
545 | if (!delta) | |
546 | return; | |
e7850595 | 547 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 548 | |
e7850595 PZ |
549 | local64_add(delta, &event->count); |
550 | local64_sub(delta, &event->hw.period_left); | |
4574910e PM |
551 | } |
552 | ||
ab7ef2e5 PM |
553 | /* |
554 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
555 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 556 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
557 | */ |
558 | static int is_limited_pmc(int pmcnum) | |
559 | { | |
0bbd0d4b PM |
560 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
561 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
562 | } |
563 | ||
a8f90e90 | 564 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
565 | unsigned long pmc5, unsigned long pmc6) |
566 | { | |
cdd6c482 | 567 | struct perf_event *event; |
ab7ef2e5 PM |
568 | u64 val, prev, delta; |
569 | int i; | |
570 | ||
571 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 572 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 573 | if (!event->hw.idx) |
ab7ef2e5 | 574 | continue; |
cdd6c482 | 575 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 576 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 577 | event->hw.idx = 0; |
86c74ab3 EM |
578 | delta = check_and_compute_delta(prev, val); |
579 | if (delta) | |
580 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
581 | } |
582 | } | |
583 | ||
a8f90e90 | 584 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
585 | unsigned long pmc5, unsigned long pmc6) |
586 | { | |
cdd6c482 | 587 | struct perf_event *event; |
86c74ab3 | 588 | u64 val, prev; |
ab7ef2e5 PM |
589 | int i; |
590 | ||
591 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 592 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
593 | event->hw.idx = cpuhw->limited_hwidx[i]; |
594 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
595 | prev = local64_read(&event->hw.prev_count); |
596 | if (check_and_compute_delta(prev, val)) | |
597 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 598 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
599 | } |
600 | } | |
601 | ||
602 | /* | |
cdd6c482 | 603 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 604 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
605 | * other events. We try to keep the values from the limited |
606 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 607 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
608 | * the limited events as small and consistent as possible. |
609 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
610 | * both, and always in the same order, to minimize variability, |
611 | * and do it inside the same asm that writes MMCR0. | |
612 | */ | |
cdd6c482 | 613 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
614 | { |
615 | unsigned long pmc5, pmc6; | |
616 | ||
617 | if (!cpuhw->n_limited) { | |
618 | mtspr(SPRN_MMCR0, mmcr0); | |
619 | return; | |
620 | } | |
621 | ||
622 | /* | |
623 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
624 | * To ensure we don't get a performance monitor interrupt |
625 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 626 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 627 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
628 | */ |
629 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
630 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
631 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
632 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
633 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
634 | ||
635 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 636 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 637 | else |
a8f90e90 | 638 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
639 | |
640 | /* | |
cdd6c482 | 641 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
642 | * enable bits, if necessary. |
643 | */ | |
644 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
645 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
646 | } |
647 | ||
4574910e | 648 | /* |
cdd6c482 IM |
649 | * Disable all events to prevent PMU interrupts and to allow |
650 | * events to be added or removed. | |
4574910e | 651 | */ |
a4eaf7f1 | 652 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 653 | { |
cdd6c482 | 654 | struct cpu_hw_events *cpuhw; |
4574910e PM |
655 | unsigned long flags; |
656 | ||
f36a1a13 PM |
657 | if (!ppmu) |
658 | return; | |
4574910e | 659 | local_irq_save(flags); |
cdd6c482 | 660 | cpuhw = &__get_cpu_var(cpu_hw_events); |
4574910e | 661 | |
448d64f8 | 662 | if (!cpuhw->disabled) { |
4574910e PM |
663 | cpuhw->disabled = 1; |
664 | cpuhw->n_added = 0; | |
665 | ||
01d0287f PM |
666 | /* |
667 | * Check if we ever enabled the PMU on this cpu. | |
668 | */ | |
669 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 670 | ppc_enable_pmcs(); |
01d0287f PM |
671 | cpuhw->pmcs_enabled = 1; |
672 | } | |
673 | ||
f708223d PM |
674 | /* |
675 | * Disable instruction sampling if it was enabled | |
676 | */ | |
677 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
678 | mtspr(SPRN_MMCRA, | |
679 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
680 | mb(); | |
681 | } | |
682 | ||
4574910e | 683 | /* |
57c0c15b | 684 | * Set the 'freeze counters' bit. |
4574910e | 685 | * The barrier is to make sure the mtspr has been |
cdd6c482 | 686 | * executed and the PMU has frozen the events |
4574910e PM |
687 | * before we return. |
688 | */ | |
ab7ef2e5 | 689 | write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); |
4574910e PM |
690 | mb(); |
691 | } | |
692 | local_irq_restore(flags); | |
4574910e PM |
693 | } |
694 | ||
695 | /* | |
cdd6c482 IM |
696 | * Re-enable all events if disable == 0. |
697 | * If we were previously disabled and events were added, then | |
4574910e PM |
698 | * put the new config on the PMU. |
699 | */ | |
a4eaf7f1 | 700 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 701 | { |
cdd6c482 IM |
702 | struct perf_event *event; |
703 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
704 | unsigned long flags; |
705 | long i; | |
706 | unsigned long val; | |
707 | s64 left; | |
cdd6c482 | 708 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
709 | int n_lim; |
710 | int idx; | |
4574910e | 711 | |
f36a1a13 PM |
712 | if (!ppmu) |
713 | return; | |
4574910e | 714 | local_irq_save(flags); |
cdd6c482 | 715 | cpuhw = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
716 | if (!cpuhw->disabled) { |
717 | local_irq_restore(flags); | |
718 | return; | |
719 | } | |
4574910e PM |
720 | cpuhw->disabled = 0; |
721 | ||
722 | /* | |
cdd6c482 | 723 | * If we didn't change anything, or only removed events, |
4574910e PM |
724 | * no need to recalculate MMCR* settings and reset the PMCs. |
725 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 726 | * (possibly updated for removal of events). |
4574910e PM |
727 | */ |
728 | if (!cpuhw->n_added) { | |
f708223d | 729 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 730 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
cdd6c482 | 731 | if (cpuhw->n_events == 0) |
a6dbf93a | 732 | ppc_set_pmu_inuse(0); |
f708223d | 733 | goto out_enable; |
4574910e PM |
734 | } |
735 | ||
736 | /* | |
cdd6c482 | 737 | * Compute MMCR* values for the new set of events |
4574910e | 738 | */ |
cdd6c482 | 739 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
4574910e PM |
740 | cpuhw->mmcr)) { |
741 | /* shouldn't ever get here */ | |
742 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
743 | goto out; | |
744 | } | |
745 | ||
0475f9ea PM |
746 | /* |
747 | * Add in MMCR0 freeze bits corresponding to the | |
cdd6c482 IM |
748 | * attr.exclude_* bits for the first event. |
749 | * We have already checked that all events have the | |
750 | * same values for these bits as the first event. | |
0475f9ea | 751 | */ |
cdd6c482 IM |
752 | event = cpuhw->event[0]; |
753 | if (event->attr.exclude_user) | |
0475f9ea | 754 | cpuhw->mmcr[0] |= MMCR0_FCP; |
cdd6c482 IM |
755 | if (event->attr.exclude_kernel) |
756 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
757 | if (event->attr.exclude_hv) | |
0475f9ea PM |
758 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
759 | ||
4574910e PM |
760 | /* |
761 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
762 | * bit set and set the hardware events to their initial values. |
763 | * Then unfreeze the events. | |
4574910e | 764 | */ |
a6dbf93a | 765 | ppc_set_pmu_inuse(1); |
f708223d | 766 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
767 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
768 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
769 | | MMCR0_FC); | |
770 | ||
771 | /* | |
cdd6c482 | 772 | * Read off any pre-existing events that need to move |
4574910e PM |
773 | * to another PMC. |
774 | */ | |
cdd6c482 IM |
775 | for (i = 0; i < cpuhw->n_events; ++i) { |
776 | event = cpuhw->event[i]; | |
777 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
778 | power_pmu_read(event); | |
779 | write_pmc(event->hw.idx, 0); | |
780 | event->hw.idx = 0; | |
4574910e PM |
781 | } |
782 | } | |
783 | ||
784 | /* | |
cdd6c482 | 785 | * Initialize the PMCs for all the new and moved events. |
4574910e | 786 | */ |
ab7ef2e5 | 787 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
788 | for (i = 0; i < cpuhw->n_events; ++i) { |
789 | event = cpuhw->event[i]; | |
790 | if (event->hw.idx) | |
4574910e | 791 | continue; |
ab7ef2e5 PM |
792 | idx = hwc_index[i] + 1; |
793 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 794 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
795 | cpuhw->limited_hwidx[n_lim] = idx; |
796 | ++n_lim; | |
797 | continue; | |
798 | } | |
4574910e | 799 | val = 0; |
cdd6c482 | 800 | if (event->hw.sample_period) { |
e7850595 | 801 | left = local64_read(&event->hw.period_left); |
4574910e PM |
802 | if (left < 0x80000000L) |
803 | val = 0x80000000L - left; | |
804 | } | |
e7850595 | 805 | local64_set(&event->hw.prev_count, val); |
cdd6c482 | 806 | event->hw.idx = idx; |
a4eaf7f1 PZ |
807 | if (event->hw.state & PERF_HES_STOPPED) |
808 | val = 0; | |
ab7ef2e5 | 809 | write_pmc(idx, val); |
cdd6c482 | 810 | perf_event_update_userpage(event); |
4574910e | 811 | } |
ab7ef2e5 | 812 | cpuhw->n_limited = n_lim; |
4574910e | 813 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
814 | |
815 | out_enable: | |
816 | mb(); | |
ab7ef2e5 | 817 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 818 | |
f708223d PM |
819 | /* |
820 | * Enable instruction sampling if necessary | |
821 | */ | |
822 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
823 | mb(); | |
824 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
825 | } | |
826 | ||
4574910e PM |
827 | out: |
828 | local_irq_restore(flags); | |
829 | } | |
830 | ||
cdd6c482 IM |
831 | static int collect_events(struct perf_event *group, int max_count, |
832 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 833 | unsigned int *flags) |
4574910e PM |
834 | { |
835 | int n = 0; | |
cdd6c482 | 836 | struct perf_event *event; |
4574910e | 837 | |
cdd6c482 | 838 | if (!is_software_event(group)) { |
4574910e PM |
839 | if (n >= max_count) |
840 | return -1; | |
841 | ctrs[n] = group; | |
cdd6c482 | 842 | flags[n] = group->hw.event_base; |
4574910e PM |
843 | events[n++] = group->hw.config; |
844 | } | |
a8f90e90 | 845 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
846 | if (!is_software_event(event) && |
847 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
848 | if (n >= max_count) |
849 | return -1; | |
cdd6c482 IM |
850 | ctrs[n] = event; |
851 | flags[n] = event->hw.event_base; | |
852 | events[n++] = event->hw.config; | |
4574910e PM |
853 | } |
854 | } | |
855 | return n; | |
856 | } | |
857 | ||
4574910e | 858 | /* |
cdd6c482 IM |
859 | * Add a event to the PMU. |
860 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 861 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
862 | * actual work of reconfiguring the PMU. |
863 | */ | |
a4eaf7f1 | 864 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 865 | { |
cdd6c482 | 866 | struct cpu_hw_events *cpuhw; |
4574910e | 867 | unsigned long flags; |
4574910e PM |
868 | int n0; |
869 | int ret = -EAGAIN; | |
870 | ||
871 | local_irq_save(flags); | |
33696fc0 | 872 | perf_pmu_disable(event->pmu); |
4574910e PM |
873 | |
874 | /* | |
cdd6c482 | 875 | * Add the event to the list (if there is room) |
4574910e PM |
876 | * and check whether the total set is still feasible. |
877 | */ | |
cdd6c482 IM |
878 | cpuhw = &__get_cpu_var(cpu_hw_events); |
879 | n0 = cpuhw->n_events; | |
a8f90e90 | 880 | if (n0 >= ppmu->n_counter) |
4574910e | 881 | goto out; |
cdd6c482 IM |
882 | cpuhw->event[n0] = event; |
883 | cpuhw->events[n0] = event->hw.config; | |
884 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 885 | |
f53d168c | 886 | /* |
887 | * This event may have been disabled/stopped in record_and_restart() | |
888 | * because we exceeded the ->event_limit. If re-starting the event, | |
889 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
890 | * notification is re-enabled. | |
891 | */ | |
a4eaf7f1 PZ |
892 | if (!(ef_flags & PERF_EF_START)) |
893 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 894 | else |
895 | event->hw.state = 0; | |
a4eaf7f1 | 896 | |
8e6d5573 LM |
897 | /* |
898 | * If group events scheduling transaction was started, | |
25985edc | 899 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
900 | * at commit time(->commit_txn) as a whole |
901 | */ | |
8d2cacbb | 902 | if (cpuhw->group_flag & PERF_EVENT_TXN) |
8e6d5573 LM |
903 | goto nocheck; |
904 | ||
cdd6c482 | 905 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 906 | goto out; |
e51ee31e | 907 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 908 | goto out; |
cdd6c482 | 909 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
910 | |
911 | nocheck: | |
cdd6c482 | 912 | ++cpuhw->n_events; |
4574910e PM |
913 | ++cpuhw->n_added; |
914 | ||
915 | ret = 0; | |
916 | out: | |
33696fc0 | 917 | perf_pmu_enable(event->pmu); |
4574910e PM |
918 | local_irq_restore(flags); |
919 | return ret; | |
920 | } | |
921 | ||
922 | /* | |
cdd6c482 | 923 | * Remove a event from the PMU. |
4574910e | 924 | */ |
a4eaf7f1 | 925 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 926 | { |
cdd6c482 | 927 | struct cpu_hw_events *cpuhw; |
4574910e | 928 | long i; |
4574910e PM |
929 | unsigned long flags; |
930 | ||
931 | local_irq_save(flags); | |
33696fc0 | 932 | perf_pmu_disable(event->pmu); |
4574910e | 933 | |
cdd6c482 IM |
934 | power_pmu_read(event); |
935 | ||
936 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
937 | for (i = 0; i < cpuhw->n_events; ++i) { | |
938 | if (event == cpuhw->event[i]) { | |
219a92a4 | 939 | while (++i < cpuhw->n_events) { |
cdd6c482 | 940 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
941 | cpuhw->events[i-1] = cpuhw->events[i]; |
942 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
943 | } | |
cdd6c482 IM |
944 | --cpuhw->n_events; |
945 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
946 | if (event->hw.idx) { | |
947 | write_pmc(event->hw.idx, 0); | |
948 | event->hw.idx = 0; | |
ab7ef2e5 | 949 | } |
cdd6c482 | 950 | perf_event_update_userpage(event); |
4574910e PM |
951 | break; |
952 | } | |
953 | } | |
ab7ef2e5 | 954 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 955 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
956 | break; |
957 | if (i < cpuhw->n_limited) { | |
958 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 959 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
960 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
961 | } | |
962 | --cpuhw->n_limited; | |
963 | } | |
cdd6c482 IM |
964 | if (cpuhw->n_events == 0) { |
965 | /* disable exceptions if no events are running */ | |
4574910e PM |
966 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
967 | } | |
968 | ||
33696fc0 | 969 | perf_pmu_enable(event->pmu); |
4574910e PM |
970 | local_irq_restore(flags); |
971 | } | |
972 | ||
8a7b8cb9 | 973 | /* |
a4eaf7f1 PZ |
974 | * POWER-PMU does not support disabling individual counters, hence |
975 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 976 | */ |
a4eaf7f1 PZ |
977 | |
978 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 979 | { |
8a7b8cb9 | 980 | unsigned long flags; |
a4eaf7f1 | 981 | s64 left; |
9a45a940 | 982 | unsigned long val; |
8a7b8cb9 | 983 | |
cdd6c482 | 984 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 985 | return; |
a4eaf7f1 PZ |
986 | |
987 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
988 | return; | |
989 | ||
990 | if (ef_flags & PERF_EF_RELOAD) | |
991 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
992 | ||
993 | local_irq_save(flags); | |
994 | perf_pmu_disable(event->pmu); | |
995 | ||
996 | event->hw.state = 0; | |
997 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
998 | |
999 | val = 0; | |
1000 | if (left < 0x80000000L) | |
1001 | val = 0x80000000L - left; | |
1002 | ||
1003 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1004 | |
1005 | perf_event_update_userpage(event); | |
1006 | perf_pmu_enable(event->pmu); | |
1007 | local_irq_restore(flags); | |
1008 | } | |
1009 | ||
1010 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1011 | { | |
1012 | unsigned long flags; | |
1013 | ||
1014 | if (!event->hw.idx || !event->hw.sample_period) | |
1015 | return; | |
1016 | ||
1017 | if (event->hw.state & PERF_HES_STOPPED) | |
1018 | return; | |
1019 | ||
8a7b8cb9 | 1020 | local_irq_save(flags); |
33696fc0 | 1021 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1022 | |
cdd6c482 | 1023 | power_pmu_read(event); |
a4eaf7f1 PZ |
1024 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1025 | write_pmc(event->hw.idx, 0); | |
1026 | ||
cdd6c482 | 1027 | perf_event_update_userpage(event); |
33696fc0 | 1028 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1029 | local_irq_restore(flags); |
1030 | } | |
1031 | ||
8e6d5573 LM |
1032 | /* |
1033 | * Start group events scheduling transaction | |
1034 | * Set the flag to make pmu::enable() not perform the | |
1035 | * schedulability test, it will be performed at commit time | |
1036 | */ | |
51b0fe39 | 1037 | void power_pmu_start_txn(struct pmu *pmu) |
8e6d5573 LM |
1038 | { |
1039 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1040 | ||
33696fc0 | 1041 | perf_pmu_disable(pmu); |
8d2cacbb | 1042 | cpuhw->group_flag |= PERF_EVENT_TXN; |
8e6d5573 LM |
1043 | cpuhw->n_txn_start = cpuhw->n_events; |
1044 | } | |
1045 | ||
1046 | /* | |
1047 | * Stop group events scheduling transaction | |
1048 | * Clear the flag and pmu::enable() will perform the | |
1049 | * schedulability test. | |
1050 | */ | |
51b0fe39 | 1051 | void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 LM |
1052 | { |
1053 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1054 | ||
8d2cacbb | 1055 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1056 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1057 | } |
1058 | ||
1059 | /* | |
1060 | * Commit group events scheduling transaction | |
1061 | * Perform the group schedulability test as a whole | |
1062 | * Return 0 if success | |
1063 | */ | |
51b0fe39 | 1064 | int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1065 | { |
1066 | struct cpu_hw_events *cpuhw; | |
1067 | long i, n; | |
1068 | ||
1069 | if (!ppmu) | |
1070 | return -EAGAIN; | |
1071 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1072 | n = cpuhw->n_events; | |
1073 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1074 | return -EAGAIN; | |
1075 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1076 | if (i < 0) | |
1077 | return -EAGAIN; | |
1078 | ||
1079 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1080 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1081 | ||
8d2cacbb | 1082 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1083 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1084 | return 0; |
1085 | } | |
1086 | ||
ab7ef2e5 | 1087 | /* |
cdd6c482 | 1088 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1089 | * or 0 if not. |
cdd6c482 | 1090 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1091 | * that a limited PMC can count, doesn't require interrupts, and |
1092 | * doesn't exclude any processor mode. | |
1093 | */ | |
cdd6c482 | 1094 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1095 | unsigned int flags) |
1096 | { | |
1097 | int n; | |
ef923214 | 1098 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1099 | |
cdd6c482 IM |
1100 | if (event->attr.exclude_user |
1101 | || event->attr.exclude_kernel | |
1102 | || event->attr.exclude_hv | |
1103 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1104 | return 0; |
1105 | ||
1106 | if (ppmu->limited_pmc_event(ev)) | |
1107 | return 1; | |
1108 | ||
1109 | /* | |
cdd6c482 | 1110 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1111 | * see if any alternative code goes on a limited PMC. |
1112 | */ | |
1113 | if (!ppmu->get_alternatives) | |
1114 | return 0; | |
1115 | ||
1116 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1117 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1118 | |
ef923214 | 1119 | return n > 0; |
ab7ef2e5 PM |
1120 | } |
1121 | ||
1122 | /* | |
cdd6c482 IM |
1123 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1124 | * and return the event_id code, or 0 if there is no such alternative. | |
1125 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1126 | */ |
ef923214 | 1127 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1128 | { |
ef923214 | 1129 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1130 | int n; |
1131 | ||
1132 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1133 | n = ppmu->get_alternatives(ev, flags, alt); | |
1134 | if (!n) | |
1135 | return 0; | |
1136 | return alt[0]; | |
1137 | } | |
1138 | ||
cdd6c482 IM |
1139 | /* Number of perf_events counting hardware events */ |
1140 | static atomic_t num_events; | |
7595d63b PM |
1141 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1142 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1143 | ||
1144 | /* | |
cdd6c482 | 1145 | * Release the PMU if this is the last perf_event. |
7595d63b | 1146 | */ |
cdd6c482 | 1147 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1148 | { |
cdd6c482 | 1149 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1150 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1151 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1152 | release_pmc_hardware(); |
1153 | mutex_unlock(&pmc_reserve_mutex); | |
1154 | } | |
1155 | } | |
1156 | ||
106b506c | 1157 | /* |
cdd6c482 | 1158 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1159 | */ |
1160 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1161 | { | |
1162 | unsigned long type, op, result; | |
1163 | int ev; | |
1164 | ||
1165 | if (!ppmu->cache_events) | |
1166 | return -EINVAL; | |
1167 | ||
1168 | /* unpack config */ | |
1169 | type = config & 0xff; | |
1170 | op = (config >> 8) & 0xff; | |
1171 | result = (config >> 16) & 0xff; | |
1172 | ||
1173 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1174 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1175 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1176 | return -EINVAL; | |
1177 | ||
1178 | ev = (*ppmu->cache_events)[type][op][result]; | |
1179 | if (ev == 0) | |
1180 | return -EOPNOTSUPP; | |
1181 | if (ev == -1) | |
1182 | return -EINVAL; | |
1183 | *eventp = ev; | |
1184 | return 0; | |
1185 | } | |
1186 | ||
b0a873eb | 1187 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1188 | { |
ef923214 PM |
1189 | u64 ev; |
1190 | unsigned long flags; | |
cdd6c482 IM |
1191 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1192 | u64 events[MAX_HWEVENTS]; | |
1193 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1194 | int n; |
7595d63b | 1195 | int err; |
cdd6c482 | 1196 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1197 | |
1198 | if (!ppmu) | |
b0a873eb PZ |
1199 | return -ENOENT; |
1200 | ||
2481c5fa SE |
1201 | /* does not support taken branch sampling */ |
1202 | if (has_branch_stack(event)) | |
1203 | return -EOPNOTSUPP; | |
1204 | ||
cdd6c482 | 1205 | switch (event->attr.type) { |
106b506c | 1206 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1207 | ev = event->attr.config; |
9aaa131a | 1208 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1209 | return -EOPNOTSUPP; |
4574910e | 1210 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1211 | break; |
1212 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1213 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1214 | if (err) |
b0a873eb | 1215 | return err; |
106b506c PM |
1216 | break; |
1217 | case PERF_TYPE_RAW: | |
cdd6c482 | 1218 | ev = event->attr.config; |
106b506c | 1219 | break; |
90c8f954 | 1220 | default: |
b0a873eb | 1221 | return -ENOENT; |
4574910e | 1222 | } |
b0a873eb | 1223 | |
cdd6c482 IM |
1224 | event->hw.config_base = ev; |
1225 | event->hw.idx = 0; | |
4574910e | 1226 | |
0475f9ea PM |
1227 | /* |
1228 | * If we are not running on a hypervisor, force the | |
1229 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1230 | * the user set it to. |
0475f9ea PM |
1231 | */ |
1232 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1233 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1234 | |
1235 | /* | |
cdd6c482 | 1236 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1237 | * PM_RUN_* events interchangeably with their non RUN_* |
1238 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1239 | * XXX we should check if the task is an idle task. | |
1240 | */ | |
1241 | flags = 0; | |
57fa7214 | 1242 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1243 | flags |= PPMU_ONLY_COUNT_RUN; |
1244 | ||
1245 | /* | |
cdd6c482 IM |
1246 | * If this machine has limited events, check whether this |
1247 | * event_id could go on a limited event. | |
ab7ef2e5 | 1248 | */ |
0bbd0d4b | 1249 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1250 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1251 | flags |= PPMU_LIMITED_PMC_OK; |
1252 | } else if (ppmu->limited_pmc_event(ev)) { | |
1253 | /* | |
cdd6c482 | 1254 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1255 | * but we can't use a limited PMC; see if any |
1256 | * alternative goes on a normal PMC. | |
1257 | */ | |
1258 | ev = normal_pmc_alternative(ev, flags); | |
1259 | if (!ev) | |
b0a873eb | 1260 | return -EINVAL; |
ab7ef2e5 PM |
1261 | } |
1262 | } | |
1263 | ||
4574910e PM |
1264 | /* |
1265 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1266 | * other hardware events in the group. We assume the event |
4574910e PM |
1267 | * hasn't been linked into its leader's sibling list at this point. |
1268 | */ | |
1269 | n = 0; | |
cdd6c482 | 1270 | if (event->group_leader != event) { |
a8f90e90 | 1271 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1272 | ctrs, events, cflags); |
4574910e | 1273 | if (n < 0) |
b0a873eb | 1274 | return -EINVAL; |
4574910e | 1275 | } |
0475f9ea | 1276 | events[n] = ev; |
cdd6c482 | 1277 | ctrs[n] = event; |
ab7ef2e5 PM |
1278 | cflags[n] = flags; |
1279 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1280 | return -EINVAL; |
e51ee31e | 1281 | |
cdd6c482 | 1282 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1283 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
cdd6c482 | 1284 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1285 | if (err) |
b0a873eb | 1286 | return -EINVAL; |
4574910e | 1287 | |
cdd6c482 IM |
1288 | event->hw.config = events[n]; |
1289 | event->hw.event_base = cflags[n]; | |
1290 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1291 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b PM |
1292 | |
1293 | /* | |
1294 | * See if we need to reserve the PMU. | |
cdd6c482 | 1295 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1296 | * mutex to ensure that we don't race with another task doing |
1297 | * reserve_pmc_hardware or release_pmc_hardware. | |
1298 | */ | |
1299 | err = 0; | |
cdd6c482 | 1300 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1301 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1302 | if (atomic_read(&num_events) == 0 && |
1303 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1304 | err = -EBUSY; |
1305 | else | |
cdd6c482 | 1306 | atomic_inc(&num_events); |
7595d63b PM |
1307 | mutex_unlock(&pmc_reserve_mutex); |
1308 | } | |
cdd6c482 | 1309 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1310 | |
b0a873eb | 1311 | return err; |
4574910e PM |
1312 | } |
1313 | ||
35edc2a5 PZ |
1314 | static int power_pmu_event_idx(struct perf_event *event) |
1315 | { | |
1316 | return event->hw.idx; | |
1317 | } | |
1318 | ||
1c53a270 SB |
1319 | ssize_t power_events_sysfs_show(struct device *dev, |
1320 | struct device_attribute *attr, char *page) | |
1321 | { | |
1322 | struct perf_pmu_events_attr *pmu_attr; | |
1323 | ||
1324 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
1325 | ||
1326 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
1327 | } | |
1328 | ||
b0a873eb | 1329 | struct pmu power_pmu = { |
a4eaf7f1 PZ |
1330 | .pmu_enable = power_pmu_enable, |
1331 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1332 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1333 | .add = power_pmu_add, |
1334 | .del = power_pmu_del, | |
1335 | .start = power_pmu_start, | |
1336 | .stop = power_pmu_stop, | |
b0a873eb | 1337 | .read = power_pmu_read, |
b0a873eb PZ |
1338 | .start_txn = power_pmu_start_txn, |
1339 | .cancel_txn = power_pmu_cancel_txn, | |
1340 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1341 | .event_idx = power_pmu_event_idx, |
b0a873eb PZ |
1342 | }; |
1343 | ||
e6878835 | 1344 | |
4574910e | 1345 | /* |
57c0c15b | 1346 | * A counter has overflowed; update its count and record |
4574910e PM |
1347 | * things if requested. Note that interrupts are hard-disabled |
1348 | * here so there is no possibility of being interrupted. | |
1349 | */ | |
cdd6c482 | 1350 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1351 | struct pt_regs *regs) |
4574910e | 1352 | { |
cdd6c482 | 1353 | u64 period = event->hw.sample_period; |
4574910e PM |
1354 | s64 prev, delta, left; |
1355 | int record = 0; | |
1356 | ||
a4eaf7f1 PZ |
1357 | if (event->hw.state & PERF_HES_STOPPED) { |
1358 | write_pmc(event->hw.idx, 0); | |
1359 | return; | |
1360 | } | |
1361 | ||
4574910e | 1362 | /* we don't have to worry about interrupts here */ |
e7850595 | 1363 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 1364 | delta = check_and_compute_delta(prev, val); |
e7850595 | 1365 | local64_add(delta, &event->count); |
4574910e PM |
1366 | |
1367 | /* | |
cdd6c482 | 1368 | * See if the total period for this event has expired, |
4574910e PM |
1369 | * and update for the next period. |
1370 | */ | |
1371 | val = 0; | |
e7850595 | 1372 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
1373 | if (delta == 0) |
1374 | left++; | |
60db5e09 | 1375 | if (period) { |
4574910e | 1376 | if (left <= 0) { |
60db5e09 | 1377 | left += period; |
4574910e | 1378 | if (left <= 0) |
60db5e09 | 1379 | left = period; |
e6878835 | 1380 | record = siar_valid(regs); |
4bca770e | 1381 | event->hw.last_period = event->hw.sample_period; |
4574910e | 1382 | } |
98fb1807 PM |
1383 | if (left < 0x80000000LL) |
1384 | val = 0x80000000LL - left; | |
4574910e | 1385 | } |
4574910e | 1386 | |
a4eaf7f1 PZ |
1387 | write_pmc(event->hw.idx, val); |
1388 | local64_set(&event->hw.prev_count, val); | |
1389 | local64_set(&event->hw.period_left, left); | |
1390 | perf_event_update_userpage(event); | |
1391 | ||
4574910e PM |
1392 | /* |
1393 | * Finally record data if requested. | |
1394 | */ | |
0bbd0d4b | 1395 | if (record) { |
dc1d628a PZ |
1396 | struct perf_sample_data data; |
1397 | ||
fd0d000b | 1398 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 1399 | |
cdd6c482 | 1400 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
1401 | perf_get_data_addr(regs, &data.addr); |
1402 | ||
a8b0ca17 | 1403 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1404 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
1405 | } |
1406 | } | |
1407 | ||
1408 | /* | |
1409 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 1410 | * for an event_id. |
0bbd0d4b PM |
1411 | */ |
1412 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1413 | { | |
98fb1807 | 1414 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 1415 | |
98fb1807 PM |
1416 | if (flags) |
1417 | return flags; | |
cdd6c482 IM |
1418 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
1419 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
1420 | } |
1421 | ||
1422 | /* | |
1423 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 1424 | * for an event_id. |
0bbd0d4b PM |
1425 | */ |
1426 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1427 | { | |
75382aa7 | 1428 | unsigned long use_siar = regs->result; |
0bbd0d4b | 1429 | |
e6878835 | 1430 | if (use_siar && siar_valid(regs)) |
75382aa7 | 1431 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 1432 | else if (use_siar) |
1433 | return 0; // no valid instruction pointer | |
75382aa7 | 1434 | else |
1ce447b9 | 1435 | return regs->nip; |
4574910e PM |
1436 | } |
1437 | ||
bc09c219 | 1438 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 1439 | { |
0837e324 AB |
1440 | /* |
1441 | * Events on POWER7 can roll back if a speculative event doesn't | |
1442 | * eventually complete. Unfortunately in some rare cases they will | |
1443 | * raise a performance monitor exception. We need to catch this to | |
1444 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
1445 | * cycles from overflow. | |
1446 | * | |
1447 | * We only do this if the first pass fails to find any overflowing | |
1448 | * PMCs because a user might set a period of less than 256 and we | |
1449 | * don't want to mistakenly reset them. | |
1450 | */ | |
bc09c219 MN |
1451 | if ((0x80000000 - val) <= 256) |
1452 | return true; | |
1453 | ||
1454 | return false; | |
1455 | } | |
1456 | ||
1457 | static bool pmc_overflow(unsigned long val) | |
1458 | { | |
1459 | if ((int)val < 0) | |
0837e324 AB |
1460 | return true; |
1461 | ||
1462 | return false; | |
1463 | } | |
1464 | ||
4574910e PM |
1465 | /* |
1466 | * Performance monitor interrupt stuff | |
1467 | */ | |
cdd6c482 | 1468 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 1469 | { |
bc09c219 | 1470 | int i, j; |
cdd6c482 IM |
1471 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); |
1472 | struct perf_event *event; | |
bc09c219 MN |
1473 | unsigned long val[8]; |
1474 | int found, active; | |
ca8f2d7f PM |
1475 | int nmi; |
1476 | ||
ab7ef2e5 | 1477 | if (cpuhw->n_limited) |
a8f90e90 | 1478 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
1479 | mfspr(SPRN_PMC6)); |
1480 | ||
98fb1807 | 1481 | perf_read_regs(regs); |
0bbd0d4b | 1482 | |
98fb1807 | 1483 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
1484 | if (nmi) |
1485 | nmi_enter(); | |
1486 | else | |
1487 | irq_enter(); | |
4574910e | 1488 | |
bc09c219 MN |
1489 | /* Read all the PMCs since we'll need them a bunch of times */ |
1490 | for (i = 0; i < ppmu->n_counter; ++i) | |
1491 | val[i] = read_pmc(i + 1); | |
1492 | ||
1493 | /* Try to find what caused the IRQ */ | |
1494 | found = 0; | |
1495 | for (i = 0; i < ppmu->n_counter; ++i) { | |
1496 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 1497 | continue; |
bc09c219 MN |
1498 | if (is_limited_pmc(i + 1)) |
1499 | continue; /* these won't generate IRQs */ | |
1500 | /* | |
1501 | * We've found one that's overflowed. For active | |
1502 | * counters we need to log this. For inactive | |
1503 | * counters, we need to reset it anyway | |
1504 | */ | |
1505 | found = 1; | |
1506 | active = 0; | |
1507 | for (j = 0; j < cpuhw->n_events; ++j) { | |
1508 | event = cpuhw->event[j]; | |
1509 | if (event->hw.idx == (i + 1)) { | |
1510 | active = 1; | |
1511 | record_and_restart(event, val[i], regs); | |
1512 | break; | |
1513 | } | |
4574910e | 1514 | } |
bc09c219 MN |
1515 | if (!active) |
1516 | /* reset non active counters that have overflowed */ | |
1517 | write_pmc(i + 1, 0); | |
4574910e | 1518 | } |
bc09c219 MN |
1519 | if (!found && pvr_version_is(PVR_POWER7)) { |
1520 | /* check active counters for special buggy p7 overflow */ | |
1521 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1522 | event = cpuhw->event[i]; | |
1523 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 1524 | continue; |
bc09c219 MN |
1525 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
1526 | /* event has overflowed in a buggy way*/ | |
1527 | found = 1; | |
1528 | record_and_restart(event, | |
1529 | val[event->hw.idx - 1], | |
1530 | regs); | |
1531 | } | |
4574910e PM |
1532 | } |
1533 | } | |
bc09c219 MN |
1534 | if ((!found) && printk_ratelimit()) |
1535 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); | |
4574910e PM |
1536 | |
1537 | /* | |
1538 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 1539 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 1540 | * and thus allow interrupts to occur again. |
cdd6c482 | 1541 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
1542 | * we get back out of this interrupt. |
1543 | */ | |
ab7ef2e5 | 1544 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1545 | |
ca8f2d7f PM |
1546 | if (nmi) |
1547 | nmi_exit(); | |
1548 | else | |
db4fb5ac | 1549 | irq_exit(); |
4574910e PM |
1550 | } |
1551 | ||
3f6da390 | 1552 | static void power_pmu_setup(int cpu) |
01d0287f | 1553 | { |
cdd6c482 | 1554 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 1555 | |
f36a1a13 PM |
1556 | if (!ppmu) |
1557 | return; | |
01d0287f PM |
1558 | memset(cpuhw, 0, sizeof(*cpuhw)); |
1559 | cpuhw->mmcr[0] = MMCR0_FC; | |
1560 | } | |
1561 | ||
3f6da390 | 1562 | static int __cpuinit |
85cfabbc | 1563 | power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
3f6da390 PZ |
1564 | { |
1565 | unsigned int cpu = (long)hcpu; | |
1566 | ||
1567 | switch (action & ~CPU_TASKS_FROZEN) { | |
1568 | case CPU_UP_PREPARE: | |
1569 | power_pmu_setup(cpu); | |
1570 | break; | |
1571 | ||
1572 | default: | |
1573 | break; | |
1574 | } | |
1575 | ||
1576 | return NOTIFY_OK; | |
1577 | } | |
1578 | ||
77c2342a | 1579 | int __cpuinit register_power_pmu(struct power_pmu *pmu) |
4574910e | 1580 | { |
079b3c56 PM |
1581 | if (ppmu) |
1582 | return -EBUSY; /* something's already registered */ | |
1583 | ||
1584 | ppmu = pmu; | |
1585 | pr_info("%s performance monitor hardware support registered\n", | |
1586 | pmu->name); | |
d095cd46 | 1587 | |
1c53a270 SB |
1588 | power_pmu.attr_groups = ppmu->attr_groups; |
1589 | ||
98fb1807 | 1590 | #ifdef MSR_HV |
d095cd46 PM |
1591 | /* |
1592 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
1593 | */ | |
1594 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 1595 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 1596 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 1597 | |
2e80a82a | 1598 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 PZ |
1599 | perf_cpu_notifier(power_pmu_notifier); |
1600 | ||
4574910e PM |
1601 | return 0; |
1602 | } |