Commit | Line | Data |
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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
16 | #include <asm/reg.h> | |
17 | #include <asm/pmc.h> | |
01d0287f | 18 | #include <asm/machdep.h> |
0475f9ea | 19 | #include <asm/firmware.h> |
0bbd0d4b | 20 | #include <asm/ptrace.h> |
4574910e | 21 | |
3925f46b AK |
22 | #define BHRB_MAX_ENTRIES 32 |
23 | #define BHRB_TARGET 0x0000000000000002 | |
24 | #define BHRB_PREDICTION 0x0000000000000001 | |
25 | #define BHRB_EA 0xFFFFFFFFFFFFFFFC | |
26 | ||
cdd6c482 IM |
27 | struct cpu_hw_events { |
28 | int n_events; | |
4574910e PM |
29 | int n_percpu; |
30 | int disabled; | |
31 | int n_added; | |
ab7ef2e5 PM |
32 | int n_limited; |
33 | u8 pmcs_enabled; | |
cdd6c482 IM |
34 | struct perf_event *event[MAX_HWEVENTS]; |
35 | u64 events[MAX_HWEVENTS]; | |
36 | unsigned int flags[MAX_HWEVENTS]; | |
448d64f8 | 37 | unsigned long mmcr[3]; |
a8f90e90 PM |
38 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
39 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
40 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
41 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
42 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 LM |
43 | |
44 | unsigned int group_flag; | |
45 | int n_txn_start; | |
3925f46b AK |
46 | |
47 | /* BHRB bits */ | |
48 | u64 bhrb_filter; /* BHRB HW branch filter */ | |
49 | int bhrb_users; | |
50 | void *bhrb_context; | |
51 | struct perf_branch_stack bhrb_stack; | |
52 | struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; | |
4574910e | 53 | }; |
3925f46b | 54 | |
cdd6c482 | 55 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e PM |
56 | |
57 | struct power_pmu *ppmu; | |
58 | ||
d095cd46 | 59 | /* |
57c0c15b | 60 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
61 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
62 | * hypervisor bit set in the MSR, or if we are running on a processor | |
63 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
64 | * then we need to use the FCHV bit to ignore kernel events. | |
65 | */ | |
cdd6c482 | 66 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 67 | |
98fb1807 PM |
68 | /* |
69 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
70 | * and a few other names are different. | |
71 | */ | |
72 | #ifdef CONFIG_PPC32 | |
73 | ||
74 | #define MMCR0_FCHV 0 | |
75 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
76 | ||
77 | #define SPRN_MMCRA SPRN_MMCR2 | |
78 | #define MMCRA_SAMPLE_ENABLE 0 | |
79 | ||
80 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
81 | { | |
82 | return 0; | |
83 | } | |
98fb1807 PM |
84 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
85 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
86 | { | |
87 | return 0; | |
88 | } | |
75382aa7 AB |
89 | static inline void perf_read_regs(struct pt_regs *regs) |
90 | { | |
91 | regs->result = 0; | |
92 | } | |
98fb1807 PM |
93 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
94 | { | |
95 | return 0; | |
96 | } | |
97 | ||
e6878835 | 98 | static inline int siar_valid(struct pt_regs *regs) |
99 | { | |
100 | return 1; | |
101 | } | |
102 | ||
d52f2dc4 MN |
103 | static inline void power_pmu_bhrb_enable(struct perf_event *event) {} |
104 | static inline void power_pmu_bhrb_disable(struct perf_event *event) {} | |
105 | void power_pmu_flush_branch_stack(void) {} | |
106 | static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} | |
98fb1807 PM |
107 | #endif /* CONFIG_PPC32 */ |
108 | ||
33904054 ME |
109 | static bool regs_use_siar(struct pt_regs *regs) |
110 | { | |
111 | return !!(regs->result & 1); | |
112 | } | |
113 | ||
98fb1807 PM |
114 | /* |
115 | * Things that are specific to 64-bit implementations. | |
116 | */ | |
117 | #ifdef CONFIG_PPC64 | |
118 | ||
119 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
120 | { | |
121 | unsigned long mmcra = regs->dsisr; | |
122 | ||
7a786832 | 123 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
124 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
125 | if (slot > 1) | |
126 | return 4 * (slot - 1); | |
127 | } | |
7a786832 | 128 | |
98fb1807 PM |
129 | return 0; |
130 | } | |
131 | ||
98fb1807 PM |
132 | /* |
133 | * The user wants a data address recorded. | |
134 | * If we're not doing instruction sampling, give them the SDAR | |
135 | * (sampled data address). If we are doing instruction sampling, then | |
136 | * only give them the SDAR if it corresponds to the instruction | |
e6878835 | 137 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC or |
138 | * the [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA. | |
98fb1807 PM |
139 | */ |
140 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
141 | { | |
142 | unsigned long mmcra = regs->dsisr; | |
e6878835 | 143 | unsigned long sdsync; |
144 | ||
145 | if (ppmu->flags & PPMU_SIAR_VALID) | |
146 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
147 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
148 | sdsync = POWER6_MMCRA_SDSYNC; | |
149 | else | |
150 | sdsync = MMCRA_SDSYNC; | |
98fb1807 PM |
151 | |
152 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) | |
153 | *addrp = mfspr(SPRN_SDAR); | |
154 | } | |
155 | ||
5682c460 | 156 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
157 | { |
158 | unsigned long sihv = MMCRA_SIHV; | |
159 | ||
8f61aa32 ME |
160 | if (ppmu->flags & PPMU_HAS_SIER) |
161 | return !!(regs->dar & SIER_SIHV); | |
162 | ||
68b30bb9 AB |
163 | if (ppmu->flags & PPMU_ALT_SIPR) |
164 | sihv = POWER6_MMCRA_SIHV; | |
165 | ||
5682c460 | 166 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
167 | } |
168 | ||
5682c460 | 169 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
170 | { |
171 | unsigned long sipr = MMCRA_SIPR; | |
172 | ||
8f61aa32 ME |
173 | if (ppmu->flags & PPMU_HAS_SIER) |
174 | return !!(regs->dar & SIER_SIPR); | |
175 | ||
68b30bb9 AB |
176 | if (ppmu->flags & PPMU_ALT_SIPR) |
177 | sipr = POWER6_MMCRA_SIPR; | |
178 | ||
5682c460 | 179 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
180 | } |
181 | ||
860aad71 ME |
182 | static bool regs_no_sipr(struct pt_regs *regs) |
183 | { | |
184 | return !!(regs->result & 2); | |
185 | } | |
186 | ||
1ce447b9 BH |
187 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
188 | { | |
189 | if (regs->msr & MSR_PR) | |
190 | return PERF_RECORD_MISC_USER; | |
191 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
192 | return PERF_RECORD_MISC_HYPERVISOR; | |
193 | return PERF_RECORD_MISC_KERNEL; | |
194 | } | |
195 | ||
98fb1807 PM |
196 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
197 | { | |
33904054 | 198 | bool use_siar = regs_use_siar(regs); |
98fb1807 | 199 | |
75382aa7 | 200 | if (!use_siar) |
1ce447b9 BH |
201 | return perf_flags_from_msr(regs); |
202 | ||
203 | /* | |
204 | * If we don't have flags in MMCRA, rather than using | |
205 | * the MSR, we intuit the flags from the address in | |
206 | * SIAR which should give slightly more reliable | |
207 | * results | |
208 | */ | |
860aad71 | 209 | if (regs_no_sipr(regs)) { |
1ce447b9 BH |
210 | unsigned long siar = mfspr(SPRN_SIAR); |
211 | if (siar >= PAGE_OFFSET) | |
212 | return PERF_RECORD_MISC_KERNEL; | |
213 | return PERF_RECORD_MISC_USER; | |
214 | } | |
98fb1807 | 215 | |
7abb840b | 216 | /* PR has priority over HV, so order below is important */ |
5682c460 | 217 | if (regs_sipr(regs)) |
7abb840b | 218 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
219 | |
220 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 221 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 222 | |
7abb840b | 223 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
224 | } |
225 | ||
226 | /* | |
227 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
228 | * on each interrupt. | |
8f61aa32 | 229 | * Overload regs->dar to store SIER if we have it. |
75382aa7 AB |
230 | * Overload regs->result to specify whether we should use the MSR (result |
231 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
232 | */ |
233 | static inline void perf_read_regs(struct pt_regs *regs) | |
234 | { | |
75382aa7 AB |
235 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
236 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
237 | int use_siar; | |
238 | ||
5682c460 | 239 | regs->dsisr = mmcra; |
860aad71 ME |
240 | regs->result = 0; |
241 | ||
242 | if (ppmu->flags & PPMU_NO_SIPR) | |
243 | regs->result |= 2; | |
5682c460 | 244 | |
8f61aa32 ME |
245 | /* |
246 | * On power8 if we're in random sampling mode, the SIER is updated. | |
247 | * If we're in continuous sampling mode, we don't have SIPR. | |
248 | */ | |
249 | if (ppmu->flags & PPMU_HAS_SIER) { | |
250 | if (marked) | |
251 | regs->dar = mfspr(SPRN_SIER); | |
252 | else | |
253 | regs->result |= 2; | |
254 | } | |
255 | ||
256 | ||
5c093efa AB |
257 | /* |
258 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
259 | * not valid. Use pt_regs. | |
260 | * | |
261 | * If it is a marked event use the SIAR. | |
262 | * | |
263 | * If the PMU doesn't update the SIAR for non marked events use | |
264 | * pt_regs. | |
265 | * | |
266 | * If the PMU has HV/PR flags then check to see if they | |
267 | * place the exception in userspace. If so, use pt_regs. In | |
268 | * continuous sampling mode the SIAR and the PMU exception are | |
269 | * not synchronised, so they may be many instructions apart. | |
270 | * This can result in confusing backtraces. We still want | |
271 | * hypervisor samples as well as samples in the kernel with | |
272 | * interrupts off hence the userspace check. | |
273 | */ | |
75382aa7 AB |
274 | if (TRAP(regs) != 0xf00) |
275 | use_siar = 0; | |
5c093efa AB |
276 | else if (marked) |
277 | use_siar = 1; | |
278 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
279 | use_siar = 0; | |
860aad71 | 280 | else if (!regs_no_sipr(regs) && regs_sipr(regs)) |
75382aa7 AB |
281 | use_siar = 0; |
282 | else | |
283 | use_siar = 1; | |
284 | ||
860aad71 | 285 | regs->result |= use_siar; |
98fb1807 PM |
286 | } |
287 | ||
288 | /* | |
289 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
290 | * it as an NMI. | |
291 | */ | |
292 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
293 | { | |
294 | return !regs->softe; | |
295 | } | |
296 | ||
e6878835 | 297 | /* |
298 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
299 | * must be sampled only if the SIAR-valid bit is set. | |
300 | * | |
301 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
302 | * bit, assume that SIAR is valid. | |
303 | */ | |
304 | static inline int siar_valid(struct pt_regs *regs) | |
305 | { | |
306 | unsigned long mmcra = regs->dsisr; | |
307 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
308 | ||
309 | if ((ppmu->flags & PPMU_SIAR_VALID) && marked) | |
310 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
311 | ||
312 | return 1; | |
313 | } | |
314 | ||
d52f2dc4 MN |
315 | |
316 | /* Reset all possible BHRB entries */ | |
317 | static void power_pmu_bhrb_reset(void) | |
318 | { | |
319 | asm volatile(PPC_CLRBHRB); | |
320 | } | |
321 | ||
322 | static void power_pmu_bhrb_enable(struct perf_event *event) | |
323 | { | |
324 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
325 | ||
326 | if (!ppmu->bhrb_nr) | |
327 | return; | |
328 | ||
329 | /* Clear BHRB if we changed task context to avoid data leaks */ | |
330 | if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { | |
331 | power_pmu_bhrb_reset(); | |
332 | cpuhw->bhrb_context = event->ctx; | |
333 | } | |
334 | cpuhw->bhrb_users++; | |
335 | } | |
336 | ||
337 | static void power_pmu_bhrb_disable(struct perf_event *event) | |
338 | { | |
339 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
340 | ||
341 | if (!ppmu->bhrb_nr) | |
342 | return; | |
343 | ||
344 | cpuhw->bhrb_users--; | |
345 | WARN_ON_ONCE(cpuhw->bhrb_users < 0); | |
346 | ||
347 | if (!cpuhw->disabled && !cpuhw->bhrb_users) { | |
348 | /* BHRB cannot be turned off when other | |
349 | * events are active on the PMU. | |
350 | */ | |
351 | ||
352 | /* avoid stale pointer */ | |
353 | cpuhw->bhrb_context = NULL; | |
354 | } | |
355 | } | |
356 | ||
357 | /* Called from ctxsw to prevent one process's branch entries to | |
358 | * mingle with the other process's entries during context switch. | |
359 | */ | |
360 | void power_pmu_flush_branch_stack(void) | |
361 | { | |
362 | if (ppmu->bhrb_nr) | |
363 | power_pmu_bhrb_reset(); | |
364 | } | |
365 | ||
366 | ||
367 | /* Processing BHRB entries */ | |
368 | static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) | |
369 | { | |
370 | u64 val; | |
371 | u64 addr; | |
372 | int r_index, u_index, target, pred; | |
373 | ||
374 | r_index = 0; | |
375 | u_index = 0; | |
376 | while (r_index < ppmu->bhrb_nr) { | |
377 | /* Assembly read function */ | |
378 | val = read_bhrb(r_index); | |
379 | ||
380 | /* Terminal marker: End of valid BHRB entries */ | |
381 | if (val == 0) { | |
382 | break; | |
383 | } else { | |
384 | /* BHRB field break up */ | |
385 | addr = val & BHRB_EA; | |
386 | pred = val & BHRB_PREDICTION; | |
387 | target = val & BHRB_TARGET; | |
388 | ||
389 | /* Probable Missed entry: Not applicable for POWER8 */ | |
390 | if ((addr == 0) && (target == 0) && (pred == 1)) { | |
391 | r_index++; | |
392 | continue; | |
393 | } | |
394 | ||
395 | /* Real Missed entry: Power8 based missed entry */ | |
396 | if ((addr == 0) && (target == 1) && (pred == 1)) { | |
397 | r_index++; | |
398 | continue; | |
399 | } | |
400 | ||
401 | /* Reserved condition: Not a valid entry */ | |
402 | if ((addr == 0) && (target == 1) && (pred == 0)) { | |
403 | r_index++; | |
404 | continue; | |
405 | } | |
406 | ||
407 | /* Is a target address */ | |
408 | if (val & BHRB_TARGET) { | |
409 | /* First address cannot be a target address */ | |
410 | if (r_index == 0) { | |
411 | r_index++; | |
412 | continue; | |
413 | } | |
414 | ||
415 | /* Update target address for the previous entry */ | |
416 | cpuhw->bhrb_entries[u_index - 1].to = addr; | |
417 | cpuhw->bhrb_entries[u_index - 1].mispred = pred; | |
418 | cpuhw->bhrb_entries[u_index - 1].predicted = ~pred; | |
419 | ||
420 | /* Dont increment u_index */ | |
421 | r_index++; | |
422 | } else { | |
423 | /* Update address, flags for current entry */ | |
424 | cpuhw->bhrb_entries[u_index].from = addr; | |
425 | cpuhw->bhrb_entries[u_index].mispred = pred; | |
426 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
427 | ||
428 | /* Successfully popullated one entry */ | |
429 | u_index++; | |
430 | r_index++; | |
431 | } | |
432 | } | |
433 | } | |
434 | cpuhw->bhrb_stack.nr = u_index; | |
435 | return; | |
436 | } | |
437 | ||
98fb1807 PM |
438 | #endif /* CONFIG_PPC64 */ |
439 | ||
cdd6c482 | 440 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 441 | |
cdd6c482 | 442 | void perf_event_print_debug(void) |
4574910e PM |
443 | { |
444 | } | |
445 | ||
4574910e | 446 | /* |
57c0c15b | 447 | * Read one performance monitor counter (PMC). |
4574910e PM |
448 | */ |
449 | static unsigned long read_pmc(int idx) | |
450 | { | |
451 | unsigned long val; | |
452 | ||
453 | switch (idx) { | |
454 | case 1: | |
455 | val = mfspr(SPRN_PMC1); | |
456 | break; | |
457 | case 2: | |
458 | val = mfspr(SPRN_PMC2); | |
459 | break; | |
460 | case 3: | |
461 | val = mfspr(SPRN_PMC3); | |
462 | break; | |
463 | case 4: | |
464 | val = mfspr(SPRN_PMC4); | |
465 | break; | |
466 | case 5: | |
467 | val = mfspr(SPRN_PMC5); | |
468 | break; | |
469 | case 6: | |
470 | val = mfspr(SPRN_PMC6); | |
471 | break; | |
98fb1807 | 472 | #ifdef CONFIG_PPC64 |
4574910e PM |
473 | case 7: |
474 | val = mfspr(SPRN_PMC7); | |
475 | break; | |
476 | case 8: | |
477 | val = mfspr(SPRN_PMC8); | |
478 | break; | |
98fb1807 | 479 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
480 | default: |
481 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
482 | val = 0; | |
483 | } | |
484 | return val; | |
485 | } | |
486 | ||
487 | /* | |
488 | * Write one PMC. | |
489 | */ | |
490 | static void write_pmc(int idx, unsigned long val) | |
491 | { | |
492 | switch (idx) { | |
493 | case 1: | |
494 | mtspr(SPRN_PMC1, val); | |
495 | break; | |
496 | case 2: | |
497 | mtspr(SPRN_PMC2, val); | |
498 | break; | |
499 | case 3: | |
500 | mtspr(SPRN_PMC3, val); | |
501 | break; | |
502 | case 4: | |
503 | mtspr(SPRN_PMC4, val); | |
504 | break; | |
505 | case 5: | |
506 | mtspr(SPRN_PMC5, val); | |
507 | break; | |
508 | case 6: | |
509 | mtspr(SPRN_PMC6, val); | |
510 | break; | |
98fb1807 | 511 | #ifdef CONFIG_PPC64 |
4574910e PM |
512 | case 7: |
513 | mtspr(SPRN_PMC7, val); | |
514 | break; | |
515 | case 8: | |
516 | mtspr(SPRN_PMC8, val); | |
517 | break; | |
98fb1807 | 518 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
519 | default: |
520 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
521 | } | |
522 | } | |
523 | ||
524 | /* | |
525 | * Check if a set of events can all go on the PMU at once. | |
526 | * If they can't, this will look at alternative codes for the events | |
527 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 528 | * The feasible set is returned in event_id[]. |
4574910e | 529 | */ |
cdd6c482 IM |
530 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
531 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 532 | int n_ev) |
4574910e | 533 | { |
448d64f8 | 534 | unsigned long mask, value, nv; |
cdd6c482 IM |
535 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
536 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 537 | int i, j; |
448d64f8 PM |
538 | unsigned long addf = ppmu->add_fields; |
539 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 540 | |
a8f90e90 | 541 | if (n_ev > ppmu->n_counter) |
4574910e PM |
542 | return -1; |
543 | ||
544 | /* First see if the events will go on as-is */ | |
545 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 546 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
547 | && !ppmu->limited_pmc_event(event_id[i])) { |
548 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 549 | cpuhw->alternatives[i]); |
cdd6c482 | 550 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 551 | } |
cdd6c482 | 552 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 553 | &cpuhw->avalues[i][0])) |
4574910e | 554 | return -1; |
4574910e PM |
555 | } |
556 | value = mask = 0; | |
557 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
558 | nv = (value | cpuhw->avalues[i][0]) + |
559 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 560 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
561 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
562 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
563 | break; |
564 | value = nv; | |
e51ee31e | 565 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
566 | } |
567 | if (i == n_ev) | |
568 | return 0; /* all OK */ | |
569 | ||
570 | /* doesn't work, gather alternatives... */ | |
571 | if (!ppmu->get_alternatives) | |
572 | return -1; | |
573 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 574 | choice[i] = 0; |
cdd6c482 | 575 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 576 | cpuhw->alternatives[i]); |
4574910e | 577 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
578 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
579 | &cpuhw->amasks[i][j], | |
580 | &cpuhw->avalues[i][j]); | |
4574910e PM |
581 | } |
582 | ||
583 | /* enumerate all possibilities and see if any will work */ | |
584 | i = 0; | |
585 | j = -1; | |
586 | value = mask = nv = 0; | |
587 | while (i < n_ev) { | |
588 | if (j >= 0) { | |
589 | /* we're backtracking, restore context */ | |
590 | value = svalues[i]; | |
591 | mask = smasks[i]; | |
592 | j = choice[i]; | |
593 | } | |
594 | /* | |
cdd6c482 | 595 | * See if any alternative k for event_id i, |
4574910e PM |
596 | * where k > j, will satisfy the constraints. |
597 | */ | |
598 | while (++j < n_alt[i]) { | |
e51ee31e PM |
599 | nv = (value | cpuhw->avalues[i][j]) + |
600 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 601 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
602 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
603 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
604 | break; |
605 | } | |
606 | if (j >= n_alt[i]) { | |
607 | /* | |
608 | * No feasible alternative, backtrack | |
cdd6c482 | 609 | * to event_id i-1 and continue enumerating its |
4574910e PM |
610 | * alternatives from where we got up to. |
611 | */ | |
612 | if (--i < 0) | |
613 | return -1; | |
614 | } else { | |
615 | /* | |
cdd6c482 IM |
616 | * Found a feasible alternative for event_id i, |
617 | * remember where we got up to with this event_id, | |
618 | * go on to the next event_id, and start with | |
4574910e PM |
619 | * the first alternative for it. |
620 | */ | |
621 | choice[i] = j; | |
622 | svalues[i] = value; | |
623 | smasks[i] = mask; | |
624 | value = nv; | |
e51ee31e | 625 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
626 | ++i; |
627 | j = -1; | |
628 | } | |
629 | } | |
630 | ||
631 | /* OK, we have a feasible combination, tell the caller the solution */ | |
632 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 633 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
634 | return 0; |
635 | } | |
636 | ||
0475f9ea | 637 | /* |
cdd6c482 | 638 | * Check if newly-added events have consistent settings for |
0475f9ea | 639 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 640 | * added events. |
0475f9ea | 641 | */ |
cdd6c482 | 642 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 643 | int n_prev, int n_new) |
0475f9ea | 644 | { |
ab7ef2e5 PM |
645 | int eu = 0, ek = 0, eh = 0; |
646 | int i, n, first; | |
cdd6c482 | 647 | struct perf_event *event; |
0475f9ea PM |
648 | |
649 | n = n_prev + n_new; | |
650 | if (n <= 1) | |
651 | return 0; | |
652 | ||
ab7ef2e5 PM |
653 | first = 1; |
654 | for (i = 0; i < n; ++i) { | |
655 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
656 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
657 | continue; | |
658 | } | |
cdd6c482 | 659 | event = ctrs[i]; |
ab7ef2e5 | 660 | if (first) { |
cdd6c482 IM |
661 | eu = event->attr.exclude_user; |
662 | ek = event->attr.exclude_kernel; | |
663 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 664 | first = 0; |
cdd6c482 IM |
665 | } else if (event->attr.exclude_user != eu || |
666 | event->attr.exclude_kernel != ek || | |
667 | event->attr.exclude_hv != eh) { | |
0475f9ea | 668 | return -EAGAIN; |
ab7ef2e5 | 669 | } |
0475f9ea | 670 | } |
ab7ef2e5 PM |
671 | |
672 | if (eu || ek || eh) | |
673 | for (i = 0; i < n; ++i) | |
674 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
675 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
676 | ||
0475f9ea PM |
677 | return 0; |
678 | } | |
679 | ||
86c74ab3 EM |
680 | static u64 check_and_compute_delta(u64 prev, u64 val) |
681 | { | |
682 | u64 delta = (val - prev) & 0xfffffffful; | |
683 | ||
684 | /* | |
685 | * POWER7 can roll back counter values, if the new value is smaller | |
686 | * than the previous value it will cause the delta and the counter to | |
687 | * have bogus values unless we rolled a counter over. If a coutner is | |
688 | * rolled back, it will be smaller, but within 256, which is the maximum | |
689 | * number of events to rollback at once. If we dectect a rollback | |
690 | * return 0. This can lead to a small lack of precision in the | |
691 | * counters. | |
692 | */ | |
693 | if (prev > val && (prev - val) < 256) | |
694 | delta = 0; | |
695 | ||
696 | return delta; | |
697 | } | |
698 | ||
cdd6c482 | 699 | static void power_pmu_read(struct perf_event *event) |
4574910e | 700 | { |
98fb1807 | 701 | s64 val, delta, prev; |
4574910e | 702 | |
a4eaf7f1 PZ |
703 | if (event->hw.state & PERF_HES_STOPPED) |
704 | return; | |
705 | ||
cdd6c482 | 706 | if (!event->hw.idx) |
4574910e PM |
707 | return; |
708 | /* | |
709 | * Performance monitor interrupts come even when interrupts | |
710 | * are soft-disabled, as long as interrupts are hard-enabled. | |
711 | * Therefore we treat them like NMIs. | |
712 | */ | |
713 | do { | |
e7850595 | 714 | prev = local64_read(&event->hw.prev_count); |
4574910e | 715 | barrier(); |
cdd6c482 | 716 | val = read_pmc(event->hw.idx); |
86c74ab3 EM |
717 | delta = check_and_compute_delta(prev, val); |
718 | if (!delta) | |
719 | return; | |
e7850595 | 720 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 721 | |
e7850595 PZ |
722 | local64_add(delta, &event->count); |
723 | local64_sub(delta, &event->hw.period_left); | |
4574910e PM |
724 | } |
725 | ||
ab7ef2e5 PM |
726 | /* |
727 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
728 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 729 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
730 | */ |
731 | static int is_limited_pmc(int pmcnum) | |
732 | { | |
0bbd0d4b PM |
733 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
734 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
735 | } |
736 | ||
a8f90e90 | 737 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
738 | unsigned long pmc5, unsigned long pmc6) |
739 | { | |
cdd6c482 | 740 | struct perf_event *event; |
ab7ef2e5 PM |
741 | u64 val, prev, delta; |
742 | int i; | |
743 | ||
744 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 745 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 746 | if (!event->hw.idx) |
ab7ef2e5 | 747 | continue; |
cdd6c482 | 748 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 749 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 750 | event->hw.idx = 0; |
86c74ab3 EM |
751 | delta = check_and_compute_delta(prev, val); |
752 | if (delta) | |
753 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
754 | } |
755 | } | |
756 | ||
a8f90e90 | 757 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
758 | unsigned long pmc5, unsigned long pmc6) |
759 | { | |
cdd6c482 | 760 | struct perf_event *event; |
86c74ab3 | 761 | u64 val, prev; |
ab7ef2e5 PM |
762 | int i; |
763 | ||
764 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 765 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
766 | event->hw.idx = cpuhw->limited_hwidx[i]; |
767 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
768 | prev = local64_read(&event->hw.prev_count); |
769 | if (check_and_compute_delta(prev, val)) | |
770 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 771 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
772 | } |
773 | } | |
774 | ||
775 | /* | |
cdd6c482 | 776 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 777 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
778 | * other events. We try to keep the values from the limited |
779 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 780 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
781 | * the limited events as small and consistent as possible. |
782 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
783 | * both, and always in the same order, to minimize variability, |
784 | * and do it inside the same asm that writes MMCR0. | |
785 | */ | |
cdd6c482 | 786 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
787 | { |
788 | unsigned long pmc5, pmc6; | |
789 | ||
790 | if (!cpuhw->n_limited) { | |
791 | mtspr(SPRN_MMCR0, mmcr0); | |
792 | return; | |
793 | } | |
794 | ||
795 | /* | |
796 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
797 | * To ensure we don't get a performance monitor interrupt |
798 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 799 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 800 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
801 | */ |
802 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
803 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
804 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
805 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
806 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
807 | ||
808 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 809 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 810 | else |
a8f90e90 | 811 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
812 | |
813 | /* | |
cdd6c482 | 814 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
815 | * enable bits, if necessary. |
816 | */ | |
817 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
818 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
819 | } |
820 | ||
4574910e | 821 | /* |
cdd6c482 IM |
822 | * Disable all events to prevent PMU interrupts and to allow |
823 | * events to be added or removed. | |
4574910e | 824 | */ |
a4eaf7f1 | 825 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 826 | { |
cdd6c482 | 827 | struct cpu_hw_events *cpuhw; |
4574910e PM |
828 | unsigned long flags; |
829 | ||
f36a1a13 PM |
830 | if (!ppmu) |
831 | return; | |
4574910e | 832 | local_irq_save(flags); |
cdd6c482 | 833 | cpuhw = &__get_cpu_var(cpu_hw_events); |
4574910e | 834 | |
448d64f8 | 835 | if (!cpuhw->disabled) { |
4574910e PM |
836 | cpuhw->disabled = 1; |
837 | cpuhw->n_added = 0; | |
838 | ||
01d0287f PM |
839 | /* |
840 | * Check if we ever enabled the PMU on this cpu. | |
841 | */ | |
842 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 843 | ppc_enable_pmcs(); |
01d0287f PM |
844 | cpuhw->pmcs_enabled = 1; |
845 | } | |
846 | ||
f708223d PM |
847 | /* |
848 | * Disable instruction sampling if it was enabled | |
849 | */ | |
850 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
851 | mtspr(SPRN_MMCRA, | |
852 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
853 | mb(); | |
854 | } | |
855 | ||
4574910e | 856 | /* |
57c0c15b | 857 | * Set the 'freeze counters' bit. |
4574910e | 858 | * The barrier is to make sure the mtspr has been |
cdd6c482 | 859 | * executed and the PMU has frozen the events |
4574910e PM |
860 | * before we return. |
861 | */ | |
ab7ef2e5 | 862 | write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); |
4574910e PM |
863 | mb(); |
864 | } | |
865 | local_irq_restore(flags); | |
4574910e PM |
866 | } |
867 | ||
868 | /* | |
cdd6c482 IM |
869 | * Re-enable all events if disable == 0. |
870 | * If we were previously disabled and events were added, then | |
4574910e PM |
871 | * put the new config on the PMU. |
872 | */ | |
a4eaf7f1 | 873 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 874 | { |
cdd6c482 IM |
875 | struct perf_event *event; |
876 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
877 | unsigned long flags; |
878 | long i; | |
879 | unsigned long val; | |
880 | s64 left; | |
cdd6c482 | 881 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
882 | int n_lim; |
883 | int idx; | |
4574910e | 884 | |
f36a1a13 PM |
885 | if (!ppmu) |
886 | return; | |
4574910e | 887 | local_irq_save(flags); |
cdd6c482 | 888 | cpuhw = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
889 | if (!cpuhw->disabled) { |
890 | local_irq_restore(flags); | |
891 | return; | |
892 | } | |
4574910e PM |
893 | cpuhw->disabled = 0; |
894 | ||
895 | /* | |
cdd6c482 | 896 | * If we didn't change anything, or only removed events, |
4574910e PM |
897 | * no need to recalculate MMCR* settings and reset the PMCs. |
898 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 899 | * (possibly updated for removal of events). |
4574910e PM |
900 | */ |
901 | if (!cpuhw->n_added) { | |
f708223d | 902 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 903 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
cdd6c482 | 904 | if (cpuhw->n_events == 0) |
a6dbf93a | 905 | ppc_set_pmu_inuse(0); |
f708223d | 906 | goto out_enable; |
4574910e PM |
907 | } |
908 | ||
909 | /* | |
cdd6c482 | 910 | * Compute MMCR* values for the new set of events |
4574910e | 911 | */ |
cdd6c482 | 912 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
4574910e PM |
913 | cpuhw->mmcr)) { |
914 | /* shouldn't ever get here */ | |
915 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
916 | goto out; | |
917 | } | |
918 | ||
0475f9ea PM |
919 | /* |
920 | * Add in MMCR0 freeze bits corresponding to the | |
cdd6c482 IM |
921 | * attr.exclude_* bits for the first event. |
922 | * We have already checked that all events have the | |
923 | * same values for these bits as the first event. | |
0475f9ea | 924 | */ |
cdd6c482 IM |
925 | event = cpuhw->event[0]; |
926 | if (event->attr.exclude_user) | |
0475f9ea | 927 | cpuhw->mmcr[0] |= MMCR0_FCP; |
cdd6c482 IM |
928 | if (event->attr.exclude_kernel) |
929 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
930 | if (event->attr.exclude_hv) | |
0475f9ea PM |
931 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
932 | ||
4574910e PM |
933 | /* |
934 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
935 | * bit set and set the hardware events to their initial values. |
936 | * Then unfreeze the events. | |
4574910e | 937 | */ |
a6dbf93a | 938 | ppc_set_pmu_inuse(1); |
f708223d | 939 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
940 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
941 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
942 | | MMCR0_FC); | |
943 | ||
944 | /* | |
cdd6c482 | 945 | * Read off any pre-existing events that need to move |
4574910e PM |
946 | * to another PMC. |
947 | */ | |
cdd6c482 IM |
948 | for (i = 0; i < cpuhw->n_events; ++i) { |
949 | event = cpuhw->event[i]; | |
950 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
951 | power_pmu_read(event); | |
952 | write_pmc(event->hw.idx, 0); | |
953 | event->hw.idx = 0; | |
4574910e PM |
954 | } |
955 | } | |
956 | ||
957 | /* | |
cdd6c482 | 958 | * Initialize the PMCs for all the new and moved events. |
4574910e | 959 | */ |
ab7ef2e5 | 960 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
961 | for (i = 0; i < cpuhw->n_events; ++i) { |
962 | event = cpuhw->event[i]; | |
963 | if (event->hw.idx) | |
4574910e | 964 | continue; |
ab7ef2e5 PM |
965 | idx = hwc_index[i] + 1; |
966 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 967 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
968 | cpuhw->limited_hwidx[n_lim] = idx; |
969 | ++n_lim; | |
970 | continue; | |
971 | } | |
4574910e | 972 | val = 0; |
cdd6c482 | 973 | if (event->hw.sample_period) { |
e7850595 | 974 | left = local64_read(&event->hw.period_left); |
4574910e PM |
975 | if (left < 0x80000000L) |
976 | val = 0x80000000L - left; | |
977 | } | |
e7850595 | 978 | local64_set(&event->hw.prev_count, val); |
cdd6c482 | 979 | event->hw.idx = idx; |
a4eaf7f1 PZ |
980 | if (event->hw.state & PERF_HES_STOPPED) |
981 | val = 0; | |
ab7ef2e5 | 982 | write_pmc(idx, val); |
cdd6c482 | 983 | perf_event_update_userpage(event); |
4574910e | 984 | } |
ab7ef2e5 | 985 | cpuhw->n_limited = n_lim; |
4574910e | 986 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
987 | |
988 | out_enable: | |
989 | mb(); | |
ab7ef2e5 | 990 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 991 | |
f708223d PM |
992 | /* |
993 | * Enable instruction sampling if necessary | |
994 | */ | |
995 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
996 | mb(); | |
997 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
998 | } | |
999 | ||
4574910e | 1000 | out: |
3925f46b AK |
1001 | if (cpuhw->bhrb_users) |
1002 | ppmu->config_bhrb(cpuhw->bhrb_filter); | |
1003 | ||
4574910e PM |
1004 | local_irq_restore(flags); |
1005 | } | |
1006 | ||
cdd6c482 IM |
1007 | static int collect_events(struct perf_event *group, int max_count, |
1008 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 1009 | unsigned int *flags) |
4574910e PM |
1010 | { |
1011 | int n = 0; | |
cdd6c482 | 1012 | struct perf_event *event; |
4574910e | 1013 | |
cdd6c482 | 1014 | if (!is_software_event(group)) { |
4574910e PM |
1015 | if (n >= max_count) |
1016 | return -1; | |
1017 | ctrs[n] = group; | |
cdd6c482 | 1018 | flags[n] = group->hw.event_base; |
4574910e PM |
1019 | events[n++] = group->hw.config; |
1020 | } | |
a8f90e90 | 1021 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
1022 | if (!is_software_event(event) && |
1023 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
1024 | if (n >= max_count) |
1025 | return -1; | |
cdd6c482 IM |
1026 | ctrs[n] = event; |
1027 | flags[n] = event->hw.event_base; | |
1028 | events[n++] = event->hw.config; | |
4574910e PM |
1029 | } |
1030 | } | |
1031 | return n; | |
1032 | } | |
1033 | ||
4574910e | 1034 | /* |
cdd6c482 IM |
1035 | * Add a event to the PMU. |
1036 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 1037 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
1038 | * actual work of reconfiguring the PMU. |
1039 | */ | |
a4eaf7f1 | 1040 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 1041 | { |
cdd6c482 | 1042 | struct cpu_hw_events *cpuhw; |
4574910e | 1043 | unsigned long flags; |
4574910e PM |
1044 | int n0; |
1045 | int ret = -EAGAIN; | |
1046 | ||
1047 | local_irq_save(flags); | |
33696fc0 | 1048 | perf_pmu_disable(event->pmu); |
4574910e PM |
1049 | |
1050 | /* | |
cdd6c482 | 1051 | * Add the event to the list (if there is room) |
4574910e PM |
1052 | * and check whether the total set is still feasible. |
1053 | */ | |
cdd6c482 IM |
1054 | cpuhw = &__get_cpu_var(cpu_hw_events); |
1055 | n0 = cpuhw->n_events; | |
a8f90e90 | 1056 | if (n0 >= ppmu->n_counter) |
4574910e | 1057 | goto out; |
cdd6c482 IM |
1058 | cpuhw->event[n0] = event; |
1059 | cpuhw->events[n0] = event->hw.config; | |
1060 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 1061 | |
f53d168c | 1062 | /* |
1063 | * This event may have been disabled/stopped in record_and_restart() | |
1064 | * because we exceeded the ->event_limit. If re-starting the event, | |
1065 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
1066 | * notification is re-enabled. | |
1067 | */ | |
a4eaf7f1 PZ |
1068 | if (!(ef_flags & PERF_EF_START)) |
1069 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 1070 | else |
1071 | event->hw.state = 0; | |
a4eaf7f1 | 1072 | |
8e6d5573 LM |
1073 | /* |
1074 | * If group events scheduling transaction was started, | |
25985edc | 1075 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
1076 | * at commit time(->commit_txn) as a whole |
1077 | */ | |
8d2cacbb | 1078 | if (cpuhw->group_flag & PERF_EVENT_TXN) |
8e6d5573 LM |
1079 | goto nocheck; |
1080 | ||
cdd6c482 | 1081 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 1082 | goto out; |
e51ee31e | 1083 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 1084 | goto out; |
cdd6c482 | 1085 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
1086 | |
1087 | nocheck: | |
cdd6c482 | 1088 | ++cpuhw->n_events; |
4574910e PM |
1089 | ++cpuhw->n_added; |
1090 | ||
1091 | ret = 0; | |
1092 | out: | |
3925f46b AK |
1093 | if (has_branch_stack(event)) |
1094 | power_pmu_bhrb_enable(event); | |
1095 | ||
33696fc0 | 1096 | perf_pmu_enable(event->pmu); |
4574910e PM |
1097 | local_irq_restore(flags); |
1098 | return ret; | |
1099 | } | |
1100 | ||
1101 | /* | |
cdd6c482 | 1102 | * Remove a event from the PMU. |
4574910e | 1103 | */ |
a4eaf7f1 | 1104 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 1105 | { |
cdd6c482 | 1106 | struct cpu_hw_events *cpuhw; |
4574910e | 1107 | long i; |
4574910e PM |
1108 | unsigned long flags; |
1109 | ||
1110 | local_irq_save(flags); | |
33696fc0 | 1111 | perf_pmu_disable(event->pmu); |
4574910e | 1112 | |
cdd6c482 IM |
1113 | power_pmu_read(event); |
1114 | ||
1115 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1116 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1117 | if (event == cpuhw->event[i]) { | |
219a92a4 | 1118 | while (++i < cpuhw->n_events) { |
cdd6c482 | 1119 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
1120 | cpuhw->events[i-1] = cpuhw->events[i]; |
1121 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
1122 | } | |
cdd6c482 IM |
1123 | --cpuhw->n_events; |
1124 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
1125 | if (event->hw.idx) { | |
1126 | write_pmc(event->hw.idx, 0); | |
1127 | event->hw.idx = 0; | |
ab7ef2e5 | 1128 | } |
cdd6c482 | 1129 | perf_event_update_userpage(event); |
4574910e PM |
1130 | break; |
1131 | } | |
1132 | } | |
ab7ef2e5 | 1133 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 1134 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
1135 | break; |
1136 | if (i < cpuhw->n_limited) { | |
1137 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 1138 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
1139 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
1140 | } | |
1141 | --cpuhw->n_limited; | |
1142 | } | |
cdd6c482 IM |
1143 | if (cpuhw->n_events == 0) { |
1144 | /* disable exceptions if no events are running */ | |
4574910e PM |
1145 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
1146 | } | |
1147 | ||
3925f46b AK |
1148 | if (has_branch_stack(event)) |
1149 | power_pmu_bhrb_disable(event); | |
1150 | ||
33696fc0 | 1151 | perf_pmu_enable(event->pmu); |
4574910e PM |
1152 | local_irq_restore(flags); |
1153 | } | |
1154 | ||
8a7b8cb9 | 1155 | /* |
a4eaf7f1 PZ |
1156 | * POWER-PMU does not support disabling individual counters, hence |
1157 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 1158 | */ |
a4eaf7f1 PZ |
1159 | |
1160 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 1161 | { |
8a7b8cb9 | 1162 | unsigned long flags; |
a4eaf7f1 | 1163 | s64 left; |
9a45a940 | 1164 | unsigned long val; |
8a7b8cb9 | 1165 | |
cdd6c482 | 1166 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 1167 | return; |
a4eaf7f1 PZ |
1168 | |
1169 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
1170 | return; | |
1171 | ||
1172 | if (ef_flags & PERF_EF_RELOAD) | |
1173 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1174 | ||
1175 | local_irq_save(flags); | |
1176 | perf_pmu_disable(event->pmu); | |
1177 | ||
1178 | event->hw.state = 0; | |
1179 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
1180 | |
1181 | val = 0; | |
1182 | if (left < 0x80000000L) | |
1183 | val = 0x80000000L - left; | |
1184 | ||
1185 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1186 | |
1187 | perf_event_update_userpage(event); | |
1188 | perf_pmu_enable(event->pmu); | |
1189 | local_irq_restore(flags); | |
1190 | } | |
1191 | ||
1192 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1193 | { | |
1194 | unsigned long flags; | |
1195 | ||
1196 | if (!event->hw.idx || !event->hw.sample_period) | |
1197 | return; | |
1198 | ||
1199 | if (event->hw.state & PERF_HES_STOPPED) | |
1200 | return; | |
1201 | ||
8a7b8cb9 | 1202 | local_irq_save(flags); |
33696fc0 | 1203 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1204 | |
cdd6c482 | 1205 | power_pmu_read(event); |
a4eaf7f1 PZ |
1206 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1207 | write_pmc(event->hw.idx, 0); | |
1208 | ||
cdd6c482 | 1209 | perf_event_update_userpage(event); |
33696fc0 | 1210 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1211 | local_irq_restore(flags); |
1212 | } | |
1213 | ||
8e6d5573 LM |
1214 | /* |
1215 | * Start group events scheduling transaction | |
1216 | * Set the flag to make pmu::enable() not perform the | |
1217 | * schedulability test, it will be performed at commit time | |
1218 | */ | |
51b0fe39 | 1219 | void power_pmu_start_txn(struct pmu *pmu) |
8e6d5573 LM |
1220 | { |
1221 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1222 | ||
33696fc0 | 1223 | perf_pmu_disable(pmu); |
8d2cacbb | 1224 | cpuhw->group_flag |= PERF_EVENT_TXN; |
8e6d5573 LM |
1225 | cpuhw->n_txn_start = cpuhw->n_events; |
1226 | } | |
1227 | ||
1228 | /* | |
1229 | * Stop group events scheduling transaction | |
1230 | * Clear the flag and pmu::enable() will perform the | |
1231 | * schedulability test. | |
1232 | */ | |
51b0fe39 | 1233 | void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 LM |
1234 | { |
1235 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1236 | ||
8d2cacbb | 1237 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1238 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1239 | } |
1240 | ||
1241 | /* | |
1242 | * Commit group events scheduling transaction | |
1243 | * Perform the group schedulability test as a whole | |
1244 | * Return 0 if success | |
1245 | */ | |
51b0fe39 | 1246 | int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1247 | { |
1248 | struct cpu_hw_events *cpuhw; | |
1249 | long i, n; | |
1250 | ||
1251 | if (!ppmu) | |
1252 | return -EAGAIN; | |
1253 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1254 | n = cpuhw->n_events; | |
1255 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1256 | return -EAGAIN; | |
1257 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1258 | if (i < 0) | |
1259 | return -EAGAIN; | |
1260 | ||
1261 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1262 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1263 | ||
8d2cacbb | 1264 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1265 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1266 | return 0; |
1267 | } | |
1268 | ||
ab7ef2e5 | 1269 | /* |
cdd6c482 | 1270 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1271 | * or 0 if not. |
cdd6c482 | 1272 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1273 | * that a limited PMC can count, doesn't require interrupts, and |
1274 | * doesn't exclude any processor mode. | |
1275 | */ | |
cdd6c482 | 1276 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1277 | unsigned int flags) |
1278 | { | |
1279 | int n; | |
ef923214 | 1280 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1281 | |
cdd6c482 IM |
1282 | if (event->attr.exclude_user |
1283 | || event->attr.exclude_kernel | |
1284 | || event->attr.exclude_hv | |
1285 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1286 | return 0; |
1287 | ||
1288 | if (ppmu->limited_pmc_event(ev)) | |
1289 | return 1; | |
1290 | ||
1291 | /* | |
cdd6c482 | 1292 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1293 | * see if any alternative code goes on a limited PMC. |
1294 | */ | |
1295 | if (!ppmu->get_alternatives) | |
1296 | return 0; | |
1297 | ||
1298 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1299 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1300 | |
ef923214 | 1301 | return n > 0; |
ab7ef2e5 PM |
1302 | } |
1303 | ||
1304 | /* | |
cdd6c482 IM |
1305 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1306 | * and return the event_id code, or 0 if there is no such alternative. | |
1307 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1308 | */ |
ef923214 | 1309 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1310 | { |
ef923214 | 1311 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1312 | int n; |
1313 | ||
1314 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1315 | n = ppmu->get_alternatives(ev, flags, alt); | |
1316 | if (!n) | |
1317 | return 0; | |
1318 | return alt[0]; | |
1319 | } | |
1320 | ||
cdd6c482 IM |
1321 | /* Number of perf_events counting hardware events */ |
1322 | static atomic_t num_events; | |
7595d63b PM |
1323 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1324 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1325 | ||
1326 | /* | |
cdd6c482 | 1327 | * Release the PMU if this is the last perf_event. |
7595d63b | 1328 | */ |
cdd6c482 | 1329 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1330 | { |
cdd6c482 | 1331 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1332 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1333 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1334 | release_pmc_hardware(); |
1335 | mutex_unlock(&pmc_reserve_mutex); | |
1336 | } | |
1337 | } | |
1338 | ||
106b506c | 1339 | /* |
cdd6c482 | 1340 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1341 | */ |
1342 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1343 | { | |
1344 | unsigned long type, op, result; | |
1345 | int ev; | |
1346 | ||
1347 | if (!ppmu->cache_events) | |
1348 | return -EINVAL; | |
1349 | ||
1350 | /* unpack config */ | |
1351 | type = config & 0xff; | |
1352 | op = (config >> 8) & 0xff; | |
1353 | result = (config >> 16) & 0xff; | |
1354 | ||
1355 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1356 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1357 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1358 | return -EINVAL; | |
1359 | ||
1360 | ev = (*ppmu->cache_events)[type][op][result]; | |
1361 | if (ev == 0) | |
1362 | return -EOPNOTSUPP; | |
1363 | if (ev == -1) | |
1364 | return -EINVAL; | |
1365 | *eventp = ev; | |
1366 | return 0; | |
1367 | } | |
1368 | ||
b0a873eb | 1369 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1370 | { |
ef923214 PM |
1371 | u64 ev; |
1372 | unsigned long flags; | |
cdd6c482 IM |
1373 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1374 | u64 events[MAX_HWEVENTS]; | |
1375 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1376 | int n; |
7595d63b | 1377 | int err; |
cdd6c482 | 1378 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1379 | |
1380 | if (!ppmu) | |
b0a873eb PZ |
1381 | return -ENOENT; |
1382 | ||
3925f46b AK |
1383 | if (has_branch_stack(event)) { |
1384 | /* PMU has BHRB enabled */ | |
1385 | if (!(ppmu->flags & PPMU_BHRB)) | |
1386 | return -EOPNOTSUPP; | |
1387 | } | |
2481c5fa | 1388 | |
cdd6c482 | 1389 | switch (event->attr.type) { |
106b506c | 1390 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1391 | ev = event->attr.config; |
9aaa131a | 1392 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1393 | return -EOPNOTSUPP; |
4574910e | 1394 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1395 | break; |
1396 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1397 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1398 | if (err) |
b0a873eb | 1399 | return err; |
106b506c PM |
1400 | break; |
1401 | case PERF_TYPE_RAW: | |
cdd6c482 | 1402 | ev = event->attr.config; |
106b506c | 1403 | break; |
90c8f954 | 1404 | default: |
b0a873eb | 1405 | return -ENOENT; |
4574910e | 1406 | } |
b0a873eb | 1407 | |
cdd6c482 IM |
1408 | event->hw.config_base = ev; |
1409 | event->hw.idx = 0; | |
4574910e | 1410 | |
0475f9ea PM |
1411 | /* |
1412 | * If we are not running on a hypervisor, force the | |
1413 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1414 | * the user set it to. |
0475f9ea PM |
1415 | */ |
1416 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1417 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1418 | |
1419 | /* | |
cdd6c482 | 1420 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1421 | * PM_RUN_* events interchangeably with their non RUN_* |
1422 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1423 | * XXX we should check if the task is an idle task. | |
1424 | */ | |
1425 | flags = 0; | |
57fa7214 | 1426 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1427 | flags |= PPMU_ONLY_COUNT_RUN; |
1428 | ||
1429 | /* | |
cdd6c482 IM |
1430 | * If this machine has limited events, check whether this |
1431 | * event_id could go on a limited event. | |
ab7ef2e5 | 1432 | */ |
0bbd0d4b | 1433 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1434 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1435 | flags |= PPMU_LIMITED_PMC_OK; |
1436 | } else if (ppmu->limited_pmc_event(ev)) { | |
1437 | /* | |
cdd6c482 | 1438 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1439 | * but we can't use a limited PMC; see if any |
1440 | * alternative goes on a normal PMC. | |
1441 | */ | |
1442 | ev = normal_pmc_alternative(ev, flags); | |
1443 | if (!ev) | |
b0a873eb | 1444 | return -EINVAL; |
ab7ef2e5 PM |
1445 | } |
1446 | } | |
1447 | ||
4574910e PM |
1448 | /* |
1449 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1450 | * other hardware events in the group. We assume the event |
4574910e PM |
1451 | * hasn't been linked into its leader's sibling list at this point. |
1452 | */ | |
1453 | n = 0; | |
cdd6c482 | 1454 | if (event->group_leader != event) { |
a8f90e90 | 1455 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1456 | ctrs, events, cflags); |
4574910e | 1457 | if (n < 0) |
b0a873eb | 1458 | return -EINVAL; |
4574910e | 1459 | } |
0475f9ea | 1460 | events[n] = ev; |
cdd6c482 | 1461 | ctrs[n] = event; |
ab7ef2e5 PM |
1462 | cflags[n] = flags; |
1463 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1464 | return -EINVAL; |
e51ee31e | 1465 | |
cdd6c482 | 1466 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1467 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
3925f46b AK |
1468 | |
1469 | if (has_branch_stack(event)) { | |
1470 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( | |
1471 | event->attr.branch_sample_type); | |
1472 | ||
1473 | if(cpuhw->bhrb_filter == -1) | |
1474 | return -EOPNOTSUPP; | |
1475 | } | |
1476 | ||
cdd6c482 | 1477 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1478 | if (err) |
b0a873eb | 1479 | return -EINVAL; |
4574910e | 1480 | |
cdd6c482 IM |
1481 | event->hw.config = events[n]; |
1482 | event->hw.event_base = cflags[n]; | |
1483 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1484 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b PM |
1485 | |
1486 | /* | |
1487 | * See if we need to reserve the PMU. | |
cdd6c482 | 1488 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1489 | * mutex to ensure that we don't race with another task doing |
1490 | * reserve_pmc_hardware or release_pmc_hardware. | |
1491 | */ | |
1492 | err = 0; | |
cdd6c482 | 1493 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1494 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1495 | if (atomic_read(&num_events) == 0 && |
1496 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1497 | err = -EBUSY; |
1498 | else | |
cdd6c482 | 1499 | atomic_inc(&num_events); |
7595d63b PM |
1500 | mutex_unlock(&pmc_reserve_mutex); |
1501 | } | |
cdd6c482 | 1502 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1503 | |
b0a873eb | 1504 | return err; |
4574910e PM |
1505 | } |
1506 | ||
35edc2a5 PZ |
1507 | static int power_pmu_event_idx(struct perf_event *event) |
1508 | { | |
1509 | return event->hw.idx; | |
1510 | } | |
1511 | ||
1c53a270 SB |
1512 | ssize_t power_events_sysfs_show(struct device *dev, |
1513 | struct device_attribute *attr, char *page) | |
1514 | { | |
1515 | struct perf_pmu_events_attr *pmu_attr; | |
1516 | ||
1517 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
1518 | ||
1519 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
1520 | } | |
1521 | ||
b0a873eb | 1522 | struct pmu power_pmu = { |
a4eaf7f1 PZ |
1523 | .pmu_enable = power_pmu_enable, |
1524 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1525 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1526 | .add = power_pmu_add, |
1527 | .del = power_pmu_del, | |
1528 | .start = power_pmu_start, | |
1529 | .stop = power_pmu_stop, | |
b0a873eb | 1530 | .read = power_pmu_read, |
b0a873eb PZ |
1531 | .start_txn = power_pmu_start_txn, |
1532 | .cancel_txn = power_pmu_cancel_txn, | |
1533 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1534 | .event_idx = power_pmu_event_idx, |
3925f46b | 1535 | .flush_branch_stack = power_pmu_flush_branch_stack, |
b0a873eb PZ |
1536 | }; |
1537 | ||
4574910e | 1538 | /* |
57c0c15b | 1539 | * A counter has overflowed; update its count and record |
4574910e PM |
1540 | * things if requested. Note that interrupts are hard-disabled |
1541 | * here so there is no possibility of being interrupted. | |
1542 | */ | |
cdd6c482 | 1543 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1544 | struct pt_regs *regs) |
4574910e | 1545 | { |
cdd6c482 | 1546 | u64 period = event->hw.sample_period; |
4574910e PM |
1547 | s64 prev, delta, left; |
1548 | int record = 0; | |
1549 | ||
a4eaf7f1 PZ |
1550 | if (event->hw.state & PERF_HES_STOPPED) { |
1551 | write_pmc(event->hw.idx, 0); | |
1552 | return; | |
1553 | } | |
1554 | ||
4574910e | 1555 | /* we don't have to worry about interrupts here */ |
e7850595 | 1556 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 1557 | delta = check_and_compute_delta(prev, val); |
e7850595 | 1558 | local64_add(delta, &event->count); |
4574910e PM |
1559 | |
1560 | /* | |
cdd6c482 | 1561 | * See if the total period for this event has expired, |
4574910e PM |
1562 | * and update for the next period. |
1563 | */ | |
1564 | val = 0; | |
e7850595 | 1565 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
1566 | if (delta == 0) |
1567 | left++; | |
60db5e09 | 1568 | if (period) { |
4574910e | 1569 | if (left <= 0) { |
60db5e09 | 1570 | left += period; |
4574910e | 1571 | if (left <= 0) |
60db5e09 | 1572 | left = period; |
e6878835 | 1573 | record = siar_valid(regs); |
4bca770e | 1574 | event->hw.last_period = event->hw.sample_period; |
4574910e | 1575 | } |
98fb1807 PM |
1576 | if (left < 0x80000000LL) |
1577 | val = 0x80000000LL - left; | |
4574910e | 1578 | } |
4574910e | 1579 | |
a4eaf7f1 PZ |
1580 | write_pmc(event->hw.idx, val); |
1581 | local64_set(&event->hw.prev_count, val); | |
1582 | local64_set(&event->hw.period_left, left); | |
1583 | perf_event_update_userpage(event); | |
1584 | ||
4574910e PM |
1585 | /* |
1586 | * Finally record data if requested. | |
1587 | */ | |
0bbd0d4b | 1588 | if (record) { |
dc1d628a PZ |
1589 | struct perf_sample_data data; |
1590 | ||
fd0d000b | 1591 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 1592 | |
cdd6c482 | 1593 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
1594 | perf_get_data_addr(regs, &data.addr); |
1595 | ||
3925f46b AK |
1596 | if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { |
1597 | struct cpu_hw_events *cpuhw; | |
1598 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1599 | power_pmu_bhrb_read(cpuhw); | |
1600 | data.br_stack = &cpuhw->bhrb_stack; | |
1601 | } | |
1602 | ||
a8b0ca17 | 1603 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1604 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
1605 | } |
1606 | } | |
1607 | ||
1608 | /* | |
1609 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 1610 | * for an event_id. |
0bbd0d4b PM |
1611 | */ |
1612 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1613 | { | |
98fb1807 | 1614 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 1615 | |
98fb1807 PM |
1616 | if (flags) |
1617 | return flags; | |
cdd6c482 IM |
1618 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
1619 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
1620 | } |
1621 | ||
1622 | /* | |
1623 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 1624 | * for an event_id. |
0bbd0d4b PM |
1625 | */ |
1626 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1627 | { | |
33904054 | 1628 | bool use_siar = regs_use_siar(regs); |
0bbd0d4b | 1629 | |
e6878835 | 1630 | if (use_siar && siar_valid(regs)) |
75382aa7 | 1631 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 1632 | else if (use_siar) |
1633 | return 0; // no valid instruction pointer | |
75382aa7 | 1634 | else |
1ce447b9 | 1635 | return regs->nip; |
4574910e PM |
1636 | } |
1637 | ||
bc09c219 | 1638 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 1639 | { |
0837e324 AB |
1640 | /* |
1641 | * Events on POWER7 can roll back if a speculative event doesn't | |
1642 | * eventually complete. Unfortunately in some rare cases they will | |
1643 | * raise a performance monitor exception. We need to catch this to | |
1644 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
1645 | * cycles from overflow. | |
1646 | * | |
1647 | * We only do this if the first pass fails to find any overflowing | |
1648 | * PMCs because a user might set a period of less than 256 and we | |
1649 | * don't want to mistakenly reset them. | |
1650 | */ | |
bc09c219 MN |
1651 | if ((0x80000000 - val) <= 256) |
1652 | return true; | |
1653 | ||
1654 | return false; | |
1655 | } | |
1656 | ||
1657 | static bool pmc_overflow(unsigned long val) | |
1658 | { | |
1659 | if ((int)val < 0) | |
0837e324 AB |
1660 | return true; |
1661 | ||
1662 | return false; | |
1663 | } | |
1664 | ||
4574910e PM |
1665 | /* |
1666 | * Performance monitor interrupt stuff | |
1667 | */ | |
cdd6c482 | 1668 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 1669 | { |
bc09c219 | 1670 | int i, j; |
cdd6c482 IM |
1671 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); |
1672 | struct perf_event *event; | |
bc09c219 MN |
1673 | unsigned long val[8]; |
1674 | int found, active; | |
ca8f2d7f PM |
1675 | int nmi; |
1676 | ||
ab7ef2e5 | 1677 | if (cpuhw->n_limited) |
a8f90e90 | 1678 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
1679 | mfspr(SPRN_PMC6)); |
1680 | ||
98fb1807 | 1681 | perf_read_regs(regs); |
0bbd0d4b | 1682 | |
98fb1807 | 1683 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
1684 | if (nmi) |
1685 | nmi_enter(); | |
1686 | else | |
1687 | irq_enter(); | |
4574910e | 1688 | |
bc09c219 MN |
1689 | /* Read all the PMCs since we'll need them a bunch of times */ |
1690 | for (i = 0; i < ppmu->n_counter; ++i) | |
1691 | val[i] = read_pmc(i + 1); | |
1692 | ||
1693 | /* Try to find what caused the IRQ */ | |
1694 | found = 0; | |
1695 | for (i = 0; i < ppmu->n_counter; ++i) { | |
1696 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 1697 | continue; |
bc09c219 MN |
1698 | if (is_limited_pmc(i + 1)) |
1699 | continue; /* these won't generate IRQs */ | |
1700 | /* | |
1701 | * We've found one that's overflowed. For active | |
1702 | * counters we need to log this. For inactive | |
1703 | * counters, we need to reset it anyway | |
1704 | */ | |
1705 | found = 1; | |
1706 | active = 0; | |
1707 | for (j = 0; j < cpuhw->n_events; ++j) { | |
1708 | event = cpuhw->event[j]; | |
1709 | if (event->hw.idx == (i + 1)) { | |
1710 | active = 1; | |
1711 | record_and_restart(event, val[i], regs); | |
1712 | break; | |
1713 | } | |
4574910e | 1714 | } |
bc09c219 MN |
1715 | if (!active) |
1716 | /* reset non active counters that have overflowed */ | |
1717 | write_pmc(i + 1, 0); | |
4574910e | 1718 | } |
bc09c219 MN |
1719 | if (!found && pvr_version_is(PVR_POWER7)) { |
1720 | /* check active counters for special buggy p7 overflow */ | |
1721 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1722 | event = cpuhw->event[i]; | |
1723 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 1724 | continue; |
bc09c219 MN |
1725 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
1726 | /* event has overflowed in a buggy way*/ | |
1727 | found = 1; | |
1728 | record_and_restart(event, | |
1729 | val[event->hw.idx - 1], | |
1730 | regs); | |
1731 | } | |
4574910e PM |
1732 | } |
1733 | } | |
bc09c219 MN |
1734 | if ((!found) && printk_ratelimit()) |
1735 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); | |
4574910e PM |
1736 | |
1737 | /* | |
1738 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 1739 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 1740 | * and thus allow interrupts to occur again. |
cdd6c482 | 1741 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
1742 | * we get back out of this interrupt. |
1743 | */ | |
ab7ef2e5 | 1744 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1745 | |
ca8f2d7f PM |
1746 | if (nmi) |
1747 | nmi_exit(); | |
1748 | else | |
db4fb5ac | 1749 | irq_exit(); |
4574910e PM |
1750 | } |
1751 | ||
3f6da390 | 1752 | static void power_pmu_setup(int cpu) |
01d0287f | 1753 | { |
cdd6c482 | 1754 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 1755 | |
f36a1a13 PM |
1756 | if (!ppmu) |
1757 | return; | |
01d0287f PM |
1758 | memset(cpuhw, 0, sizeof(*cpuhw)); |
1759 | cpuhw->mmcr[0] = MMCR0_FC; | |
1760 | } | |
1761 | ||
3f6da390 | 1762 | static int __cpuinit |
85cfabbc | 1763 | power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
3f6da390 PZ |
1764 | { |
1765 | unsigned int cpu = (long)hcpu; | |
1766 | ||
1767 | switch (action & ~CPU_TASKS_FROZEN) { | |
1768 | case CPU_UP_PREPARE: | |
1769 | power_pmu_setup(cpu); | |
1770 | break; | |
1771 | ||
1772 | default: | |
1773 | break; | |
1774 | } | |
1775 | ||
1776 | return NOTIFY_OK; | |
1777 | } | |
1778 | ||
77c2342a | 1779 | int __cpuinit register_power_pmu(struct power_pmu *pmu) |
4574910e | 1780 | { |
079b3c56 PM |
1781 | if (ppmu) |
1782 | return -EBUSY; /* something's already registered */ | |
1783 | ||
1784 | ppmu = pmu; | |
1785 | pr_info("%s performance monitor hardware support registered\n", | |
1786 | pmu->name); | |
d095cd46 | 1787 | |
1c53a270 SB |
1788 | power_pmu.attr_groups = ppmu->attr_groups; |
1789 | ||
98fb1807 | 1790 | #ifdef MSR_HV |
d095cd46 PM |
1791 | /* |
1792 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
1793 | */ | |
1794 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 1795 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 1796 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 1797 | |
2e80a82a | 1798 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 PZ |
1799 | perf_cpu_notifier(power_pmu_notifier); |
1800 | ||
4574910e PM |
1801 | return 0; |
1802 | } |