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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
69123184 | 16 | #include <linux/uaccess.h> |
4574910e PM |
17 | #include <asm/reg.h> |
18 | #include <asm/pmc.h> | |
01d0287f | 19 | #include <asm/machdep.h> |
0475f9ea | 20 | #include <asm/firmware.h> |
0bbd0d4b | 21 | #include <asm/ptrace.h> |
69123184 | 22 | #include <asm/code-patching.h> |
4574910e | 23 | |
3925f46b AK |
24 | #define BHRB_MAX_ENTRIES 32 |
25 | #define BHRB_TARGET 0x0000000000000002 | |
26 | #define BHRB_PREDICTION 0x0000000000000001 | |
27 | #define BHRB_EA 0xFFFFFFFFFFFFFFFC | |
28 | ||
cdd6c482 IM |
29 | struct cpu_hw_events { |
30 | int n_events; | |
4574910e PM |
31 | int n_percpu; |
32 | int disabled; | |
33 | int n_added; | |
ab7ef2e5 PM |
34 | int n_limited; |
35 | u8 pmcs_enabled; | |
cdd6c482 IM |
36 | struct perf_event *event[MAX_HWEVENTS]; |
37 | u64 events[MAX_HWEVENTS]; | |
38 | unsigned int flags[MAX_HWEVENTS]; | |
448d64f8 | 39 | unsigned long mmcr[3]; |
a8f90e90 PM |
40 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
41 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
42 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
43 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
44 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 LM |
45 | |
46 | unsigned int group_flag; | |
47 | int n_txn_start; | |
3925f46b AK |
48 | |
49 | /* BHRB bits */ | |
50 | u64 bhrb_filter; /* BHRB HW branch filter */ | |
51 | int bhrb_users; | |
52 | void *bhrb_context; | |
53 | struct perf_branch_stack bhrb_stack; | |
54 | struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; | |
4574910e | 55 | }; |
3925f46b | 56 | |
cdd6c482 | 57 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e PM |
58 | |
59 | struct power_pmu *ppmu; | |
60 | ||
d095cd46 | 61 | /* |
57c0c15b | 62 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
63 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
64 | * hypervisor bit set in the MSR, or if we are running on a processor | |
65 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
66 | * then we need to use the FCHV bit to ignore kernel events. | |
67 | */ | |
cdd6c482 | 68 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 69 | |
98fb1807 PM |
70 | /* |
71 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
72 | * and a few other names are different. | |
73 | */ | |
74 | #ifdef CONFIG_PPC32 | |
75 | ||
76 | #define MMCR0_FCHV 0 | |
77 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
78 | ||
79 | #define SPRN_MMCRA SPRN_MMCR2 | |
80 | #define MMCRA_SAMPLE_ENABLE 0 | |
81 | ||
82 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
83 | { | |
84 | return 0; | |
85 | } | |
98fb1807 PM |
86 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
87 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
88 | { | |
89 | return 0; | |
90 | } | |
75382aa7 AB |
91 | static inline void perf_read_regs(struct pt_regs *regs) |
92 | { | |
93 | regs->result = 0; | |
94 | } | |
98fb1807 PM |
95 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
96 | { | |
97 | return 0; | |
98 | } | |
99 | ||
e6878835 | 100 | static inline int siar_valid(struct pt_regs *regs) |
101 | { | |
102 | return 1; | |
103 | } | |
104 | ||
d52f2dc4 MN |
105 | static inline void power_pmu_bhrb_enable(struct perf_event *event) {} |
106 | static inline void power_pmu_bhrb_disable(struct perf_event *event) {} | |
107 | void power_pmu_flush_branch_stack(void) {} | |
108 | static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} | |
98fb1807 PM |
109 | #endif /* CONFIG_PPC32 */ |
110 | ||
33904054 ME |
111 | static bool regs_use_siar(struct pt_regs *regs) |
112 | { | |
cbda6aa1 | 113 | return !!regs->result; |
33904054 ME |
114 | } |
115 | ||
98fb1807 PM |
116 | /* |
117 | * Things that are specific to 64-bit implementations. | |
118 | */ | |
119 | #ifdef CONFIG_PPC64 | |
120 | ||
121 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
122 | { | |
123 | unsigned long mmcra = regs->dsisr; | |
124 | ||
7a786832 | 125 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
126 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
127 | if (slot > 1) | |
128 | return 4 * (slot - 1); | |
129 | } | |
7a786832 | 130 | |
98fb1807 PM |
131 | return 0; |
132 | } | |
133 | ||
98fb1807 PM |
134 | /* |
135 | * The user wants a data address recorded. | |
136 | * If we're not doing instruction sampling, give them the SDAR | |
137 | * (sampled data address). If we are doing instruction sampling, then | |
138 | * only give them the SDAR if it corresponds to the instruction | |
58a032c3 ME |
139 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the |
140 | * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. | |
98fb1807 PM |
141 | */ |
142 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
143 | { | |
144 | unsigned long mmcra = regs->dsisr; | |
58a032c3 | 145 | bool sdar_valid; |
e6878835 | 146 | |
58a032c3 ME |
147 | if (ppmu->flags & PPMU_HAS_SIER) |
148 | sdar_valid = regs->dar & SIER_SDAR_VALID; | |
149 | else { | |
150 | unsigned long sdsync; | |
151 | ||
152 | if (ppmu->flags & PPMU_SIAR_VALID) | |
153 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
154 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
155 | sdsync = POWER6_MMCRA_SDSYNC; | |
156 | else | |
157 | sdsync = MMCRA_SDSYNC; | |
158 | ||
159 | sdar_valid = mmcra & sdsync; | |
160 | } | |
98fb1807 | 161 | |
58a032c3 | 162 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) |
98fb1807 PM |
163 | *addrp = mfspr(SPRN_SDAR); |
164 | } | |
165 | ||
5682c460 | 166 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
167 | { |
168 | unsigned long sihv = MMCRA_SIHV; | |
169 | ||
8f61aa32 ME |
170 | if (ppmu->flags & PPMU_HAS_SIER) |
171 | return !!(regs->dar & SIER_SIHV); | |
172 | ||
68b30bb9 AB |
173 | if (ppmu->flags & PPMU_ALT_SIPR) |
174 | sihv = POWER6_MMCRA_SIHV; | |
175 | ||
5682c460 | 176 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
177 | } |
178 | ||
5682c460 | 179 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
180 | { |
181 | unsigned long sipr = MMCRA_SIPR; | |
182 | ||
8f61aa32 ME |
183 | if (ppmu->flags & PPMU_HAS_SIER) |
184 | return !!(regs->dar & SIER_SIPR); | |
185 | ||
68b30bb9 AB |
186 | if (ppmu->flags & PPMU_ALT_SIPR) |
187 | sipr = POWER6_MMCRA_SIPR; | |
188 | ||
5682c460 | 189 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
190 | } |
191 | ||
1ce447b9 BH |
192 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
193 | { | |
194 | if (regs->msr & MSR_PR) | |
195 | return PERF_RECORD_MISC_USER; | |
196 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
197 | return PERF_RECORD_MISC_HYPERVISOR; | |
198 | return PERF_RECORD_MISC_KERNEL; | |
199 | } | |
200 | ||
98fb1807 PM |
201 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
202 | { | |
33904054 | 203 | bool use_siar = regs_use_siar(regs); |
98fb1807 | 204 | |
75382aa7 | 205 | if (!use_siar) |
1ce447b9 BH |
206 | return perf_flags_from_msr(regs); |
207 | ||
208 | /* | |
209 | * If we don't have flags in MMCRA, rather than using | |
210 | * the MSR, we intuit the flags from the address in | |
211 | * SIAR which should give slightly more reliable | |
212 | * results | |
213 | */ | |
cbda6aa1 | 214 | if (ppmu->flags & PPMU_NO_SIPR) { |
1ce447b9 BH |
215 | unsigned long siar = mfspr(SPRN_SIAR); |
216 | if (siar >= PAGE_OFFSET) | |
217 | return PERF_RECORD_MISC_KERNEL; | |
218 | return PERF_RECORD_MISC_USER; | |
219 | } | |
98fb1807 | 220 | |
7abb840b | 221 | /* PR has priority over HV, so order below is important */ |
5682c460 | 222 | if (regs_sipr(regs)) |
7abb840b | 223 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
224 | |
225 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 226 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 227 | |
7abb840b | 228 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
229 | } |
230 | ||
231 | /* | |
232 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
233 | * on each interrupt. | |
8f61aa32 | 234 | * Overload regs->dar to store SIER if we have it. |
75382aa7 AB |
235 | * Overload regs->result to specify whether we should use the MSR (result |
236 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
237 | */ |
238 | static inline void perf_read_regs(struct pt_regs *regs) | |
239 | { | |
75382aa7 AB |
240 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
241 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
242 | int use_siar; | |
243 | ||
5682c460 | 244 | regs->dsisr = mmcra; |
8f61aa32 | 245 | |
cbda6aa1 ME |
246 | if (ppmu->flags & PPMU_HAS_SIER) |
247 | regs->dar = mfspr(SPRN_SIER); | |
8f61aa32 | 248 | |
5c093efa AB |
249 | /* |
250 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
251 | * not valid. Use pt_regs. | |
252 | * | |
253 | * If it is a marked event use the SIAR. | |
254 | * | |
255 | * If the PMU doesn't update the SIAR for non marked events use | |
256 | * pt_regs. | |
257 | * | |
258 | * If the PMU has HV/PR flags then check to see if they | |
259 | * place the exception in userspace. If so, use pt_regs. In | |
260 | * continuous sampling mode the SIAR and the PMU exception are | |
261 | * not synchronised, so they may be many instructions apart. | |
262 | * This can result in confusing backtraces. We still want | |
263 | * hypervisor samples as well as samples in the kernel with | |
264 | * interrupts off hence the userspace check. | |
265 | */ | |
75382aa7 AB |
266 | if (TRAP(regs) != 0xf00) |
267 | use_siar = 0; | |
5c093efa AB |
268 | else if (marked) |
269 | use_siar = 1; | |
270 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
271 | use_siar = 0; | |
cbda6aa1 | 272 | else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) |
75382aa7 AB |
273 | use_siar = 0; |
274 | else | |
275 | use_siar = 1; | |
276 | ||
cbda6aa1 | 277 | regs->result = use_siar; |
98fb1807 PM |
278 | } |
279 | ||
280 | /* | |
281 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
282 | * it as an NMI. | |
283 | */ | |
284 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
285 | { | |
286 | return !regs->softe; | |
287 | } | |
288 | ||
e6878835 | 289 | /* |
290 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
291 | * must be sampled only if the SIAR-valid bit is set. | |
292 | * | |
293 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
294 | * bit, assume that SIAR is valid. | |
295 | */ | |
296 | static inline int siar_valid(struct pt_regs *regs) | |
297 | { | |
298 | unsigned long mmcra = regs->dsisr; | |
299 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
300 | ||
58a032c3 ME |
301 | if (marked) { |
302 | if (ppmu->flags & PPMU_HAS_SIER) | |
303 | return regs->dar & SIER_SIAR_VALID; | |
304 | ||
305 | if (ppmu->flags & PPMU_SIAR_VALID) | |
306 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
307 | } | |
e6878835 | 308 | |
309 | return 1; | |
310 | } | |
311 | ||
d52f2dc4 MN |
312 | |
313 | /* Reset all possible BHRB entries */ | |
314 | static void power_pmu_bhrb_reset(void) | |
315 | { | |
316 | asm volatile(PPC_CLRBHRB); | |
317 | } | |
318 | ||
319 | static void power_pmu_bhrb_enable(struct perf_event *event) | |
320 | { | |
321 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
322 | ||
323 | if (!ppmu->bhrb_nr) | |
324 | return; | |
325 | ||
326 | /* Clear BHRB if we changed task context to avoid data leaks */ | |
327 | if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { | |
328 | power_pmu_bhrb_reset(); | |
329 | cpuhw->bhrb_context = event->ctx; | |
330 | } | |
331 | cpuhw->bhrb_users++; | |
332 | } | |
333 | ||
334 | static void power_pmu_bhrb_disable(struct perf_event *event) | |
335 | { | |
336 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
337 | ||
338 | if (!ppmu->bhrb_nr) | |
339 | return; | |
340 | ||
341 | cpuhw->bhrb_users--; | |
342 | WARN_ON_ONCE(cpuhw->bhrb_users < 0); | |
343 | ||
344 | if (!cpuhw->disabled && !cpuhw->bhrb_users) { | |
345 | /* BHRB cannot be turned off when other | |
346 | * events are active on the PMU. | |
347 | */ | |
348 | ||
349 | /* avoid stale pointer */ | |
350 | cpuhw->bhrb_context = NULL; | |
351 | } | |
352 | } | |
353 | ||
354 | /* Called from ctxsw to prevent one process's branch entries to | |
355 | * mingle with the other process's entries during context switch. | |
356 | */ | |
357 | void power_pmu_flush_branch_stack(void) | |
358 | { | |
359 | if (ppmu->bhrb_nr) | |
360 | power_pmu_bhrb_reset(); | |
361 | } | |
69123184 MN |
362 | /* Calculate the to address for a branch */ |
363 | static __u64 power_pmu_bhrb_to(u64 addr) | |
364 | { | |
365 | unsigned int instr; | |
366 | int ret; | |
367 | __u64 target; | |
368 | ||
369 | if (is_kernel_addr(addr)) | |
370 | return branch_target((unsigned int *)addr); | |
371 | ||
372 | /* Userspace: need copy instruction here then translate it */ | |
373 | pagefault_disable(); | |
374 | ret = __get_user_inatomic(instr, (unsigned int __user *)addr); | |
375 | if (ret) { | |
376 | pagefault_enable(); | |
377 | return 0; | |
378 | } | |
379 | pagefault_enable(); | |
380 | ||
381 | target = branch_target(&instr); | |
382 | if ((!target) || (instr & BRANCH_ABSOLUTE)) | |
383 | return target; | |
384 | ||
385 | /* Translate relative branch target from kernel to user address */ | |
386 | return target - (unsigned long)&instr + addr; | |
387 | } | |
d52f2dc4 | 388 | |
d52f2dc4 | 389 | /* Processing BHRB entries */ |
506e70d1 | 390 | void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) |
d52f2dc4 MN |
391 | { |
392 | u64 val; | |
393 | u64 addr; | |
506e70d1 | 394 | int r_index, u_index, pred; |
d52f2dc4 MN |
395 | |
396 | r_index = 0; | |
397 | u_index = 0; | |
398 | while (r_index < ppmu->bhrb_nr) { | |
399 | /* Assembly read function */ | |
506e70d1 MN |
400 | val = read_bhrb(r_index++); |
401 | if (!val) | |
402 | /* Terminal marker: End of valid BHRB entries */ | |
d52f2dc4 | 403 | break; |
506e70d1 | 404 | else { |
d52f2dc4 MN |
405 | addr = val & BHRB_EA; |
406 | pred = val & BHRB_PREDICTION; | |
d52f2dc4 | 407 | |
506e70d1 MN |
408 | if (!addr) |
409 | /* invalid entry */ | |
d52f2dc4 | 410 | continue; |
d52f2dc4 | 411 | |
506e70d1 MN |
412 | /* Branches are read most recent first (ie. mfbhrb 0 is |
413 | * the most recent branch). | |
414 | * There are two types of valid entries: | |
415 | * 1) a target entry which is the to address of a | |
416 | * computed goto like a blr,bctr,btar. The next | |
417 | * entry read from the bhrb will be branch | |
418 | * corresponding to this target (ie. the actual | |
419 | * blr/bctr/btar instruction). | |
420 | * 2) a from address which is an actual branch. If a | |
421 | * target entry proceeds this, then this is the | |
422 | * matching branch for that target. If this is not | |
423 | * following a target entry, then this is a branch | |
424 | * where the target is given as an immediate field | |
425 | * in the instruction (ie. an i or b form branch). | |
426 | * In this case we need to read the instruction from | |
427 | * memory to determine the target/to address. | |
428 | */ | |
d52f2dc4 | 429 | |
d52f2dc4 | 430 | if (val & BHRB_TARGET) { |
506e70d1 MN |
431 | /* Target branches use two entries |
432 | * (ie. computed gotos/XL form) | |
433 | */ | |
434 | cpuhw->bhrb_entries[u_index].to = addr; | |
435 | cpuhw->bhrb_entries[u_index].mispred = pred; | |
436 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 437 | |
506e70d1 MN |
438 | /* Get from address in next entry */ |
439 | val = read_bhrb(r_index++); | |
440 | addr = val & BHRB_EA; | |
441 | if (val & BHRB_TARGET) { | |
442 | /* Shouldn't have two targets in a | |
443 | row.. Reset index and try again */ | |
444 | r_index--; | |
445 | addr = 0; | |
446 | } | |
447 | cpuhw->bhrb_entries[u_index].from = addr; | |
d52f2dc4 | 448 | } else { |
506e70d1 MN |
449 | /* Branches to immediate field |
450 | (ie I or B form) */ | |
d52f2dc4 | 451 | cpuhw->bhrb_entries[u_index].from = addr; |
69123184 MN |
452 | cpuhw->bhrb_entries[u_index].to = |
453 | power_pmu_bhrb_to(addr); | |
d52f2dc4 MN |
454 | cpuhw->bhrb_entries[u_index].mispred = pred; |
455 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 456 | } |
506e70d1 MN |
457 | u_index++; |
458 | ||
d52f2dc4 MN |
459 | } |
460 | } | |
461 | cpuhw->bhrb_stack.nr = u_index; | |
462 | return; | |
463 | } | |
464 | ||
98fb1807 PM |
465 | #endif /* CONFIG_PPC64 */ |
466 | ||
cdd6c482 | 467 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 468 | |
cdd6c482 | 469 | void perf_event_print_debug(void) |
4574910e PM |
470 | { |
471 | } | |
472 | ||
4574910e | 473 | /* |
57c0c15b | 474 | * Read one performance monitor counter (PMC). |
4574910e PM |
475 | */ |
476 | static unsigned long read_pmc(int idx) | |
477 | { | |
478 | unsigned long val; | |
479 | ||
480 | switch (idx) { | |
481 | case 1: | |
482 | val = mfspr(SPRN_PMC1); | |
483 | break; | |
484 | case 2: | |
485 | val = mfspr(SPRN_PMC2); | |
486 | break; | |
487 | case 3: | |
488 | val = mfspr(SPRN_PMC3); | |
489 | break; | |
490 | case 4: | |
491 | val = mfspr(SPRN_PMC4); | |
492 | break; | |
493 | case 5: | |
494 | val = mfspr(SPRN_PMC5); | |
495 | break; | |
496 | case 6: | |
497 | val = mfspr(SPRN_PMC6); | |
498 | break; | |
98fb1807 | 499 | #ifdef CONFIG_PPC64 |
4574910e PM |
500 | case 7: |
501 | val = mfspr(SPRN_PMC7); | |
502 | break; | |
503 | case 8: | |
504 | val = mfspr(SPRN_PMC8); | |
505 | break; | |
98fb1807 | 506 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
507 | default: |
508 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
509 | val = 0; | |
510 | } | |
511 | return val; | |
512 | } | |
513 | ||
514 | /* | |
515 | * Write one PMC. | |
516 | */ | |
517 | static void write_pmc(int idx, unsigned long val) | |
518 | { | |
519 | switch (idx) { | |
520 | case 1: | |
521 | mtspr(SPRN_PMC1, val); | |
522 | break; | |
523 | case 2: | |
524 | mtspr(SPRN_PMC2, val); | |
525 | break; | |
526 | case 3: | |
527 | mtspr(SPRN_PMC3, val); | |
528 | break; | |
529 | case 4: | |
530 | mtspr(SPRN_PMC4, val); | |
531 | break; | |
532 | case 5: | |
533 | mtspr(SPRN_PMC5, val); | |
534 | break; | |
535 | case 6: | |
536 | mtspr(SPRN_PMC6, val); | |
537 | break; | |
98fb1807 | 538 | #ifdef CONFIG_PPC64 |
4574910e PM |
539 | case 7: |
540 | mtspr(SPRN_PMC7, val); | |
541 | break; | |
542 | case 8: | |
543 | mtspr(SPRN_PMC8, val); | |
544 | break; | |
98fb1807 | 545 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
546 | default: |
547 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
548 | } | |
549 | } | |
550 | ||
551 | /* | |
552 | * Check if a set of events can all go on the PMU at once. | |
553 | * If they can't, this will look at alternative codes for the events | |
554 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 555 | * The feasible set is returned in event_id[]. |
4574910e | 556 | */ |
cdd6c482 IM |
557 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
558 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 559 | int n_ev) |
4574910e | 560 | { |
448d64f8 | 561 | unsigned long mask, value, nv; |
cdd6c482 IM |
562 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
563 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 564 | int i, j; |
448d64f8 PM |
565 | unsigned long addf = ppmu->add_fields; |
566 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 567 | |
a8f90e90 | 568 | if (n_ev > ppmu->n_counter) |
4574910e PM |
569 | return -1; |
570 | ||
571 | /* First see if the events will go on as-is */ | |
572 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 573 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
574 | && !ppmu->limited_pmc_event(event_id[i])) { |
575 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 576 | cpuhw->alternatives[i]); |
cdd6c482 | 577 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 578 | } |
cdd6c482 | 579 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 580 | &cpuhw->avalues[i][0])) |
4574910e | 581 | return -1; |
4574910e PM |
582 | } |
583 | value = mask = 0; | |
584 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
585 | nv = (value | cpuhw->avalues[i][0]) + |
586 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 587 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
588 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
589 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
590 | break; |
591 | value = nv; | |
e51ee31e | 592 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
593 | } |
594 | if (i == n_ev) | |
595 | return 0; /* all OK */ | |
596 | ||
597 | /* doesn't work, gather alternatives... */ | |
598 | if (!ppmu->get_alternatives) | |
599 | return -1; | |
600 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 601 | choice[i] = 0; |
cdd6c482 | 602 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 603 | cpuhw->alternatives[i]); |
4574910e | 604 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
605 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
606 | &cpuhw->amasks[i][j], | |
607 | &cpuhw->avalues[i][j]); | |
4574910e PM |
608 | } |
609 | ||
610 | /* enumerate all possibilities and see if any will work */ | |
611 | i = 0; | |
612 | j = -1; | |
613 | value = mask = nv = 0; | |
614 | while (i < n_ev) { | |
615 | if (j >= 0) { | |
616 | /* we're backtracking, restore context */ | |
617 | value = svalues[i]; | |
618 | mask = smasks[i]; | |
619 | j = choice[i]; | |
620 | } | |
621 | /* | |
cdd6c482 | 622 | * See if any alternative k for event_id i, |
4574910e PM |
623 | * where k > j, will satisfy the constraints. |
624 | */ | |
625 | while (++j < n_alt[i]) { | |
e51ee31e PM |
626 | nv = (value | cpuhw->avalues[i][j]) + |
627 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 628 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
629 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
630 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
631 | break; |
632 | } | |
633 | if (j >= n_alt[i]) { | |
634 | /* | |
635 | * No feasible alternative, backtrack | |
cdd6c482 | 636 | * to event_id i-1 and continue enumerating its |
4574910e PM |
637 | * alternatives from where we got up to. |
638 | */ | |
639 | if (--i < 0) | |
640 | return -1; | |
641 | } else { | |
642 | /* | |
cdd6c482 IM |
643 | * Found a feasible alternative for event_id i, |
644 | * remember where we got up to with this event_id, | |
645 | * go on to the next event_id, and start with | |
4574910e PM |
646 | * the first alternative for it. |
647 | */ | |
648 | choice[i] = j; | |
649 | svalues[i] = value; | |
650 | smasks[i] = mask; | |
651 | value = nv; | |
e51ee31e | 652 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
653 | ++i; |
654 | j = -1; | |
655 | } | |
656 | } | |
657 | ||
658 | /* OK, we have a feasible combination, tell the caller the solution */ | |
659 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 660 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
661 | return 0; |
662 | } | |
663 | ||
0475f9ea | 664 | /* |
cdd6c482 | 665 | * Check if newly-added events have consistent settings for |
0475f9ea | 666 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 667 | * added events. |
0475f9ea | 668 | */ |
cdd6c482 | 669 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 670 | int n_prev, int n_new) |
0475f9ea | 671 | { |
ab7ef2e5 PM |
672 | int eu = 0, ek = 0, eh = 0; |
673 | int i, n, first; | |
cdd6c482 | 674 | struct perf_event *event; |
0475f9ea PM |
675 | |
676 | n = n_prev + n_new; | |
677 | if (n <= 1) | |
678 | return 0; | |
679 | ||
ab7ef2e5 PM |
680 | first = 1; |
681 | for (i = 0; i < n; ++i) { | |
682 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
683 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
684 | continue; | |
685 | } | |
cdd6c482 | 686 | event = ctrs[i]; |
ab7ef2e5 | 687 | if (first) { |
cdd6c482 IM |
688 | eu = event->attr.exclude_user; |
689 | ek = event->attr.exclude_kernel; | |
690 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 691 | first = 0; |
cdd6c482 IM |
692 | } else if (event->attr.exclude_user != eu || |
693 | event->attr.exclude_kernel != ek || | |
694 | event->attr.exclude_hv != eh) { | |
0475f9ea | 695 | return -EAGAIN; |
ab7ef2e5 | 696 | } |
0475f9ea | 697 | } |
ab7ef2e5 PM |
698 | |
699 | if (eu || ek || eh) | |
700 | for (i = 0; i < n; ++i) | |
701 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
702 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
703 | ||
0475f9ea PM |
704 | return 0; |
705 | } | |
706 | ||
86c74ab3 EM |
707 | static u64 check_and_compute_delta(u64 prev, u64 val) |
708 | { | |
709 | u64 delta = (val - prev) & 0xfffffffful; | |
710 | ||
711 | /* | |
712 | * POWER7 can roll back counter values, if the new value is smaller | |
713 | * than the previous value it will cause the delta and the counter to | |
714 | * have bogus values unless we rolled a counter over. If a coutner is | |
715 | * rolled back, it will be smaller, but within 256, which is the maximum | |
716 | * number of events to rollback at once. If we dectect a rollback | |
717 | * return 0. This can lead to a small lack of precision in the | |
718 | * counters. | |
719 | */ | |
720 | if (prev > val && (prev - val) < 256) | |
721 | delta = 0; | |
722 | ||
723 | return delta; | |
724 | } | |
725 | ||
cdd6c482 | 726 | static void power_pmu_read(struct perf_event *event) |
4574910e | 727 | { |
98fb1807 | 728 | s64 val, delta, prev; |
4574910e | 729 | |
a4eaf7f1 PZ |
730 | if (event->hw.state & PERF_HES_STOPPED) |
731 | return; | |
732 | ||
cdd6c482 | 733 | if (!event->hw.idx) |
4574910e PM |
734 | return; |
735 | /* | |
736 | * Performance monitor interrupts come even when interrupts | |
737 | * are soft-disabled, as long as interrupts are hard-enabled. | |
738 | * Therefore we treat them like NMIs. | |
739 | */ | |
740 | do { | |
e7850595 | 741 | prev = local64_read(&event->hw.prev_count); |
4574910e | 742 | barrier(); |
cdd6c482 | 743 | val = read_pmc(event->hw.idx); |
86c74ab3 EM |
744 | delta = check_and_compute_delta(prev, val); |
745 | if (!delta) | |
746 | return; | |
e7850595 | 747 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 748 | |
e7850595 PZ |
749 | local64_add(delta, &event->count); |
750 | local64_sub(delta, &event->hw.period_left); | |
4574910e PM |
751 | } |
752 | ||
ab7ef2e5 PM |
753 | /* |
754 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
755 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 756 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
757 | */ |
758 | static int is_limited_pmc(int pmcnum) | |
759 | { | |
0bbd0d4b PM |
760 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
761 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
762 | } |
763 | ||
a8f90e90 | 764 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
765 | unsigned long pmc5, unsigned long pmc6) |
766 | { | |
cdd6c482 | 767 | struct perf_event *event; |
ab7ef2e5 PM |
768 | u64 val, prev, delta; |
769 | int i; | |
770 | ||
771 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 772 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 773 | if (!event->hw.idx) |
ab7ef2e5 | 774 | continue; |
cdd6c482 | 775 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 776 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 777 | event->hw.idx = 0; |
86c74ab3 EM |
778 | delta = check_and_compute_delta(prev, val); |
779 | if (delta) | |
780 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
781 | } |
782 | } | |
783 | ||
a8f90e90 | 784 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
785 | unsigned long pmc5, unsigned long pmc6) |
786 | { | |
cdd6c482 | 787 | struct perf_event *event; |
86c74ab3 | 788 | u64 val, prev; |
ab7ef2e5 PM |
789 | int i; |
790 | ||
791 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 792 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
793 | event->hw.idx = cpuhw->limited_hwidx[i]; |
794 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
795 | prev = local64_read(&event->hw.prev_count); |
796 | if (check_and_compute_delta(prev, val)) | |
797 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 798 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
799 | } |
800 | } | |
801 | ||
802 | /* | |
cdd6c482 | 803 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 804 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
805 | * other events. We try to keep the values from the limited |
806 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 807 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
808 | * the limited events as small and consistent as possible. |
809 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
810 | * both, and always in the same order, to minimize variability, |
811 | * and do it inside the same asm that writes MMCR0. | |
812 | */ | |
cdd6c482 | 813 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
814 | { |
815 | unsigned long pmc5, pmc6; | |
816 | ||
817 | if (!cpuhw->n_limited) { | |
818 | mtspr(SPRN_MMCR0, mmcr0); | |
819 | return; | |
820 | } | |
821 | ||
822 | /* | |
823 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
824 | * To ensure we don't get a performance monitor interrupt |
825 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 826 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 827 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
828 | */ |
829 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
830 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
831 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
832 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
833 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
834 | ||
835 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 836 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 837 | else |
a8f90e90 | 838 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
839 | |
840 | /* | |
cdd6c482 | 841 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
842 | * enable bits, if necessary. |
843 | */ | |
844 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
845 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
846 | } |
847 | ||
4574910e | 848 | /* |
cdd6c482 IM |
849 | * Disable all events to prevent PMU interrupts and to allow |
850 | * events to be added or removed. | |
4574910e | 851 | */ |
a4eaf7f1 | 852 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 853 | { |
cdd6c482 | 854 | struct cpu_hw_events *cpuhw; |
4574910e PM |
855 | unsigned long flags; |
856 | ||
f36a1a13 PM |
857 | if (!ppmu) |
858 | return; | |
4574910e | 859 | local_irq_save(flags); |
cdd6c482 | 860 | cpuhw = &__get_cpu_var(cpu_hw_events); |
4574910e | 861 | |
448d64f8 | 862 | if (!cpuhw->disabled) { |
4574910e PM |
863 | cpuhw->disabled = 1; |
864 | cpuhw->n_added = 0; | |
865 | ||
01d0287f PM |
866 | /* |
867 | * Check if we ever enabled the PMU on this cpu. | |
868 | */ | |
869 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 870 | ppc_enable_pmcs(); |
01d0287f PM |
871 | cpuhw->pmcs_enabled = 1; |
872 | } | |
873 | ||
f708223d PM |
874 | /* |
875 | * Disable instruction sampling if it was enabled | |
876 | */ | |
877 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
878 | mtspr(SPRN_MMCRA, | |
879 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
880 | mb(); | |
881 | } | |
882 | ||
4574910e | 883 | /* |
57c0c15b | 884 | * Set the 'freeze counters' bit. |
4574910e | 885 | * The barrier is to make sure the mtspr has been |
cdd6c482 | 886 | * executed and the PMU has frozen the events |
4574910e PM |
887 | * before we return. |
888 | */ | |
ab7ef2e5 | 889 | write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); |
4574910e PM |
890 | mb(); |
891 | } | |
892 | local_irq_restore(flags); | |
4574910e PM |
893 | } |
894 | ||
895 | /* | |
cdd6c482 IM |
896 | * Re-enable all events if disable == 0. |
897 | * If we were previously disabled and events were added, then | |
4574910e PM |
898 | * put the new config on the PMU. |
899 | */ | |
a4eaf7f1 | 900 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 901 | { |
cdd6c482 IM |
902 | struct perf_event *event; |
903 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
904 | unsigned long flags; |
905 | long i; | |
906 | unsigned long val; | |
907 | s64 left; | |
cdd6c482 | 908 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
909 | int n_lim; |
910 | int idx; | |
4574910e | 911 | |
f36a1a13 PM |
912 | if (!ppmu) |
913 | return; | |
4574910e | 914 | local_irq_save(flags); |
cdd6c482 | 915 | cpuhw = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
916 | if (!cpuhw->disabled) { |
917 | local_irq_restore(flags); | |
918 | return; | |
919 | } | |
4574910e PM |
920 | cpuhw->disabled = 0; |
921 | ||
922 | /* | |
cdd6c482 | 923 | * If we didn't change anything, or only removed events, |
4574910e PM |
924 | * no need to recalculate MMCR* settings and reset the PMCs. |
925 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 926 | * (possibly updated for removal of events). |
4574910e PM |
927 | */ |
928 | if (!cpuhw->n_added) { | |
f708223d | 929 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 930 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
cdd6c482 | 931 | if (cpuhw->n_events == 0) |
a6dbf93a | 932 | ppc_set_pmu_inuse(0); |
f708223d | 933 | goto out_enable; |
4574910e PM |
934 | } |
935 | ||
936 | /* | |
cdd6c482 | 937 | * Compute MMCR* values for the new set of events |
4574910e | 938 | */ |
cdd6c482 | 939 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
4574910e PM |
940 | cpuhw->mmcr)) { |
941 | /* shouldn't ever get here */ | |
942 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
943 | goto out; | |
944 | } | |
945 | ||
0475f9ea PM |
946 | /* |
947 | * Add in MMCR0 freeze bits corresponding to the | |
cdd6c482 IM |
948 | * attr.exclude_* bits for the first event. |
949 | * We have already checked that all events have the | |
950 | * same values for these bits as the first event. | |
0475f9ea | 951 | */ |
cdd6c482 IM |
952 | event = cpuhw->event[0]; |
953 | if (event->attr.exclude_user) | |
0475f9ea | 954 | cpuhw->mmcr[0] |= MMCR0_FCP; |
cdd6c482 IM |
955 | if (event->attr.exclude_kernel) |
956 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
957 | if (event->attr.exclude_hv) | |
0475f9ea PM |
958 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
959 | ||
4574910e PM |
960 | /* |
961 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
962 | * bit set and set the hardware events to their initial values. |
963 | * Then unfreeze the events. | |
4574910e | 964 | */ |
a6dbf93a | 965 | ppc_set_pmu_inuse(1); |
f708223d | 966 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
967 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
968 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
969 | | MMCR0_FC); | |
970 | ||
971 | /* | |
cdd6c482 | 972 | * Read off any pre-existing events that need to move |
4574910e PM |
973 | * to another PMC. |
974 | */ | |
cdd6c482 IM |
975 | for (i = 0; i < cpuhw->n_events; ++i) { |
976 | event = cpuhw->event[i]; | |
977 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
978 | power_pmu_read(event); | |
979 | write_pmc(event->hw.idx, 0); | |
980 | event->hw.idx = 0; | |
4574910e PM |
981 | } |
982 | } | |
983 | ||
984 | /* | |
cdd6c482 | 985 | * Initialize the PMCs for all the new and moved events. |
4574910e | 986 | */ |
ab7ef2e5 | 987 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
988 | for (i = 0; i < cpuhw->n_events; ++i) { |
989 | event = cpuhw->event[i]; | |
990 | if (event->hw.idx) | |
4574910e | 991 | continue; |
ab7ef2e5 PM |
992 | idx = hwc_index[i] + 1; |
993 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 994 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
995 | cpuhw->limited_hwidx[n_lim] = idx; |
996 | ++n_lim; | |
997 | continue; | |
998 | } | |
4574910e | 999 | val = 0; |
cdd6c482 | 1000 | if (event->hw.sample_period) { |
e7850595 | 1001 | left = local64_read(&event->hw.period_left); |
4574910e PM |
1002 | if (left < 0x80000000L) |
1003 | val = 0x80000000L - left; | |
1004 | } | |
e7850595 | 1005 | local64_set(&event->hw.prev_count, val); |
cdd6c482 | 1006 | event->hw.idx = idx; |
a4eaf7f1 PZ |
1007 | if (event->hw.state & PERF_HES_STOPPED) |
1008 | val = 0; | |
ab7ef2e5 | 1009 | write_pmc(idx, val); |
cdd6c482 | 1010 | perf_event_update_userpage(event); |
4574910e | 1011 | } |
ab7ef2e5 | 1012 | cpuhw->n_limited = n_lim; |
4574910e | 1013 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
1014 | |
1015 | out_enable: | |
1016 | mb(); | |
ab7ef2e5 | 1017 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1018 | |
f708223d PM |
1019 | /* |
1020 | * Enable instruction sampling if necessary | |
1021 | */ | |
1022 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1023 | mb(); | |
1024 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
1025 | } | |
1026 | ||
4574910e | 1027 | out: |
3925f46b AK |
1028 | if (cpuhw->bhrb_users) |
1029 | ppmu->config_bhrb(cpuhw->bhrb_filter); | |
1030 | ||
4574910e PM |
1031 | local_irq_restore(flags); |
1032 | } | |
1033 | ||
cdd6c482 IM |
1034 | static int collect_events(struct perf_event *group, int max_count, |
1035 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 1036 | unsigned int *flags) |
4574910e PM |
1037 | { |
1038 | int n = 0; | |
cdd6c482 | 1039 | struct perf_event *event; |
4574910e | 1040 | |
cdd6c482 | 1041 | if (!is_software_event(group)) { |
4574910e PM |
1042 | if (n >= max_count) |
1043 | return -1; | |
1044 | ctrs[n] = group; | |
cdd6c482 | 1045 | flags[n] = group->hw.event_base; |
4574910e PM |
1046 | events[n++] = group->hw.config; |
1047 | } | |
a8f90e90 | 1048 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
1049 | if (!is_software_event(event) && |
1050 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
1051 | if (n >= max_count) |
1052 | return -1; | |
cdd6c482 IM |
1053 | ctrs[n] = event; |
1054 | flags[n] = event->hw.event_base; | |
1055 | events[n++] = event->hw.config; | |
4574910e PM |
1056 | } |
1057 | } | |
1058 | return n; | |
1059 | } | |
1060 | ||
4574910e | 1061 | /* |
cdd6c482 IM |
1062 | * Add a event to the PMU. |
1063 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 1064 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
1065 | * actual work of reconfiguring the PMU. |
1066 | */ | |
a4eaf7f1 | 1067 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 1068 | { |
cdd6c482 | 1069 | struct cpu_hw_events *cpuhw; |
4574910e | 1070 | unsigned long flags; |
4574910e PM |
1071 | int n0; |
1072 | int ret = -EAGAIN; | |
1073 | ||
1074 | local_irq_save(flags); | |
33696fc0 | 1075 | perf_pmu_disable(event->pmu); |
4574910e PM |
1076 | |
1077 | /* | |
cdd6c482 | 1078 | * Add the event to the list (if there is room) |
4574910e PM |
1079 | * and check whether the total set is still feasible. |
1080 | */ | |
cdd6c482 IM |
1081 | cpuhw = &__get_cpu_var(cpu_hw_events); |
1082 | n0 = cpuhw->n_events; | |
a8f90e90 | 1083 | if (n0 >= ppmu->n_counter) |
4574910e | 1084 | goto out; |
cdd6c482 IM |
1085 | cpuhw->event[n0] = event; |
1086 | cpuhw->events[n0] = event->hw.config; | |
1087 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 1088 | |
f53d168c | 1089 | /* |
1090 | * This event may have been disabled/stopped in record_and_restart() | |
1091 | * because we exceeded the ->event_limit. If re-starting the event, | |
1092 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
1093 | * notification is re-enabled. | |
1094 | */ | |
a4eaf7f1 PZ |
1095 | if (!(ef_flags & PERF_EF_START)) |
1096 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 1097 | else |
1098 | event->hw.state = 0; | |
a4eaf7f1 | 1099 | |
8e6d5573 LM |
1100 | /* |
1101 | * If group events scheduling transaction was started, | |
25985edc | 1102 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
1103 | * at commit time(->commit_txn) as a whole |
1104 | */ | |
8d2cacbb | 1105 | if (cpuhw->group_flag & PERF_EVENT_TXN) |
8e6d5573 LM |
1106 | goto nocheck; |
1107 | ||
cdd6c482 | 1108 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 1109 | goto out; |
e51ee31e | 1110 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 1111 | goto out; |
cdd6c482 | 1112 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
1113 | |
1114 | nocheck: | |
cdd6c482 | 1115 | ++cpuhw->n_events; |
4574910e PM |
1116 | ++cpuhw->n_added; |
1117 | ||
1118 | ret = 0; | |
1119 | out: | |
3925f46b AK |
1120 | if (has_branch_stack(event)) |
1121 | power_pmu_bhrb_enable(event); | |
1122 | ||
33696fc0 | 1123 | perf_pmu_enable(event->pmu); |
4574910e PM |
1124 | local_irq_restore(flags); |
1125 | return ret; | |
1126 | } | |
1127 | ||
1128 | /* | |
cdd6c482 | 1129 | * Remove a event from the PMU. |
4574910e | 1130 | */ |
a4eaf7f1 | 1131 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 1132 | { |
cdd6c482 | 1133 | struct cpu_hw_events *cpuhw; |
4574910e | 1134 | long i; |
4574910e PM |
1135 | unsigned long flags; |
1136 | ||
1137 | local_irq_save(flags); | |
33696fc0 | 1138 | perf_pmu_disable(event->pmu); |
4574910e | 1139 | |
cdd6c482 IM |
1140 | power_pmu_read(event); |
1141 | ||
1142 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1143 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1144 | if (event == cpuhw->event[i]) { | |
219a92a4 | 1145 | while (++i < cpuhw->n_events) { |
cdd6c482 | 1146 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
1147 | cpuhw->events[i-1] = cpuhw->events[i]; |
1148 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
1149 | } | |
cdd6c482 IM |
1150 | --cpuhw->n_events; |
1151 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
1152 | if (event->hw.idx) { | |
1153 | write_pmc(event->hw.idx, 0); | |
1154 | event->hw.idx = 0; | |
ab7ef2e5 | 1155 | } |
cdd6c482 | 1156 | perf_event_update_userpage(event); |
4574910e PM |
1157 | break; |
1158 | } | |
1159 | } | |
ab7ef2e5 | 1160 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 1161 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
1162 | break; |
1163 | if (i < cpuhw->n_limited) { | |
1164 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 1165 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
1166 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
1167 | } | |
1168 | --cpuhw->n_limited; | |
1169 | } | |
cdd6c482 IM |
1170 | if (cpuhw->n_events == 0) { |
1171 | /* disable exceptions if no events are running */ | |
4574910e PM |
1172 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
1173 | } | |
1174 | ||
3925f46b AK |
1175 | if (has_branch_stack(event)) |
1176 | power_pmu_bhrb_disable(event); | |
1177 | ||
33696fc0 | 1178 | perf_pmu_enable(event->pmu); |
4574910e PM |
1179 | local_irq_restore(flags); |
1180 | } | |
1181 | ||
8a7b8cb9 | 1182 | /* |
a4eaf7f1 PZ |
1183 | * POWER-PMU does not support disabling individual counters, hence |
1184 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 1185 | */ |
a4eaf7f1 PZ |
1186 | |
1187 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 1188 | { |
8a7b8cb9 | 1189 | unsigned long flags; |
a4eaf7f1 | 1190 | s64 left; |
9a45a940 | 1191 | unsigned long val; |
8a7b8cb9 | 1192 | |
cdd6c482 | 1193 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 1194 | return; |
a4eaf7f1 PZ |
1195 | |
1196 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
1197 | return; | |
1198 | ||
1199 | if (ef_flags & PERF_EF_RELOAD) | |
1200 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1201 | ||
1202 | local_irq_save(flags); | |
1203 | perf_pmu_disable(event->pmu); | |
1204 | ||
1205 | event->hw.state = 0; | |
1206 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
1207 | |
1208 | val = 0; | |
1209 | if (left < 0x80000000L) | |
1210 | val = 0x80000000L - left; | |
1211 | ||
1212 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1213 | |
1214 | perf_event_update_userpage(event); | |
1215 | perf_pmu_enable(event->pmu); | |
1216 | local_irq_restore(flags); | |
1217 | } | |
1218 | ||
1219 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1220 | { | |
1221 | unsigned long flags; | |
1222 | ||
1223 | if (!event->hw.idx || !event->hw.sample_period) | |
1224 | return; | |
1225 | ||
1226 | if (event->hw.state & PERF_HES_STOPPED) | |
1227 | return; | |
1228 | ||
8a7b8cb9 | 1229 | local_irq_save(flags); |
33696fc0 | 1230 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1231 | |
cdd6c482 | 1232 | power_pmu_read(event); |
a4eaf7f1 PZ |
1233 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1234 | write_pmc(event->hw.idx, 0); | |
1235 | ||
cdd6c482 | 1236 | perf_event_update_userpage(event); |
33696fc0 | 1237 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1238 | local_irq_restore(flags); |
1239 | } | |
1240 | ||
8e6d5573 LM |
1241 | /* |
1242 | * Start group events scheduling transaction | |
1243 | * Set the flag to make pmu::enable() not perform the | |
1244 | * schedulability test, it will be performed at commit time | |
1245 | */ | |
51b0fe39 | 1246 | void power_pmu_start_txn(struct pmu *pmu) |
8e6d5573 LM |
1247 | { |
1248 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1249 | ||
33696fc0 | 1250 | perf_pmu_disable(pmu); |
8d2cacbb | 1251 | cpuhw->group_flag |= PERF_EVENT_TXN; |
8e6d5573 LM |
1252 | cpuhw->n_txn_start = cpuhw->n_events; |
1253 | } | |
1254 | ||
1255 | /* | |
1256 | * Stop group events scheduling transaction | |
1257 | * Clear the flag and pmu::enable() will perform the | |
1258 | * schedulability test. | |
1259 | */ | |
51b0fe39 | 1260 | void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 LM |
1261 | { |
1262 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1263 | ||
8d2cacbb | 1264 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1265 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1266 | } |
1267 | ||
1268 | /* | |
1269 | * Commit group events scheduling transaction | |
1270 | * Perform the group schedulability test as a whole | |
1271 | * Return 0 if success | |
1272 | */ | |
51b0fe39 | 1273 | int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1274 | { |
1275 | struct cpu_hw_events *cpuhw; | |
1276 | long i, n; | |
1277 | ||
1278 | if (!ppmu) | |
1279 | return -EAGAIN; | |
1280 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1281 | n = cpuhw->n_events; | |
1282 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1283 | return -EAGAIN; | |
1284 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1285 | if (i < 0) | |
1286 | return -EAGAIN; | |
1287 | ||
1288 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1289 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1290 | ||
8d2cacbb | 1291 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1292 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1293 | return 0; |
1294 | } | |
1295 | ||
ab7ef2e5 | 1296 | /* |
cdd6c482 | 1297 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1298 | * or 0 if not. |
cdd6c482 | 1299 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1300 | * that a limited PMC can count, doesn't require interrupts, and |
1301 | * doesn't exclude any processor mode. | |
1302 | */ | |
cdd6c482 | 1303 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1304 | unsigned int flags) |
1305 | { | |
1306 | int n; | |
ef923214 | 1307 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1308 | |
cdd6c482 IM |
1309 | if (event->attr.exclude_user |
1310 | || event->attr.exclude_kernel | |
1311 | || event->attr.exclude_hv | |
1312 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1313 | return 0; |
1314 | ||
1315 | if (ppmu->limited_pmc_event(ev)) | |
1316 | return 1; | |
1317 | ||
1318 | /* | |
cdd6c482 | 1319 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1320 | * see if any alternative code goes on a limited PMC. |
1321 | */ | |
1322 | if (!ppmu->get_alternatives) | |
1323 | return 0; | |
1324 | ||
1325 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1326 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1327 | |
ef923214 | 1328 | return n > 0; |
ab7ef2e5 PM |
1329 | } |
1330 | ||
1331 | /* | |
cdd6c482 IM |
1332 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1333 | * and return the event_id code, or 0 if there is no such alternative. | |
1334 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1335 | */ |
ef923214 | 1336 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1337 | { |
ef923214 | 1338 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1339 | int n; |
1340 | ||
1341 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1342 | n = ppmu->get_alternatives(ev, flags, alt); | |
1343 | if (!n) | |
1344 | return 0; | |
1345 | return alt[0]; | |
1346 | } | |
1347 | ||
cdd6c482 IM |
1348 | /* Number of perf_events counting hardware events */ |
1349 | static atomic_t num_events; | |
7595d63b PM |
1350 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1351 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1352 | ||
1353 | /* | |
cdd6c482 | 1354 | * Release the PMU if this is the last perf_event. |
7595d63b | 1355 | */ |
cdd6c482 | 1356 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1357 | { |
cdd6c482 | 1358 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1359 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1360 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1361 | release_pmc_hardware(); |
1362 | mutex_unlock(&pmc_reserve_mutex); | |
1363 | } | |
1364 | } | |
1365 | ||
106b506c | 1366 | /* |
cdd6c482 | 1367 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1368 | */ |
1369 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1370 | { | |
1371 | unsigned long type, op, result; | |
1372 | int ev; | |
1373 | ||
1374 | if (!ppmu->cache_events) | |
1375 | return -EINVAL; | |
1376 | ||
1377 | /* unpack config */ | |
1378 | type = config & 0xff; | |
1379 | op = (config >> 8) & 0xff; | |
1380 | result = (config >> 16) & 0xff; | |
1381 | ||
1382 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1383 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1384 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1385 | return -EINVAL; | |
1386 | ||
1387 | ev = (*ppmu->cache_events)[type][op][result]; | |
1388 | if (ev == 0) | |
1389 | return -EOPNOTSUPP; | |
1390 | if (ev == -1) | |
1391 | return -EINVAL; | |
1392 | *eventp = ev; | |
1393 | return 0; | |
1394 | } | |
1395 | ||
b0a873eb | 1396 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1397 | { |
ef923214 PM |
1398 | u64 ev; |
1399 | unsigned long flags; | |
cdd6c482 IM |
1400 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1401 | u64 events[MAX_HWEVENTS]; | |
1402 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1403 | int n; |
7595d63b | 1404 | int err; |
cdd6c482 | 1405 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1406 | |
1407 | if (!ppmu) | |
b0a873eb PZ |
1408 | return -ENOENT; |
1409 | ||
3925f46b AK |
1410 | if (has_branch_stack(event)) { |
1411 | /* PMU has BHRB enabled */ | |
1412 | if (!(ppmu->flags & PPMU_BHRB)) | |
1413 | return -EOPNOTSUPP; | |
1414 | } | |
2481c5fa | 1415 | |
cdd6c482 | 1416 | switch (event->attr.type) { |
106b506c | 1417 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1418 | ev = event->attr.config; |
9aaa131a | 1419 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1420 | return -EOPNOTSUPP; |
4574910e | 1421 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1422 | break; |
1423 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1424 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1425 | if (err) |
b0a873eb | 1426 | return err; |
106b506c PM |
1427 | break; |
1428 | case PERF_TYPE_RAW: | |
cdd6c482 | 1429 | ev = event->attr.config; |
106b506c | 1430 | break; |
90c8f954 | 1431 | default: |
b0a873eb | 1432 | return -ENOENT; |
4574910e | 1433 | } |
b0a873eb | 1434 | |
cdd6c482 IM |
1435 | event->hw.config_base = ev; |
1436 | event->hw.idx = 0; | |
4574910e | 1437 | |
0475f9ea PM |
1438 | /* |
1439 | * If we are not running on a hypervisor, force the | |
1440 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1441 | * the user set it to. |
0475f9ea PM |
1442 | */ |
1443 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1444 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1445 | |
1446 | /* | |
cdd6c482 | 1447 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1448 | * PM_RUN_* events interchangeably with their non RUN_* |
1449 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1450 | * XXX we should check if the task is an idle task. | |
1451 | */ | |
1452 | flags = 0; | |
57fa7214 | 1453 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1454 | flags |= PPMU_ONLY_COUNT_RUN; |
1455 | ||
1456 | /* | |
cdd6c482 IM |
1457 | * If this machine has limited events, check whether this |
1458 | * event_id could go on a limited event. | |
ab7ef2e5 | 1459 | */ |
0bbd0d4b | 1460 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1461 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1462 | flags |= PPMU_LIMITED_PMC_OK; |
1463 | } else if (ppmu->limited_pmc_event(ev)) { | |
1464 | /* | |
cdd6c482 | 1465 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1466 | * but we can't use a limited PMC; see if any |
1467 | * alternative goes on a normal PMC. | |
1468 | */ | |
1469 | ev = normal_pmc_alternative(ev, flags); | |
1470 | if (!ev) | |
b0a873eb | 1471 | return -EINVAL; |
ab7ef2e5 PM |
1472 | } |
1473 | } | |
1474 | ||
4574910e PM |
1475 | /* |
1476 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1477 | * other hardware events in the group. We assume the event |
4574910e PM |
1478 | * hasn't been linked into its leader's sibling list at this point. |
1479 | */ | |
1480 | n = 0; | |
cdd6c482 | 1481 | if (event->group_leader != event) { |
a8f90e90 | 1482 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1483 | ctrs, events, cflags); |
4574910e | 1484 | if (n < 0) |
b0a873eb | 1485 | return -EINVAL; |
4574910e | 1486 | } |
0475f9ea | 1487 | events[n] = ev; |
cdd6c482 | 1488 | ctrs[n] = event; |
ab7ef2e5 PM |
1489 | cflags[n] = flags; |
1490 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1491 | return -EINVAL; |
e51ee31e | 1492 | |
cdd6c482 | 1493 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1494 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
3925f46b AK |
1495 | |
1496 | if (has_branch_stack(event)) { | |
1497 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( | |
1498 | event->attr.branch_sample_type); | |
1499 | ||
1500 | if(cpuhw->bhrb_filter == -1) | |
1501 | return -EOPNOTSUPP; | |
1502 | } | |
1503 | ||
cdd6c482 | 1504 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1505 | if (err) |
b0a873eb | 1506 | return -EINVAL; |
4574910e | 1507 | |
cdd6c482 IM |
1508 | event->hw.config = events[n]; |
1509 | event->hw.event_base = cflags[n]; | |
1510 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1511 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b PM |
1512 | |
1513 | /* | |
1514 | * See if we need to reserve the PMU. | |
cdd6c482 | 1515 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1516 | * mutex to ensure that we don't race with another task doing |
1517 | * reserve_pmc_hardware or release_pmc_hardware. | |
1518 | */ | |
1519 | err = 0; | |
cdd6c482 | 1520 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1521 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1522 | if (atomic_read(&num_events) == 0 && |
1523 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1524 | err = -EBUSY; |
1525 | else | |
cdd6c482 | 1526 | atomic_inc(&num_events); |
7595d63b PM |
1527 | mutex_unlock(&pmc_reserve_mutex); |
1528 | } | |
cdd6c482 | 1529 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1530 | |
b0a873eb | 1531 | return err; |
4574910e PM |
1532 | } |
1533 | ||
35edc2a5 PZ |
1534 | static int power_pmu_event_idx(struct perf_event *event) |
1535 | { | |
1536 | return event->hw.idx; | |
1537 | } | |
1538 | ||
1c53a270 SB |
1539 | ssize_t power_events_sysfs_show(struct device *dev, |
1540 | struct device_attribute *attr, char *page) | |
1541 | { | |
1542 | struct perf_pmu_events_attr *pmu_attr; | |
1543 | ||
1544 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
1545 | ||
1546 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
1547 | } | |
1548 | ||
b0a873eb | 1549 | struct pmu power_pmu = { |
a4eaf7f1 PZ |
1550 | .pmu_enable = power_pmu_enable, |
1551 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1552 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1553 | .add = power_pmu_add, |
1554 | .del = power_pmu_del, | |
1555 | .start = power_pmu_start, | |
1556 | .stop = power_pmu_stop, | |
b0a873eb | 1557 | .read = power_pmu_read, |
b0a873eb PZ |
1558 | .start_txn = power_pmu_start_txn, |
1559 | .cancel_txn = power_pmu_cancel_txn, | |
1560 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1561 | .event_idx = power_pmu_event_idx, |
3925f46b | 1562 | .flush_branch_stack = power_pmu_flush_branch_stack, |
b0a873eb PZ |
1563 | }; |
1564 | ||
4574910e | 1565 | /* |
57c0c15b | 1566 | * A counter has overflowed; update its count and record |
4574910e PM |
1567 | * things if requested. Note that interrupts are hard-disabled |
1568 | * here so there is no possibility of being interrupted. | |
1569 | */ | |
cdd6c482 | 1570 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1571 | struct pt_regs *regs) |
4574910e | 1572 | { |
cdd6c482 | 1573 | u64 period = event->hw.sample_period; |
4574910e PM |
1574 | s64 prev, delta, left; |
1575 | int record = 0; | |
1576 | ||
a4eaf7f1 PZ |
1577 | if (event->hw.state & PERF_HES_STOPPED) { |
1578 | write_pmc(event->hw.idx, 0); | |
1579 | return; | |
1580 | } | |
1581 | ||
4574910e | 1582 | /* we don't have to worry about interrupts here */ |
e7850595 | 1583 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 1584 | delta = check_and_compute_delta(prev, val); |
e7850595 | 1585 | local64_add(delta, &event->count); |
4574910e PM |
1586 | |
1587 | /* | |
cdd6c482 | 1588 | * See if the total period for this event has expired, |
4574910e PM |
1589 | * and update for the next period. |
1590 | */ | |
1591 | val = 0; | |
e7850595 | 1592 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
1593 | if (delta == 0) |
1594 | left++; | |
60db5e09 | 1595 | if (period) { |
4574910e | 1596 | if (left <= 0) { |
60db5e09 | 1597 | left += period; |
4574910e | 1598 | if (left <= 0) |
60db5e09 | 1599 | left = period; |
e6878835 | 1600 | record = siar_valid(regs); |
4bca770e | 1601 | event->hw.last_period = event->hw.sample_period; |
4574910e | 1602 | } |
98fb1807 PM |
1603 | if (left < 0x80000000LL) |
1604 | val = 0x80000000LL - left; | |
4574910e | 1605 | } |
4574910e | 1606 | |
a4eaf7f1 PZ |
1607 | write_pmc(event->hw.idx, val); |
1608 | local64_set(&event->hw.prev_count, val); | |
1609 | local64_set(&event->hw.period_left, left); | |
1610 | perf_event_update_userpage(event); | |
1611 | ||
4574910e PM |
1612 | /* |
1613 | * Finally record data if requested. | |
1614 | */ | |
0bbd0d4b | 1615 | if (record) { |
dc1d628a PZ |
1616 | struct perf_sample_data data; |
1617 | ||
fd0d000b | 1618 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 1619 | |
cdd6c482 | 1620 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
1621 | perf_get_data_addr(regs, &data.addr); |
1622 | ||
3925f46b AK |
1623 | if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { |
1624 | struct cpu_hw_events *cpuhw; | |
1625 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1626 | power_pmu_bhrb_read(cpuhw); | |
1627 | data.br_stack = &cpuhw->bhrb_stack; | |
1628 | } | |
1629 | ||
a8b0ca17 | 1630 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1631 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
1632 | } |
1633 | } | |
1634 | ||
1635 | /* | |
1636 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 1637 | * for an event_id. |
0bbd0d4b PM |
1638 | */ |
1639 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1640 | { | |
98fb1807 | 1641 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 1642 | |
98fb1807 PM |
1643 | if (flags) |
1644 | return flags; | |
cdd6c482 IM |
1645 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
1646 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
1647 | } |
1648 | ||
1649 | /* | |
1650 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 1651 | * for an event_id. |
0bbd0d4b PM |
1652 | */ |
1653 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1654 | { | |
33904054 | 1655 | bool use_siar = regs_use_siar(regs); |
0bbd0d4b | 1656 | |
e6878835 | 1657 | if (use_siar && siar_valid(regs)) |
75382aa7 | 1658 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 1659 | else if (use_siar) |
1660 | return 0; // no valid instruction pointer | |
75382aa7 | 1661 | else |
1ce447b9 | 1662 | return regs->nip; |
4574910e PM |
1663 | } |
1664 | ||
bc09c219 | 1665 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 1666 | { |
0837e324 AB |
1667 | /* |
1668 | * Events on POWER7 can roll back if a speculative event doesn't | |
1669 | * eventually complete. Unfortunately in some rare cases they will | |
1670 | * raise a performance monitor exception. We need to catch this to | |
1671 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
1672 | * cycles from overflow. | |
1673 | * | |
1674 | * We only do this if the first pass fails to find any overflowing | |
1675 | * PMCs because a user might set a period of less than 256 and we | |
1676 | * don't want to mistakenly reset them. | |
1677 | */ | |
bc09c219 MN |
1678 | if ((0x80000000 - val) <= 256) |
1679 | return true; | |
1680 | ||
1681 | return false; | |
1682 | } | |
1683 | ||
1684 | static bool pmc_overflow(unsigned long val) | |
1685 | { | |
1686 | if ((int)val < 0) | |
0837e324 AB |
1687 | return true; |
1688 | ||
1689 | return false; | |
1690 | } | |
1691 | ||
4574910e PM |
1692 | /* |
1693 | * Performance monitor interrupt stuff | |
1694 | */ | |
cdd6c482 | 1695 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 1696 | { |
bc09c219 | 1697 | int i, j; |
cdd6c482 IM |
1698 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); |
1699 | struct perf_event *event; | |
bc09c219 MN |
1700 | unsigned long val[8]; |
1701 | int found, active; | |
ca8f2d7f PM |
1702 | int nmi; |
1703 | ||
ab7ef2e5 | 1704 | if (cpuhw->n_limited) |
a8f90e90 | 1705 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
1706 | mfspr(SPRN_PMC6)); |
1707 | ||
98fb1807 | 1708 | perf_read_regs(regs); |
0bbd0d4b | 1709 | |
98fb1807 | 1710 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
1711 | if (nmi) |
1712 | nmi_enter(); | |
1713 | else | |
1714 | irq_enter(); | |
4574910e | 1715 | |
bc09c219 MN |
1716 | /* Read all the PMCs since we'll need them a bunch of times */ |
1717 | for (i = 0; i < ppmu->n_counter; ++i) | |
1718 | val[i] = read_pmc(i + 1); | |
1719 | ||
1720 | /* Try to find what caused the IRQ */ | |
1721 | found = 0; | |
1722 | for (i = 0; i < ppmu->n_counter; ++i) { | |
1723 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 1724 | continue; |
bc09c219 MN |
1725 | if (is_limited_pmc(i + 1)) |
1726 | continue; /* these won't generate IRQs */ | |
1727 | /* | |
1728 | * We've found one that's overflowed. For active | |
1729 | * counters we need to log this. For inactive | |
1730 | * counters, we need to reset it anyway | |
1731 | */ | |
1732 | found = 1; | |
1733 | active = 0; | |
1734 | for (j = 0; j < cpuhw->n_events; ++j) { | |
1735 | event = cpuhw->event[j]; | |
1736 | if (event->hw.idx == (i + 1)) { | |
1737 | active = 1; | |
1738 | record_and_restart(event, val[i], regs); | |
1739 | break; | |
1740 | } | |
4574910e | 1741 | } |
bc09c219 MN |
1742 | if (!active) |
1743 | /* reset non active counters that have overflowed */ | |
1744 | write_pmc(i + 1, 0); | |
4574910e | 1745 | } |
bc09c219 MN |
1746 | if (!found && pvr_version_is(PVR_POWER7)) { |
1747 | /* check active counters for special buggy p7 overflow */ | |
1748 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1749 | event = cpuhw->event[i]; | |
1750 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 1751 | continue; |
bc09c219 MN |
1752 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
1753 | /* event has overflowed in a buggy way*/ | |
1754 | found = 1; | |
1755 | record_and_restart(event, | |
1756 | val[event->hw.idx - 1], | |
1757 | regs); | |
1758 | } | |
4574910e PM |
1759 | } |
1760 | } | |
6772faa1 | 1761 | if (!found && !nmi && printk_ratelimit()) |
bc09c219 | 1762 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); |
4574910e PM |
1763 | |
1764 | /* | |
1765 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 1766 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 1767 | * and thus allow interrupts to occur again. |
cdd6c482 | 1768 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
1769 | * we get back out of this interrupt. |
1770 | */ | |
ab7ef2e5 | 1771 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1772 | |
ca8f2d7f PM |
1773 | if (nmi) |
1774 | nmi_exit(); | |
1775 | else | |
db4fb5ac | 1776 | irq_exit(); |
4574910e PM |
1777 | } |
1778 | ||
3f6da390 | 1779 | static void power_pmu_setup(int cpu) |
01d0287f | 1780 | { |
cdd6c482 | 1781 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 1782 | |
f36a1a13 PM |
1783 | if (!ppmu) |
1784 | return; | |
01d0287f PM |
1785 | memset(cpuhw, 0, sizeof(*cpuhw)); |
1786 | cpuhw->mmcr[0] = MMCR0_FC; | |
1787 | } | |
1788 | ||
061d19f2 | 1789 | static int |
85cfabbc | 1790 | power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
3f6da390 PZ |
1791 | { |
1792 | unsigned int cpu = (long)hcpu; | |
1793 | ||
1794 | switch (action & ~CPU_TASKS_FROZEN) { | |
1795 | case CPU_UP_PREPARE: | |
1796 | power_pmu_setup(cpu); | |
1797 | break; | |
1798 | ||
1799 | default: | |
1800 | break; | |
1801 | } | |
1802 | ||
1803 | return NOTIFY_OK; | |
1804 | } | |
1805 | ||
061d19f2 | 1806 | int register_power_pmu(struct power_pmu *pmu) |
4574910e | 1807 | { |
079b3c56 PM |
1808 | if (ppmu) |
1809 | return -EBUSY; /* something's already registered */ | |
1810 | ||
1811 | ppmu = pmu; | |
1812 | pr_info("%s performance monitor hardware support registered\n", | |
1813 | pmu->name); | |
d095cd46 | 1814 | |
1c53a270 SB |
1815 | power_pmu.attr_groups = ppmu->attr_groups; |
1816 | ||
98fb1807 | 1817 | #ifdef MSR_HV |
d095cd46 PM |
1818 | /* |
1819 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
1820 | */ | |
1821 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 1822 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 1823 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 1824 | |
2e80a82a | 1825 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 PZ |
1826 | perf_cpu_notifier(power_pmu_notifier); |
1827 | ||
4574910e PM |
1828 | return 0; |
1829 | } |