Commit | Line | Data |
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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
69123184 | 16 | #include <linux/uaccess.h> |
4574910e PM |
17 | #include <asm/reg.h> |
18 | #include <asm/pmc.h> | |
01d0287f | 19 | #include <asm/machdep.h> |
0475f9ea | 20 | #include <asm/firmware.h> |
0bbd0d4b | 21 | #include <asm/ptrace.h> |
69123184 | 22 | #include <asm/code-patching.h> |
4574910e | 23 | |
3925f46b AK |
24 | #define BHRB_MAX_ENTRIES 32 |
25 | #define BHRB_TARGET 0x0000000000000002 | |
26 | #define BHRB_PREDICTION 0x0000000000000001 | |
b0d436c7 | 27 | #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL |
3925f46b | 28 | |
cdd6c482 IM |
29 | struct cpu_hw_events { |
30 | int n_events; | |
4574910e PM |
31 | int n_percpu; |
32 | int disabled; | |
33 | int n_added; | |
ab7ef2e5 PM |
34 | int n_limited; |
35 | u8 pmcs_enabled; | |
cdd6c482 IM |
36 | struct perf_event *event[MAX_HWEVENTS]; |
37 | u64 events[MAX_HWEVENTS]; | |
38 | unsigned int flags[MAX_HWEVENTS]; | |
9de5cb0f ME |
39 | /* |
40 | * The order of the MMCR array is: | |
41 | * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2 | |
42 | * - 32-bit, MMCR0, MMCR1, MMCR2 | |
43 | */ | |
44 | unsigned long mmcr[4]; | |
a8f90e90 PM |
45 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
46 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
47 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
48 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
49 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 | 50 | |
fbbe0701 | 51 | unsigned int txn_flags; |
8e6d5573 | 52 | int n_txn_start; |
3925f46b AK |
53 | |
54 | /* BHRB bits */ | |
55 | u64 bhrb_filter; /* BHRB HW branch filter */ | |
f0322f7f | 56 | unsigned int bhrb_users; |
3925f46b AK |
57 | void *bhrb_context; |
58 | struct perf_branch_stack bhrb_stack; | |
59 | struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; | |
4574910e | 60 | }; |
3925f46b | 61 | |
e51df2c1 | 62 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e | 63 | |
e51df2c1 | 64 | static struct power_pmu *ppmu; |
4574910e | 65 | |
d095cd46 | 66 | /* |
57c0c15b | 67 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
68 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
69 | * hypervisor bit set in the MSR, or if we are running on a processor | |
70 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
71 | * then we need to use the FCHV bit to ignore kernel events. | |
72 | */ | |
cdd6c482 | 73 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 74 | |
98fb1807 PM |
75 | /* |
76 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
77 | * and a few other names are different. | |
78 | */ | |
79 | #ifdef CONFIG_PPC32 | |
80 | ||
81 | #define MMCR0_FCHV 0 | |
82 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
7a7a41f9 | 83 | #define MMCR0_FC56 0 |
378a6ee9 | 84 | #define MMCR0_PMAO 0 |
330a1eb7 | 85 | #define MMCR0_EBE 0 |
76cb8a78 | 86 | #define MMCR0_BHRBA 0 |
330a1eb7 ME |
87 | #define MMCR0_PMCC 0 |
88 | #define MMCR0_PMCC_U6 0 | |
98fb1807 PM |
89 | |
90 | #define SPRN_MMCRA SPRN_MMCR2 | |
91 | #define MMCRA_SAMPLE_ENABLE 0 | |
92 | ||
93 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
94 | { | |
95 | return 0; | |
96 | } | |
98fb1807 PM |
97 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
98 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
99 | { | |
100 | return 0; | |
101 | } | |
75382aa7 AB |
102 | static inline void perf_read_regs(struct pt_regs *regs) |
103 | { | |
104 | regs->result = 0; | |
105 | } | |
98fb1807 PM |
106 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
107 | { | |
108 | return 0; | |
109 | } | |
110 | ||
e6878835 | 111 | static inline int siar_valid(struct pt_regs *regs) |
112 | { | |
113 | return 1; | |
114 | } | |
115 | ||
330a1eb7 ME |
116 | static bool is_ebb_event(struct perf_event *event) { return false; } |
117 | static int ebb_event_check(struct perf_event *event) { return 0; } | |
118 | static void ebb_event_add(struct perf_event *event) { } | |
119 | static void ebb_switch_out(unsigned long mmcr0) { } | |
9de5cb0f | 120 | static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) |
330a1eb7 | 121 | { |
9de5cb0f | 122 | return cpuhw->mmcr[0]; |
330a1eb7 ME |
123 | } |
124 | ||
d52f2dc4 MN |
125 | static inline void power_pmu_bhrb_enable(struct perf_event *event) {} |
126 | static inline void power_pmu_bhrb_disable(struct perf_event *event) {} | |
acba3c7e | 127 | static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} |
d52f2dc4 | 128 | static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} |
c2e37a26 | 129 | static void pmao_restore_workaround(bool ebb) { } |
98fb1807 PM |
130 | #endif /* CONFIG_PPC32 */ |
131 | ||
33904054 ME |
132 | static bool regs_use_siar(struct pt_regs *regs) |
133 | { | |
72e349f1 AB |
134 | /* |
135 | * When we take a performance monitor exception the regs are setup | |
136 | * using perf_read_regs() which overloads some fields, in particular | |
137 | * regs->result to tell us whether to use SIAR. | |
138 | * | |
139 | * However if the regs are from another exception, eg. a syscall, then | |
140 | * they have not been setup using perf_read_regs() and so regs->result | |
141 | * is something random. | |
142 | */ | |
143 | return ((TRAP(regs) == 0xf00) && regs->result); | |
33904054 ME |
144 | } |
145 | ||
98fb1807 PM |
146 | /* |
147 | * Things that are specific to 64-bit implementations. | |
148 | */ | |
149 | #ifdef CONFIG_PPC64 | |
150 | ||
151 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
152 | { | |
153 | unsigned long mmcra = regs->dsisr; | |
154 | ||
7a786832 | 155 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
156 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
157 | if (slot > 1) | |
158 | return 4 * (slot - 1); | |
159 | } | |
7a786832 | 160 | |
98fb1807 PM |
161 | return 0; |
162 | } | |
163 | ||
98fb1807 PM |
164 | /* |
165 | * The user wants a data address recorded. | |
166 | * If we're not doing instruction sampling, give them the SDAR | |
167 | * (sampled data address). If we are doing instruction sampling, then | |
168 | * only give them the SDAR if it corresponds to the instruction | |
58a032c3 ME |
169 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the |
170 | * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. | |
98fb1807 PM |
171 | */ |
172 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
173 | { | |
174 | unsigned long mmcra = regs->dsisr; | |
58a032c3 | 175 | bool sdar_valid; |
e6878835 | 176 | |
58a032c3 ME |
177 | if (ppmu->flags & PPMU_HAS_SIER) |
178 | sdar_valid = regs->dar & SIER_SDAR_VALID; | |
179 | else { | |
180 | unsigned long sdsync; | |
181 | ||
182 | if (ppmu->flags & PPMU_SIAR_VALID) | |
183 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
184 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
185 | sdsync = POWER6_MMCRA_SDSYNC; | |
186 | else | |
187 | sdsync = MMCRA_SDSYNC; | |
188 | ||
189 | sdar_valid = mmcra & sdsync; | |
190 | } | |
98fb1807 | 191 | |
58a032c3 | 192 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) |
98fb1807 PM |
193 | *addrp = mfspr(SPRN_SDAR); |
194 | } | |
195 | ||
5682c460 | 196 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
197 | { |
198 | unsigned long sihv = MMCRA_SIHV; | |
199 | ||
8f61aa32 ME |
200 | if (ppmu->flags & PPMU_HAS_SIER) |
201 | return !!(regs->dar & SIER_SIHV); | |
202 | ||
68b30bb9 AB |
203 | if (ppmu->flags & PPMU_ALT_SIPR) |
204 | sihv = POWER6_MMCRA_SIHV; | |
205 | ||
5682c460 | 206 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
207 | } |
208 | ||
5682c460 | 209 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
210 | { |
211 | unsigned long sipr = MMCRA_SIPR; | |
212 | ||
8f61aa32 ME |
213 | if (ppmu->flags & PPMU_HAS_SIER) |
214 | return !!(regs->dar & SIER_SIPR); | |
215 | ||
68b30bb9 AB |
216 | if (ppmu->flags & PPMU_ALT_SIPR) |
217 | sipr = POWER6_MMCRA_SIPR; | |
218 | ||
5682c460 | 219 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
220 | } |
221 | ||
1ce447b9 BH |
222 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
223 | { | |
224 | if (regs->msr & MSR_PR) | |
225 | return PERF_RECORD_MISC_USER; | |
226 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
227 | return PERF_RECORD_MISC_HYPERVISOR; | |
228 | return PERF_RECORD_MISC_KERNEL; | |
229 | } | |
230 | ||
98fb1807 PM |
231 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
232 | { | |
33904054 | 233 | bool use_siar = regs_use_siar(regs); |
98fb1807 | 234 | |
75382aa7 | 235 | if (!use_siar) |
1ce447b9 BH |
236 | return perf_flags_from_msr(regs); |
237 | ||
238 | /* | |
239 | * If we don't have flags in MMCRA, rather than using | |
240 | * the MSR, we intuit the flags from the address in | |
241 | * SIAR which should give slightly more reliable | |
242 | * results | |
243 | */ | |
cbda6aa1 | 244 | if (ppmu->flags & PPMU_NO_SIPR) { |
1ce447b9 BH |
245 | unsigned long siar = mfspr(SPRN_SIAR); |
246 | if (siar >= PAGE_OFFSET) | |
247 | return PERF_RECORD_MISC_KERNEL; | |
248 | return PERF_RECORD_MISC_USER; | |
249 | } | |
98fb1807 | 250 | |
7abb840b | 251 | /* PR has priority over HV, so order below is important */ |
5682c460 | 252 | if (regs_sipr(regs)) |
7abb840b | 253 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
254 | |
255 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 256 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 257 | |
7abb840b | 258 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
259 | } |
260 | ||
261 | /* | |
262 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
263 | * on each interrupt. | |
8f61aa32 | 264 | * Overload regs->dar to store SIER if we have it. |
75382aa7 AB |
265 | * Overload regs->result to specify whether we should use the MSR (result |
266 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
267 | */ |
268 | static inline void perf_read_regs(struct pt_regs *regs) | |
269 | { | |
75382aa7 AB |
270 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
271 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
272 | int use_siar; | |
273 | ||
5682c460 | 274 | regs->dsisr = mmcra; |
8f61aa32 | 275 | |
cbda6aa1 ME |
276 | if (ppmu->flags & PPMU_HAS_SIER) |
277 | regs->dar = mfspr(SPRN_SIER); | |
8f61aa32 | 278 | |
5c093efa AB |
279 | /* |
280 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
281 | * not valid. Use pt_regs. | |
282 | * | |
283 | * If it is a marked event use the SIAR. | |
284 | * | |
285 | * If the PMU doesn't update the SIAR for non marked events use | |
286 | * pt_regs. | |
287 | * | |
288 | * If the PMU has HV/PR flags then check to see if they | |
289 | * place the exception in userspace. If so, use pt_regs. In | |
290 | * continuous sampling mode the SIAR and the PMU exception are | |
291 | * not synchronised, so they may be many instructions apart. | |
292 | * This can result in confusing backtraces. We still want | |
293 | * hypervisor samples as well as samples in the kernel with | |
294 | * interrupts off hence the userspace check. | |
295 | */ | |
75382aa7 AB |
296 | if (TRAP(regs) != 0xf00) |
297 | use_siar = 0; | |
5c093efa AB |
298 | else if (marked) |
299 | use_siar = 1; | |
300 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
301 | use_siar = 0; | |
cbda6aa1 | 302 | else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) |
75382aa7 AB |
303 | use_siar = 0; |
304 | else | |
305 | use_siar = 1; | |
306 | ||
cbda6aa1 | 307 | regs->result = use_siar; |
98fb1807 PM |
308 | } |
309 | ||
310 | /* | |
311 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
312 | * it as an NMI. | |
313 | */ | |
314 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
315 | { | |
316 | return !regs->softe; | |
317 | } | |
318 | ||
e6878835 | 319 | /* |
320 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
321 | * must be sampled only if the SIAR-valid bit is set. | |
322 | * | |
323 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
324 | * bit, assume that SIAR is valid. | |
325 | */ | |
326 | static inline int siar_valid(struct pt_regs *regs) | |
327 | { | |
328 | unsigned long mmcra = regs->dsisr; | |
329 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
330 | ||
58a032c3 ME |
331 | if (marked) { |
332 | if (ppmu->flags & PPMU_HAS_SIER) | |
333 | return regs->dar & SIER_SIAR_VALID; | |
334 | ||
335 | if (ppmu->flags & PPMU_SIAR_VALID) | |
336 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
337 | } | |
e6878835 | 338 | |
339 | return 1; | |
340 | } | |
341 | ||
d52f2dc4 MN |
342 | |
343 | /* Reset all possible BHRB entries */ | |
344 | static void power_pmu_bhrb_reset(void) | |
345 | { | |
346 | asm volatile(PPC_CLRBHRB); | |
347 | } | |
348 | ||
349 | static void power_pmu_bhrb_enable(struct perf_event *event) | |
350 | { | |
69111bac | 351 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
d52f2dc4 MN |
352 | |
353 | if (!ppmu->bhrb_nr) | |
354 | return; | |
355 | ||
356 | /* Clear BHRB if we changed task context to avoid data leaks */ | |
357 | if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { | |
358 | power_pmu_bhrb_reset(); | |
359 | cpuhw->bhrb_context = event->ctx; | |
360 | } | |
361 | cpuhw->bhrb_users++; | |
acba3c7e | 362 | perf_sched_cb_inc(event->ctx->pmu); |
d52f2dc4 MN |
363 | } |
364 | ||
365 | static void power_pmu_bhrb_disable(struct perf_event *event) | |
366 | { | |
69111bac | 367 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
d52f2dc4 MN |
368 | |
369 | if (!ppmu->bhrb_nr) | |
370 | return; | |
371 | ||
f0322f7f | 372 | WARN_ON_ONCE(!cpuhw->bhrb_users); |
d52f2dc4 | 373 | cpuhw->bhrb_users--; |
acba3c7e | 374 | perf_sched_cb_dec(event->ctx->pmu); |
d52f2dc4 MN |
375 | |
376 | if (!cpuhw->disabled && !cpuhw->bhrb_users) { | |
377 | /* BHRB cannot be turned off when other | |
378 | * events are active on the PMU. | |
379 | */ | |
380 | ||
381 | /* avoid stale pointer */ | |
382 | cpuhw->bhrb_context = NULL; | |
383 | } | |
384 | } | |
385 | ||
386 | /* Called from ctxsw to prevent one process's branch entries to | |
387 | * mingle with the other process's entries during context switch. | |
388 | */ | |
acba3c7e | 389 | static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) |
d52f2dc4 | 390 | { |
acba3c7e PZ |
391 | if (!ppmu->bhrb_nr) |
392 | return; | |
393 | ||
394 | if (sched_in) | |
d52f2dc4 MN |
395 | power_pmu_bhrb_reset(); |
396 | } | |
69123184 MN |
397 | /* Calculate the to address for a branch */ |
398 | static __u64 power_pmu_bhrb_to(u64 addr) | |
399 | { | |
400 | unsigned int instr; | |
401 | int ret; | |
402 | __u64 target; | |
403 | ||
404 | if (is_kernel_addr(addr)) | |
405 | return branch_target((unsigned int *)addr); | |
406 | ||
407 | /* Userspace: need copy instruction here then translate it */ | |
408 | pagefault_disable(); | |
409 | ret = __get_user_inatomic(instr, (unsigned int __user *)addr); | |
410 | if (ret) { | |
411 | pagefault_enable(); | |
412 | return 0; | |
413 | } | |
414 | pagefault_enable(); | |
415 | ||
416 | target = branch_target(&instr); | |
417 | if ((!target) || (instr & BRANCH_ABSOLUTE)) | |
418 | return target; | |
419 | ||
420 | /* Translate relative branch target from kernel to user address */ | |
421 | return target - (unsigned long)&instr + addr; | |
422 | } | |
d52f2dc4 | 423 | |
d52f2dc4 | 424 | /* Processing BHRB entries */ |
e51df2c1 | 425 | static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) |
d52f2dc4 MN |
426 | { |
427 | u64 val; | |
428 | u64 addr; | |
506e70d1 | 429 | int r_index, u_index, pred; |
d52f2dc4 MN |
430 | |
431 | r_index = 0; | |
432 | u_index = 0; | |
433 | while (r_index < ppmu->bhrb_nr) { | |
434 | /* Assembly read function */ | |
506e70d1 MN |
435 | val = read_bhrb(r_index++); |
436 | if (!val) | |
437 | /* Terminal marker: End of valid BHRB entries */ | |
d52f2dc4 | 438 | break; |
506e70d1 | 439 | else { |
d52f2dc4 MN |
440 | addr = val & BHRB_EA; |
441 | pred = val & BHRB_PREDICTION; | |
d52f2dc4 | 442 | |
506e70d1 MN |
443 | if (!addr) |
444 | /* invalid entry */ | |
d52f2dc4 | 445 | continue; |
d52f2dc4 | 446 | |
506e70d1 MN |
447 | /* Branches are read most recent first (ie. mfbhrb 0 is |
448 | * the most recent branch). | |
449 | * There are two types of valid entries: | |
450 | * 1) a target entry which is the to address of a | |
451 | * computed goto like a blr,bctr,btar. The next | |
452 | * entry read from the bhrb will be branch | |
453 | * corresponding to this target (ie. the actual | |
454 | * blr/bctr/btar instruction). | |
455 | * 2) a from address which is an actual branch. If a | |
456 | * target entry proceeds this, then this is the | |
457 | * matching branch for that target. If this is not | |
458 | * following a target entry, then this is a branch | |
459 | * where the target is given as an immediate field | |
460 | * in the instruction (ie. an i or b form branch). | |
461 | * In this case we need to read the instruction from | |
462 | * memory to determine the target/to address. | |
463 | */ | |
d52f2dc4 | 464 | |
d52f2dc4 | 465 | if (val & BHRB_TARGET) { |
506e70d1 MN |
466 | /* Target branches use two entries |
467 | * (ie. computed gotos/XL form) | |
468 | */ | |
469 | cpuhw->bhrb_entries[u_index].to = addr; | |
470 | cpuhw->bhrb_entries[u_index].mispred = pred; | |
471 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 472 | |
506e70d1 MN |
473 | /* Get from address in next entry */ |
474 | val = read_bhrb(r_index++); | |
475 | addr = val & BHRB_EA; | |
476 | if (val & BHRB_TARGET) { | |
477 | /* Shouldn't have two targets in a | |
478 | row.. Reset index and try again */ | |
479 | r_index--; | |
480 | addr = 0; | |
481 | } | |
482 | cpuhw->bhrb_entries[u_index].from = addr; | |
d52f2dc4 | 483 | } else { |
506e70d1 MN |
484 | /* Branches to immediate field |
485 | (ie I or B form) */ | |
d52f2dc4 | 486 | cpuhw->bhrb_entries[u_index].from = addr; |
69123184 MN |
487 | cpuhw->bhrb_entries[u_index].to = |
488 | power_pmu_bhrb_to(addr); | |
d52f2dc4 MN |
489 | cpuhw->bhrb_entries[u_index].mispred = pred; |
490 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 491 | } |
506e70d1 MN |
492 | u_index++; |
493 | ||
d52f2dc4 MN |
494 | } |
495 | } | |
496 | cpuhw->bhrb_stack.nr = u_index; | |
497 | return; | |
498 | } | |
499 | ||
330a1eb7 ME |
500 | static bool is_ebb_event(struct perf_event *event) |
501 | { | |
502 | /* | |
503 | * This could be a per-PMU callback, but we'd rather avoid the cost. We | |
504 | * check that the PMU supports EBB, meaning those that don't can still | |
505 | * use bit 63 of the event code for something else if they wish. | |
506 | */ | |
4d9690dd | 507 | return (ppmu->flags & PPMU_ARCH_207S) && |
8d7c55d0 | 508 | ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); |
330a1eb7 ME |
509 | } |
510 | ||
511 | static int ebb_event_check(struct perf_event *event) | |
512 | { | |
513 | struct perf_event *leader = event->group_leader; | |
514 | ||
515 | /* Event and group leader must agree on EBB */ | |
516 | if (is_ebb_event(leader) != is_ebb_event(event)) | |
517 | return -EINVAL; | |
518 | ||
519 | if (is_ebb_event(event)) { | |
520 | if (!(event->attach_state & PERF_ATTACH_TASK)) | |
521 | return -EINVAL; | |
522 | ||
523 | if (!leader->attr.pinned || !leader->attr.exclusive) | |
524 | return -EINVAL; | |
525 | ||
58b5fb00 ME |
526 | if (event->attr.freq || |
527 | event->attr.inherit || | |
528 | event->attr.sample_type || | |
529 | event->attr.sample_period || | |
530 | event->attr.enable_on_exec) | |
330a1eb7 ME |
531 | return -EINVAL; |
532 | } | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
537 | static void ebb_event_add(struct perf_event *event) | |
538 | { | |
539 | if (!is_ebb_event(event) || current->thread.used_ebb) | |
540 | return; | |
541 | ||
542 | /* | |
543 | * IFF this is the first time we've added an EBB event, set | |
544 | * PMXE in the user MMCR0 so we can detect when it's cleared by | |
545 | * userspace. We need this so that we can context switch while | |
546 | * userspace is in the EBB handler (where PMXE is 0). | |
547 | */ | |
548 | current->thread.used_ebb = 1; | |
549 | current->thread.mmcr0 |= MMCR0_PMXE; | |
550 | } | |
551 | ||
552 | static void ebb_switch_out(unsigned long mmcr0) | |
553 | { | |
554 | if (!(mmcr0 & MMCR0_EBE)) | |
555 | return; | |
556 | ||
557 | current->thread.siar = mfspr(SPRN_SIAR); | |
558 | current->thread.sier = mfspr(SPRN_SIER); | |
559 | current->thread.sdar = mfspr(SPRN_SDAR); | |
560 | current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; | |
561 | current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; | |
562 | } | |
563 | ||
9de5cb0f | 564 | static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) |
330a1eb7 | 565 | { |
9de5cb0f ME |
566 | unsigned long mmcr0 = cpuhw->mmcr[0]; |
567 | ||
330a1eb7 ME |
568 | if (!ebb) |
569 | goto out; | |
570 | ||
76cb8a78 ME |
571 | /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ |
572 | mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; | |
330a1eb7 | 573 | |
c2e37a26 ME |
574 | /* |
575 | * Add any bits from the user MMCR0, FC or PMAO. This is compatible | |
576 | * with pmao_restore_workaround() because we may add PMAO but we never | |
577 | * clear it here. | |
578 | */ | |
330a1eb7 ME |
579 | mmcr0 |= current->thread.mmcr0; |
580 | ||
c2e37a26 ME |
581 | /* |
582 | * Be careful not to set PMXE if userspace had it cleared. This is also | |
583 | * compatible with pmao_restore_workaround() because it has already | |
584 | * cleared PMXE and we leave PMAO alone. | |
585 | */ | |
330a1eb7 ME |
586 | if (!(current->thread.mmcr0 & MMCR0_PMXE)) |
587 | mmcr0 &= ~MMCR0_PMXE; | |
588 | ||
589 | mtspr(SPRN_SIAR, current->thread.siar); | |
590 | mtspr(SPRN_SIER, current->thread.sier); | |
591 | mtspr(SPRN_SDAR, current->thread.sdar); | |
9de5cb0f ME |
592 | |
593 | /* | |
594 | * Merge the kernel & user values of MMCR2. The semantics we implement | |
595 | * are that the user MMCR2 can set bits, ie. cause counters to freeze, | |
596 | * but not clear bits. If a task wants to be able to clear bits, ie. | |
597 | * unfreeze counters, it should not set exclude_xxx in its events and | |
598 | * instead manage the MMCR2 entirely by itself. | |
599 | */ | |
600 | mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2); | |
330a1eb7 ME |
601 | out: |
602 | return mmcr0; | |
603 | } | |
c2e37a26 ME |
604 | |
605 | static void pmao_restore_workaround(bool ebb) | |
606 | { | |
607 | unsigned pmcs[6]; | |
608 | ||
609 | if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) | |
610 | return; | |
611 | ||
612 | /* | |
613 | * On POWER8E there is a hardware defect which affects the PMU context | |
614 | * switch logic, ie. power_pmu_disable/enable(). | |
615 | * | |
616 | * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 | |
617 | * by the hardware. Sometime later the actual PMU exception is | |
618 | * delivered. | |
619 | * | |
620 | * If we context switch, or simply disable/enable, the PMU prior to the | |
621 | * exception arriving, the exception will be lost when we clear PMAO. | |
622 | * | |
623 | * When we reenable the PMU, we will write the saved MMCR0 with PMAO | |
624 | * set, and this _should_ generate an exception. However because of the | |
625 | * defect no exception is generated when we write PMAO, and we get | |
626 | * stuck with no counters counting but no exception delivered. | |
627 | * | |
628 | * The workaround is to detect this case and tweak the hardware to | |
629 | * create another pending PMU exception. | |
630 | * | |
631 | * We do that by setting up PMC6 (cycles) for an imminent overflow and | |
632 | * enabling the PMU. That causes a new exception to be generated in the | |
633 | * chip, but we don't take it yet because we have interrupts hard | |
634 | * disabled. We then write back the PMU state as we want it to be seen | |
635 | * by the exception handler. When we reenable interrupts the exception | |
636 | * handler will be called and see the correct state. | |
637 | * | |
638 | * The logic is the same for EBB, except that the exception is gated by | |
639 | * us having interrupts hard disabled as well as the fact that we are | |
640 | * not in userspace. The exception is finally delivered when we return | |
641 | * to userspace. | |
642 | */ | |
643 | ||
644 | /* Only if PMAO is set and PMAO_SYNC is clear */ | |
645 | if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) | |
646 | return; | |
647 | ||
648 | /* If we're doing EBB, only if BESCR[GE] is set */ | |
649 | if (ebb && !(current->thread.bescr & BESCR_GE)) | |
650 | return; | |
651 | ||
652 | /* | |
653 | * We are already soft-disabled in power_pmu_enable(). We need to hard | |
58bffb5b | 654 | * disable to actually prevent the PMU exception from firing. |
c2e37a26 ME |
655 | */ |
656 | hard_irq_disable(); | |
657 | ||
658 | /* | |
659 | * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. | |
660 | * Using read/write_pmc() in a for loop adds 12 function calls and | |
661 | * almost doubles our code size. | |
662 | */ | |
663 | pmcs[0] = mfspr(SPRN_PMC1); | |
664 | pmcs[1] = mfspr(SPRN_PMC2); | |
665 | pmcs[2] = mfspr(SPRN_PMC3); | |
666 | pmcs[3] = mfspr(SPRN_PMC4); | |
667 | pmcs[4] = mfspr(SPRN_PMC5); | |
668 | pmcs[5] = mfspr(SPRN_PMC6); | |
669 | ||
670 | /* Ensure all freeze bits are unset */ | |
671 | mtspr(SPRN_MMCR2, 0); | |
672 | ||
673 | /* Set up PMC6 to overflow in one cycle */ | |
674 | mtspr(SPRN_PMC6, 0x7FFFFFFE); | |
675 | ||
676 | /* Enable exceptions and unfreeze PMC6 */ | |
677 | mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); | |
678 | ||
679 | /* Now we need to refreeze and restore the PMCs */ | |
680 | mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); | |
681 | ||
682 | mtspr(SPRN_PMC1, pmcs[0]); | |
683 | mtspr(SPRN_PMC2, pmcs[1]); | |
684 | mtspr(SPRN_PMC3, pmcs[2]); | |
685 | mtspr(SPRN_PMC4, pmcs[3]); | |
686 | mtspr(SPRN_PMC5, pmcs[4]); | |
687 | mtspr(SPRN_PMC6, pmcs[5]); | |
688 | } | |
98fb1807 PM |
689 | #endif /* CONFIG_PPC64 */ |
690 | ||
cdd6c482 | 691 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 692 | |
4574910e | 693 | /* |
57c0c15b | 694 | * Read one performance monitor counter (PMC). |
4574910e PM |
695 | */ |
696 | static unsigned long read_pmc(int idx) | |
697 | { | |
698 | unsigned long val; | |
699 | ||
700 | switch (idx) { | |
701 | case 1: | |
702 | val = mfspr(SPRN_PMC1); | |
703 | break; | |
704 | case 2: | |
705 | val = mfspr(SPRN_PMC2); | |
706 | break; | |
707 | case 3: | |
708 | val = mfspr(SPRN_PMC3); | |
709 | break; | |
710 | case 4: | |
711 | val = mfspr(SPRN_PMC4); | |
712 | break; | |
713 | case 5: | |
714 | val = mfspr(SPRN_PMC5); | |
715 | break; | |
716 | case 6: | |
717 | val = mfspr(SPRN_PMC6); | |
718 | break; | |
98fb1807 | 719 | #ifdef CONFIG_PPC64 |
4574910e PM |
720 | case 7: |
721 | val = mfspr(SPRN_PMC7); | |
722 | break; | |
723 | case 8: | |
724 | val = mfspr(SPRN_PMC8); | |
725 | break; | |
98fb1807 | 726 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
727 | default: |
728 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
729 | val = 0; | |
730 | } | |
731 | return val; | |
732 | } | |
733 | ||
734 | /* | |
735 | * Write one PMC. | |
736 | */ | |
737 | static void write_pmc(int idx, unsigned long val) | |
738 | { | |
739 | switch (idx) { | |
740 | case 1: | |
741 | mtspr(SPRN_PMC1, val); | |
742 | break; | |
743 | case 2: | |
744 | mtspr(SPRN_PMC2, val); | |
745 | break; | |
746 | case 3: | |
747 | mtspr(SPRN_PMC3, val); | |
748 | break; | |
749 | case 4: | |
750 | mtspr(SPRN_PMC4, val); | |
751 | break; | |
752 | case 5: | |
753 | mtspr(SPRN_PMC5, val); | |
754 | break; | |
755 | case 6: | |
756 | mtspr(SPRN_PMC6, val); | |
757 | break; | |
98fb1807 | 758 | #ifdef CONFIG_PPC64 |
4574910e PM |
759 | case 7: |
760 | mtspr(SPRN_PMC7, val); | |
761 | break; | |
762 | case 8: | |
763 | mtspr(SPRN_PMC8, val); | |
764 | break; | |
98fb1807 | 765 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
766 | default: |
767 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
768 | } | |
769 | } | |
770 | ||
5f6d0380 AK |
771 | /* Called from sysrq_handle_showregs() */ |
772 | void perf_event_print_debug(void) | |
773 | { | |
774 | unsigned long sdar, sier, flags; | |
775 | u32 pmcs[MAX_HWEVENTS]; | |
776 | int i; | |
777 | ||
778 | if (!ppmu->n_counter) | |
779 | return; | |
780 | ||
781 | local_irq_save(flags); | |
782 | ||
783 | pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", | |
784 | smp_processor_id(), ppmu->name, ppmu->n_counter); | |
785 | ||
786 | for (i = 0; i < ppmu->n_counter; i++) | |
787 | pmcs[i] = read_pmc(i + 1); | |
788 | ||
789 | for (; i < MAX_HWEVENTS; i++) | |
790 | pmcs[i] = 0xdeadbeef; | |
791 | ||
792 | pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", | |
793 | pmcs[0], pmcs[1], pmcs[2], pmcs[3]); | |
794 | ||
795 | if (ppmu->n_counter > 4) | |
796 | pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", | |
797 | pmcs[4], pmcs[5], pmcs[6], pmcs[7]); | |
798 | ||
799 | pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", | |
800 | mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); | |
801 | ||
802 | sdar = sier = 0; | |
803 | #ifdef CONFIG_PPC64 | |
804 | sdar = mfspr(SPRN_SDAR); | |
805 | ||
806 | if (ppmu->flags & PPMU_HAS_SIER) | |
807 | sier = mfspr(SPRN_SIER); | |
808 | ||
4d9690dd | 809 | if (ppmu->flags & PPMU_ARCH_207S) { |
5f6d0380 AK |
810 | pr_info("MMCR2: %016lx EBBHR: %016lx\n", |
811 | mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); | |
812 | pr_info("EBBRR: %016lx BESCR: %016lx\n", | |
813 | mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); | |
814 | } | |
815 | #endif | |
816 | pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", | |
817 | mfspr(SPRN_SIAR), sdar, sier); | |
818 | ||
819 | local_irq_restore(flags); | |
820 | } | |
821 | ||
4574910e PM |
822 | /* |
823 | * Check if a set of events can all go on the PMU at once. | |
824 | * If they can't, this will look at alternative codes for the events | |
825 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 826 | * The feasible set is returned in event_id[]. |
4574910e | 827 | */ |
cdd6c482 IM |
828 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
829 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 830 | int n_ev) |
4574910e | 831 | { |
448d64f8 | 832 | unsigned long mask, value, nv; |
cdd6c482 IM |
833 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
834 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 835 | int i, j; |
448d64f8 PM |
836 | unsigned long addf = ppmu->add_fields; |
837 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 838 | |
a8f90e90 | 839 | if (n_ev > ppmu->n_counter) |
4574910e PM |
840 | return -1; |
841 | ||
842 | /* First see if the events will go on as-is */ | |
843 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 844 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
845 | && !ppmu->limited_pmc_event(event_id[i])) { |
846 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 847 | cpuhw->alternatives[i]); |
cdd6c482 | 848 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 849 | } |
cdd6c482 | 850 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 851 | &cpuhw->avalues[i][0])) |
4574910e | 852 | return -1; |
4574910e PM |
853 | } |
854 | value = mask = 0; | |
855 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
856 | nv = (value | cpuhw->avalues[i][0]) + |
857 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 858 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
859 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
860 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
861 | break; |
862 | value = nv; | |
e51ee31e | 863 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
864 | } |
865 | if (i == n_ev) | |
866 | return 0; /* all OK */ | |
867 | ||
868 | /* doesn't work, gather alternatives... */ | |
869 | if (!ppmu->get_alternatives) | |
870 | return -1; | |
871 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 872 | choice[i] = 0; |
cdd6c482 | 873 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 874 | cpuhw->alternatives[i]); |
4574910e | 875 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
876 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
877 | &cpuhw->amasks[i][j], | |
878 | &cpuhw->avalues[i][j]); | |
4574910e PM |
879 | } |
880 | ||
881 | /* enumerate all possibilities and see if any will work */ | |
882 | i = 0; | |
883 | j = -1; | |
884 | value = mask = nv = 0; | |
885 | while (i < n_ev) { | |
886 | if (j >= 0) { | |
887 | /* we're backtracking, restore context */ | |
888 | value = svalues[i]; | |
889 | mask = smasks[i]; | |
890 | j = choice[i]; | |
891 | } | |
892 | /* | |
cdd6c482 | 893 | * See if any alternative k for event_id i, |
4574910e PM |
894 | * where k > j, will satisfy the constraints. |
895 | */ | |
896 | while (++j < n_alt[i]) { | |
e51ee31e PM |
897 | nv = (value | cpuhw->avalues[i][j]) + |
898 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 899 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
900 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
901 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
902 | break; |
903 | } | |
904 | if (j >= n_alt[i]) { | |
905 | /* | |
906 | * No feasible alternative, backtrack | |
cdd6c482 | 907 | * to event_id i-1 and continue enumerating its |
4574910e PM |
908 | * alternatives from where we got up to. |
909 | */ | |
910 | if (--i < 0) | |
911 | return -1; | |
912 | } else { | |
913 | /* | |
cdd6c482 IM |
914 | * Found a feasible alternative for event_id i, |
915 | * remember where we got up to with this event_id, | |
916 | * go on to the next event_id, and start with | |
4574910e PM |
917 | * the first alternative for it. |
918 | */ | |
919 | choice[i] = j; | |
920 | svalues[i] = value; | |
921 | smasks[i] = mask; | |
922 | value = nv; | |
e51ee31e | 923 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
924 | ++i; |
925 | j = -1; | |
926 | } | |
927 | } | |
928 | ||
929 | /* OK, we have a feasible combination, tell the caller the solution */ | |
930 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 931 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
932 | return 0; |
933 | } | |
934 | ||
0475f9ea | 935 | /* |
cdd6c482 | 936 | * Check if newly-added events have consistent settings for |
0475f9ea | 937 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 938 | * added events. |
0475f9ea | 939 | */ |
cdd6c482 | 940 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 941 | int n_prev, int n_new) |
0475f9ea | 942 | { |
ab7ef2e5 PM |
943 | int eu = 0, ek = 0, eh = 0; |
944 | int i, n, first; | |
cdd6c482 | 945 | struct perf_event *event; |
0475f9ea | 946 | |
9de5cb0f ME |
947 | /* |
948 | * If the PMU we're on supports per event exclude settings then we | |
949 | * don't need to do any of this logic. NB. This assumes no PMU has both | |
950 | * per event exclude and limited PMCs. | |
951 | */ | |
952 | if (ppmu->flags & PPMU_ARCH_207S) | |
953 | return 0; | |
954 | ||
0475f9ea PM |
955 | n = n_prev + n_new; |
956 | if (n <= 1) | |
957 | return 0; | |
958 | ||
ab7ef2e5 PM |
959 | first = 1; |
960 | for (i = 0; i < n; ++i) { | |
961 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
962 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
963 | continue; | |
964 | } | |
cdd6c482 | 965 | event = ctrs[i]; |
ab7ef2e5 | 966 | if (first) { |
cdd6c482 IM |
967 | eu = event->attr.exclude_user; |
968 | ek = event->attr.exclude_kernel; | |
969 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 970 | first = 0; |
cdd6c482 IM |
971 | } else if (event->attr.exclude_user != eu || |
972 | event->attr.exclude_kernel != ek || | |
973 | event->attr.exclude_hv != eh) { | |
0475f9ea | 974 | return -EAGAIN; |
ab7ef2e5 | 975 | } |
0475f9ea | 976 | } |
ab7ef2e5 PM |
977 | |
978 | if (eu || ek || eh) | |
979 | for (i = 0; i < n; ++i) | |
980 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
981 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
982 | ||
0475f9ea PM |
983 | return 0; |
984 | } | |
985 | ||
86c74ab3 EM |
986 | static u64 check_and_compute_delta(u64 prev, u64 val) |
987 | { | |
988 | u64 delta = (val - prev) & 0xfffffffful; | |
989 | ||
990 | /* | |
991 | * POWER7 can roll back counter values, if the new value is smaller | |
992 | * than the previous value it will cause the delta and the counter to | |
993 | * have bogus values unless we rolled a counter over. If a coutner is | |
994 | * rolled back, it will be smaller, but within 256, which is the maximum | |
027dfac6 | 995 | * number of events to rollback at once. If we detect a rollback |
86c74ab3 EM |
996 | * return 0. This can lead to a small lack of precision in the |
997 | * counters. | |
998 | */ | |
999 | if (prev > val && (prev - val) < 256) | |
1000 | delta = 0; | |
1001 | ||
1002 | return delta; | |
1003 | } | |
1004 | ||
cdd6c482 | 1005 | static void power_pmu_read(struct perf_event *event) |
4574910e | 1006 | { |
98fb1807 | 1007 | s64 val, delta, prev; |
4574910e | 1008 | |
a4eaf7f1 PZ |
1009 | if (event->hw.state & PERF_HES_STOPPED) |
1010 | return; | |
1011 | ||
cdd6c482 | 1012 | if (!event->hw.idx) |
4574910e | 1013 | return; |
330a1eb7 ME |
1014 | |
1015 | if (is_ebb_event(event)) { | |
1016 | val = read_pmc(event->hw.idx); | |
1017 | local64_set(&event->hw.prev_count, val); | |
1018 | return; | |
1019 | } | |
1020 | ||
4574910e PM |
1021 | /* |
1022 | * Performance monitor interrupts come even when interrupts | |
1023 | * are soft-disabled, as long as interrupts are hard-enabled. | |
1024 | * Therefore we treat them like NMIs. | |
1025 | */ | |
1026 | do { | |
e7850595 | 1027 | prev = local64_read(&event->hw.prev_count); |
4574910e | 1028 | barrier(); |
cdd6c482 | 1029 | val = read_pmc(event->hw.idx); |
86c74ab3 EM |
1030 | delta = check_and_compute_delta(prev, val); |
1031 | if (!delta) | |
1032 | return; | |
e7850595 | 1033 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 1034 | |
e7850595 | 1035 | local64_add(delta, &event->count); |
f5602941 AB |
1036 | |
1037 | /* | |
1038 | * A number of places program the PMC with (0x80000000 - period_left). | |
1039 | * We never want period_left to be less than 1 because we will program | |
1040 | * the PMC with a value >= 0x800000000 and an edge detected PMC will | |
1041 | * roll around to 0 before taking an exception. We have seen this | |
1042 | * on POWER8. | |
1043 | * | |
1044 | * To fix this, clamp the minimum value of period_left to 1. | |
1045 | */ | |
1046 | do { | |
1047 | prev = local64_read(&event->hw.period_left); | |
1048 | val = prev - delta; | |
1049 | if (val < 1) | |
1050 | val = 1; | |
1051 | } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); | |
4574910e PM |
1052 | } |
1053 | ||
ab7ef2e5 PM |
1054 | /* |
1055 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
1056 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 1057 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
1058 | */ |
1059 | static int is_limited_pmc(int pmcnum) | |
1060 | { | |
0bbd0d4b PM |
1061 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
1062 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
1063 | } |
1064 | ||
a8f90e90 | 1065 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
1066 | unsigned long pmc5, unsigned long pmc6) |
1067 | { | |
cdd6c482 | 1068 | struct perf_event *event; |
ab7ef2e5 PM |
1069 | u64 val, prev, delta; |
1070 | int i; | |
1071 | ||
1072 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 1073 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 1074 | if (!event->hw.idx) |
ab7ef2e5 | 1075 | continue; |
cdd6c482 | 1076 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 1077 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 1078 | event->hw.idx = 0; |
86c74ab3 EM |
1079 | delta = check_and_compute_delta(prev, val); |
1080 | if (delta) | |
1081 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
1082 | } |
1083 | } | |
1084 | ||
a8f90e90 | 1085 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
1086 | unsigned long pmc5, unsigned long pmc6) |
1087 | { | |
cdd6c482 | 1088 | struct perf_event *event; |
86c74ab3 | 1089 | u64 val, prev; |
ab7ef2e5 PM |
1090 | int i; |
1091 | ||
1092 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 1093 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
1094 | event->hw.idx = cpuhw->limited_hwidx[i]; |
1095 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
1096 | prev = local64_read(&event->hw.prev_count); |
1097 | if (check_and_compute_delta(prev, val)) | |
1098 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 1099 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
1100 | } |
1101 | } | |
1102 | ||
1103 | /* | |
cdd6c482 | 1104 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 1105 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
1106 | * other events. We try to keep the values from the limited |
1107 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 1108 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
1109 | * the limited events as small and consistent as possible. |
1110 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
1111 | * both, and always in the same order, to minimize variability, |
1112 | * and do it inside the same asm that writes MMCR0. | |
1113 | */ | |
cdd6c482 | 1114 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
1115 | { |
1116 | unsigned long pmc5, pmc6; | |
1117 | ||
1118 | if (!cpuhw->n_limited) { | |
1119 | mtspr(SPRN_MMCR0, mmcr0); | |
1120 | return; | |
1121 | } | |
1122 | ||
1123 | /* | |
1124 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
1125 | * To ensure we don't get a performance monitor interrupt |
1126 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 1127 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 1128 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
1129 | */ |
1130 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
1131 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
1132 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
1133 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
1134 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
1135 | ||
1136 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 1137 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 1138 | else |
a8f90e90 | 1139 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
1140 | |
1141 | /* | |
cdd6c482 | 1142 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
1143 | * enable bits, if necessary. |
1144 | */ | |
1145 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
1146 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
1147 | } |
1148 | ||
4574910e | 1149 | /* |
cdd6c482 IM |
1150 | * Disable all events to prevent PMU interrupts and to allow |
1151 | * events to be added or removed. | |
4574910e | 1152 | */ |
a4eaf7f1 | 1153 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 1154 | { |
cdd6c482 | 1155 | struct cpu_hw_events *cpuhw; |
330a1eb7 | 1156 | unsigned long flags, mmcr0, val; |
4574910e | 1157 | |
f36a1a13 PM |
1158 | if (!ppmu) |
1159 | return; | |
4574910e | 1160 | local_irq_save(flags); |
69111bac | 1161 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
4574910e | 1162 | |
448d64f8 | 1163 | if (!cpuhw->disabled) { |
01d0287f PM |
1164 | /* |
1165 | * Check if we ever enabled the PMU on this cpu. | |
1166 | */ | |
1167 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 1168 | ppc_enable_pmcs(); |
01d0287f PM |
1169 | cpuhw->pmcs_enabled = 1; |
1170 | } | |
1171 | ||
378a6ee9 | 1172 | /* |
76cb8a78 | 1173 | * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 |
378a6ee9 | 1174 | */ |
330a1eb7 | 1175 | val = mmcr0 = mfspr(SPRN_MMCR0); |
378a6ee9 | 1176 | val |= MMCR0_FC; |
76cb8a78 ME |
1177 | val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | |
1178 | MMCR0_FC56); | |
378a6ee9 ME |
1179 | |
1180 | /* | |
1181 | * The barrier is to make sure the mtspr has been | |
1182 | * executed and the PMU has frozen the events etc. | |
1183 | * before we return. | |
1184 | */ | |
1185 | write_mmcr0(cpuhw, val); | |
1186 | mb(); | |
1187 | ||
f708223d PM |
1188 | /* |
1189 | * Disable instruction sampling if it was enabled | |
1190 | */ | |
1191 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1192 | mtspr(SPRN_MMCRA, | |
1193 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
1194 | mb(); | |
1195 | } | |
1196 | ||
378a6ee9 ME |
1197 | cpuhw->disabled = 1; |
1198 | cpuhw->n_added = 0; | |
330a1eb7 ME |
1199 | |
1200 | ebb_switch_out(mmcr0); | |
4574910e | 1201 | } |
330a1eb7 | 1202 | |
4574910e | 1203 | local_irq_restore(flags); |
4574910e PM |
1204 | } |
1205 | ||
1206 | /* | |
cdd6c482 IM |
1207 | * Re-enable all events if disable == 0. |
1208 | * If we were previously disabled and events were added, then | |
4574910e PM |
1209 | * put the new config on the PMU. |
1210 | */ | |
a4eaf7f1 | 1211 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 1212 | { |
cdd6c482 IM |
1213 | struct perf_event *event; |
1214 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
1215 | unsigned long flags; |
1216 | long i; | |
330a1eb7 | 1217 | unsigned long val, mmcr0; |
4574910e | 1218 | s64 left; |
cdd6c482 | 1219 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
1220 | int n_lim; |
1221 | int idx; | |
330a1eb7 | 1222 | bool ebb; |
4574910e | 1223 | |
f36a1a13 PM |
1224 | if (!ppmu) |
1225 | return; | |
4574910e | 1226 | local_irq_save(flags); |
0a48843d | 1227 | |
69111bac | 1228 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
0a48843d ME |
1229 | if (!cpuhw->disabled) |
1230 | goto out; | |
1231 | ||
4ea355b5 ME |
1232 | if (cpuhw->n_events == 0) { |
1233 | ppc_set_pmu_inuse(0); | |
1234 | goto out; | |
1235 | } | |
1236 | ||
4574910e PM |
1237 | cpuhw->disabled = 0; |
1238 | ||
330a1eb7 ME |
1239 | /* |
1240 | * EBB requires an exclusive group and all events must have the EBB | |
1241 | * flag set, or not set, so we can just check a single event. Also we | |
1242 | * know we have at least one event. | |
1243 | */ | |
1244 | ebb = is_ebb_event(cpuhw->event[0]); | |
1245 | ||
4574910e | 1246 | /* |
cdd6c482 | 1247 | * If we didn't change anything, or only removed events, |
4574910e PM |
1248 | * no need to recalculate MMCR* settings and reset the PMCs. |
1249 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 1250 | * (possibly updated for removal of events). |
4574910e PM |
1251 | */ |
1252 | if (!cpuhw->n_added) { | |
f708223d | 1253 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 1254 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
f708223d | 1255 | goto out_enable; |
4574910e PM |
1256 | } |
1257 | ||
1258 | /* | |
79a4cb28 | 1259 | * Clear all MMCR settings and recompute them for the new set of events. |
4574910e | 1260 | */ |
79a4cb28 ME |
1261 | memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); |
1262 | ||
cdd6c482 | 1263 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
8abd818f | 1264 | cpuhw->mmcr, cpuhw->event)) { |
4574910e PM |
1265 | /* shouldn't ever get here */ |
1266 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
1267 | goto out; | |
1268 | } | |
1269 | ||
9de5cb0f ME |
1270 | if (!(ppmu->flags & PPMU_ARCH_207S)) { |
1271 | /* | |
1272 | * Add in MMCR0 freeze bits corresponding to the attr.exclude_* | |
1273 | * bits for the first event. We have already checked that all | |
1274 | * events have the same value for these bits as the first event. | |
1275 | */ | |
1276 | event = cpuhw->event[0]; | |
1277 | if (event->attr.exclude_user) | |
1278 | cpuhw->mmcr[0] |= MMCR0_FCP; | |
1279 | if (event->attr.exclude_kernel) | |
1280 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
1281 | if (event->attr.exclude_hv) | |
1282 | cpuhw->mmcr[0] |= MMCR0_FCHV; | |
1283 | } | |
0475f9ea | 1284 | |
4574910e PM |
1285 | /* |
1286 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
1287 | * bit set and set the hardware events to their initial values. |
1288 | * Then unfreeze the events. | |
4574910e | 1289 | */ |
a6dbf93a | 1290 | ppc_set_pmu_inuse(1); |
f708223d | 1291 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
1292 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
1293 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
1294 | | MMCR0_FC); | |
9de5cb0f ME |
1295 | if (ppmu->flags & PPMU_ARCH_207S) |
1296 | mtspr(SPRN_MMCR2, cpuhw->mmcr[3]); | |
4574910e PM |
1297 | |
1298 | /* | |
cdd6c482 | 1299 | * Read off any pre-existing events that need to move |
4574910e PM |
1300 | * to another PMC. |
1301 | */ | |
cdd6c482 IM |
1302 | for (i = 0; i < cpuhw->n_events; ++i) { |
1303 | event = cpuhw->event[i]; | |
1304 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
1305 | power_pmu_read(event); | |
1306 | write_pmc(event->hw.idx, 0); | |
1307 | event->hw.idx = 0; | |
4574910e PM |
1308 | } |
1309 | } | |
1310 | ||
1311 | /* | |
cdd6c482 | 1312 | * Initialize the PMCs for all the new and moved events. |
4574910e | 1313 | */ |
ab7ef2e5 | 1314 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
1315 | for (i = 0; i < cpuhw->n_events; ++i) { |
1316 | event = cpuhw->event[i]; | |
1317 | if (event->hw.idx) | |
4574910e | 1318 | continue; |
ab7ef2e5 PM |
1319 | idx = hwc_index[i] + 1; |
1320 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 1321 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
1322 | cpuhw->limited_hwidx[n_lim] = idx; |
1323 | ++n_lim; | |
1324 | continue; | |
1325 | } | |
330a1eb7 ME |
1326 | |
1327 | if (ebb) | |
1328 | val = local64_read(&event->hw.prev_count); | |
1329 | else { | |
1330 | val = 0; | |
1331 | if (event->hw.sample_period) { | |
1332 | left = local64_read(&event->hw.period_left); | |
1333 | if (left < 0x80000000L) | |
1334 | val = 0x80000000L - left; | |
1335 | } | |
1336 | local64_set(&event->hw.prev_count, val); | |
4574910e | 1337 | } |
330a1eb7 | 1338 | |
cdd6c482 | 1339 | event->hw.idx = idx; |
a4eaf7f1 PZ |
1340 | if (event->hw.state & PERF_HES_STOPPED) |
1341 | val = 0; | |
ab7ef2e5 | 1342 | write_pmc(idx, val); |
330a1eb7 | 1343 | |
cdd6c482 | 1344 | perf_event_update_userpage(event); |
4574910e | 1345 | } |
ab7ef2e5 | 1346 | cpuhw->n_limited = n_lim; |
4574910e | 1347 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
1348 | |
1349 | out_enable: | |
c2e37a26 ME |
1350 | pmao_restore_workaround(ebb); |
1351 | ||
9de5cb0f | 1352 | mmcr0 = ebb_switch_in(ebb, cpuhw); |
330a1eb7 | 1353 | |
f708223d | 1354 | mb(); |
b4d6c06c AK |
1355 | if (cpuhw->bhrb_users) |
1356 | ppmu->config_bhrb(cpuhw->bhrb_filter); | |
1357 | ||
330a1eb7 | 1358 | write_mmcr0(cpuhw, mmcr0); |
4574910e | 1359 | |
f708223d PM |
1360 | /* |
1361 | * Enable instruction sampling if necessary | |
1362 | */ | |
1363 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1364 | mb(); | |
1365 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
1366 | } | |
1367 | ||
4574910e | 1368 | out: |
3925f46b | 1369 | |
4574910e PM |
1370 | local_irq_restore(flags); |
1371 | } | |
1372 | ||
cdd6c482 IM |
1373 | static int collect_events(struct perf_event *group, int max_count, |
1374 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 1375 | unsigned int *flags) |
4574910e PM |
1376 | { |
1377 | int n = 0; | |
cdd6c482 | 1378 | struct perf_event *event; |
4574910e | 1379 | |
cdd6c482 | 1380 | if (!is_software_event(group)) { |
4574910e PM |
1381 | if (n >= max_count) |
1382 | return -1; | |
1383 | ctrs[n] = group; | |
cdd6c482 | 1384 | flags[n] = group->hw.event_base; |
4574910e PM |
1385 | events[n++] = group->hw.config; |
1386 | } | |
a8f90e90 | 1387 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
1388 | if (!is_software_event(event) && |
1389 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
1390 | if (n >= max_count) |
1391 | return -1; | |
cdd6c482 IM |
1392 | ctrs[n] = event; |
1393 | flags[n] = event->hw.event_base; | |
1394 | events[n++] = event->hw.config; | |
4574910e PM |
1395 | } |
1396 | } | |
1397 | return n; | |
1398 | } | |
1399 | ||
4574910e | 1400 | /* |
cdd6c482 IM |
1401 | * Add a event to the PMU. |
1402 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 1403 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
1404 | * actual work of reconfiguring the PMU. |
1405 | */ | |
a4eaf7f1 | 1406 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 1407 | { |
cdd6c482 | 1408 | struct cpu_hw_events *cpuhw; |
4574910e | 1409 | unsigned long flags; |
4574910e PM |
1410 | int n0; |
1411 | int ret = -EAGAIN; | |
1412 | ||
1413 | local_irq_save(flags); | |
33696fc0 | 1414 | perf_pmu_disable(event->pmu); |
4574910e PM |
1415 | |
1416 | /* | |
cdd6c482 | 1417 | * Add the event to the list (if there is room) |
4574910e PM |
1418 | * and check whether the total set is still feasible. |
1419 | */ | |
69111bac | 1420 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1421 | n0 = cpuhw->n_events; |
a8f90e90 | 1422 | if (n0 >= ppmu->n_counter) |
4574910e | 1423 | goto out; |
cdd6c482 IM |
1424 | cpuhw->event[n0] = event; |
1425 | cpuhw->events[n0] = event->hw.config; | |
1426 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 1427 | |
f53d168c | 1428 | /* |
1429 | * This event may have been disabled/stopped in record_and_restart() | |
1430 | * because we exceeded the ->event_limit. If re-starting the event, | |
1431 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
1432 | * notification is re-enabled. | |
1433 | */ | |
a4eaf7f1 PZ |
1434 | if (!(ef_flags & PERF_EF_START)) |
1435 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 1436 | else |
1437 | event->hw.state = 0; | |
a4eaf7f1 | 1438 | |
8e6d5573 LM |
1439 | /* |
1440 | * If group events scheduling transaction was started, | |
25985edc | 1441 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
1442 | * at commit time(->commit_txn) as a whole |
1443 | */ | |
8f3e5684 | 1444 | if (cpuhw->txn_flags & PERF_PMU_TXN_ADD) |
8e6d5573 LM |
1445 | goto nocheck; |
1446 | ||
cdd6c482 | 1447 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 1448 | goto out; |
e51ee31e | 1449 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 1450 | goto out; |
cdd6c482 | 1451 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
1452 | |
1453 | nocheck: | |
330a1eb7 ME |
1454 | ebb_event_add(event); |
1455 | ||
cdd6c482 | 1456 | ++cpuhw->n_events; |
4574910e PM |
1457 | ++cpuhw->n_added; |
1458 | ||
1459 | ret = 0; | |
1460 | out: | |
ff3d79dc | 1461 | if (has_branch_stack(event)) { |
3925f46b | 1462 | power_pmu_bhrb_enable(event); |
ff3d79dc AK |
1463 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( |
1464 | event->attr.branch_sample_type); | |
1465 | } | |
3925f46b | 1466 | |
33696fc0 | 1467 | perf_pmu_enable(event->pmu); |
4574910e PM |
1468 | local_irq_restore(flags); |
1469 | return ret; | |
1470 | } | |
1471 | ||
1472 | /* | |
cdd6c482 | 1473 | * Remove a event from the PMU. |
4574910e | 1474 | */ |
a4eaf7f1 | 1475 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 1476 | { |
cdd6c482 | 1477 | struct cpu_hw_events *cpuhw; |
4574910e | 1478 | long i; |
4574910e PM |
1479 | unsigned long flags; |
1480 | ||
1481 | local_irq_save(flags); | |
33696fc0 | 1482 | perf_pmu_disable(event->pmu); |
4574910e | 1483 | |
cdd6c482 IM |
1484 | power_pmu_read(event); |
1485 | ||
69111bac | 1486 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 IM |
1487 | for (i = 0; i < cpuhw->n_events; ++i) { |
1488 | if (event == cpuhw->event[i]) { | |
219a92a4 | 1489 | while (++i < cpuhw->n_events) { |
cdd6c482 | 1490 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
1491 | cpuhw->events[i-1] = cpuhw->events[i]; |
1492 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
1493 | } | |
cdd6c482 IM |
1494 | --cpuhw->n_events; |
1495 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
1496 | if (event->hw.idx) { | |
1497 | write_pmc(event->hw.idx, 0); | |
1498 | event->hw.idx = 0; | |
ab7ef2e5 | 1499 | } |
cdd6c482 | 1500 | perf_event_update_userpage(event); |
4574910e PM |
1501 | break; |
1502 | } | |
1503 | } | |
ab7ef2e5 | 1504 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 1505 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
1506 | break; |
1507 | if (i < cpuhw->n_limited) { | |
1508 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 1509 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
1510 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
1511 | } | |
1512 | --cpuhw->n_limited; | |
1513 | } | |
cdd6c482 IM |
1514 | if (cpuhw->n_events == 0) { |
1515 | /* disable exceptions if no events are running */ | |
4574910e PM |
1516 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
1517 | } | |
1518 | ||
3925f46b AK |
1519 | if (has_branch_stack(event)) |
1520 | power_pmu_bhrb_disable(event); | |
1521 | ||
33696fc0 | 1522 | perf_pmu_enable(event->pmu); |
4574910e PM |
1523 | local_irq_restore(flags); |
1524 | } | |
1525 | ||
8a7b8cb9 | 1526 | /* |
a4eaf7f1 PZ |
1527 | * POWER-PMU does not support disabling individual counters, hence |
1528 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 1529 | */ |
a4eaf7f1 PZ |
1530 | |
1531 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 1532 | { |
8a7b8cb9 | 1533 | unsigned long flags; |
a4eaf7f1 | 1534 | s64 left; |
9a45a940 | 1535 | unsigned long val; |
8a7b8cb9 | 1536 | |
cdd6c482 | 1537 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 1538 | return; |
a4eaf7f1 PZ |
1539 | |
1540 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
1541 | return; | |
1542 | ||
1543 | if (ef_flags & PERF_EF_RELOAD) | |
1544 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1545 | ||
1546 | local_irq_save(flags); | |
1547 | perf_pmu_disable(event->pmu); | |
1548 | ||
1549 | event->hw.state = 0; | |
1550 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
1551 | |
1552 | val = 0; | |
1553 | if (left < 0x80000000L) | |
1554 | val = 0x80000000L - left; | |
1555 | ||
1556 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1557 | |
1558 | perf_event_update_userpage(event); | |
1559 | perf_pmu_enable(event->pmu); | |
1560 | local_irq_restore(flags); | |
1561 | } | |
1562 | ||
1563 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1564 | { | |
1565 | unsigned long flags; | |
1566 | ||
1567 | if (!event->hw.idx || !event->hw.sample_period) | |
1568 | return; | |
1569 | ||
1570 | if (event->hw.state & PERF_HES_STOPPED) | |
1571 | return; | |
1572 | ||
8a7b8cb9 | 1573 | local_irq_save(flags); |
33696fc0 | 1574 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1575 | |
cdd6c482 | 1576 | power_pmu_read(event); |
a4eaf7f1 PZ |
1577 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1578 | write_pmc(event->hw.idx, 0); | |
1579 | ||
cdd6c482 | 1580 | perf_event_update_userpage(event); |
33696fc0 | 1581 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1582 | local_irq_restore(flags); |
1583 | } | |
1584 | ||
8e6d5573 LM |
1585 | /* |
1586 | * Start group events scheduling transaction | |
1587 | * Set the flag to make pmu::enable() not perform the | |
1588 | * schedulability test, it will be performed at commit time | |
fbbe0701 SB |
1589 | * |
1590 | * We only support PERF_PMU_TXN_ADD transactions. Save the | |
1591 | * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD | |
1592 | * transactions. | |
8e6d5573 | 1593 | */ |
fbbe0701 | 1594 | static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) |
8e6d5573 | 1595 | { |
69111bac | 1596 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
8e6d5573 | 1597 | |
fbbe0701 SB |
1598 | WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ |
1599 | ||
1600 | cpuhw->txn_flags = txn_flags; | |
1601 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1602 | return; | |
1603 | ||
33696fc0 | 1604 | perf_pmu_disable(pmu); |
8e6d5573 LM |
1605 | cpuhw->n_txn_start = cpuhw->n_events; |
1606 | } | |
1607 | ||
1608 | /* | |
1609 | * Stop group events scheduling transaction | |
1610 | * Clear the flag and pmu::enable() will perform the | |
1611 | * schedulability test. | |
1612 | */ | |
e51df2c1 | 1613 | static void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 | 1614 | { |
69111bac | 1615 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
fbbe0701 SB |
1616 | unsigned int txn_flags; |
1617 | ||
1618 | WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ | |
1619 | ||
1620 | txn_flags = cpuhw->txn_flags; | |
1621 | cpuhw->txn_flags = 0; | |
1622 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1623 | return; | |
8e6d5573 | 1624 | |
33696fc0 | 1625 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1626 | } |
1627 | ||
1628 | /* | |
1629 | * Commit group events scheduling transaction | |
1630 | * Perform the group schedulability test as a whole | |
1631 | * Return 0 if success | |
1632 | */ | |
e51df2c1 | 1633 | static int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1634 | { |
1635 | struct cpu_hw_events *cpuhw; | |
1636 | long i, n; | |
1637 | ||
1638 | if (!ppmu) | |
1639 | return -EAGAIN; | |
fbbe0701 | 1640 | |
69111bac | 1641 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
fbbe0701 SB |
1642 | WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ |
1643 | ||
1644 | if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { | |
1645 | cpuhw->txn_flags = 0; | |
1646 | return 0; | |
1647 | } | |
1648 | ||
8e6d5573 LM |
1649 | n = cpuhw->n_events; |
1650 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1651 | return -EAGAIN; | |
1652 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1653 | if (i < 0) | |
1654 | return -EAGAIN; | |
1655 | ||
1656 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1657 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1658 | ||
fbbe0701 | 1659 | cpuhw->txn_flags = 0; |
33696fc0 | 1660 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1661 | return 0; |
1662 | } | |
1663 | ||
ab7ef2e5 | 1664 | /* |
cdd6c482 | 1665 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1666 | * or 0 if not. |
cdd6c482 | 1667 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1668 | * that a limited PMC can count, doesn't require interrupts, and |
1669 | * doesn't exclude any processor mode. | |
1670 | */ | |
cdd6c482 | 1671 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1672 | unsigned int flags) |
1673 | { | |
1674 | int n; | |
ef923214 | 1675 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1676 | |
cdd6c482 IM |
1677 | if (event->attr.exclude_user |
1678 | || event->attr.exclude_kernel | |
1679 | || event->attr.exclude_hv | |
1680 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1681 | return 0; |
1682 | ||
1683 | if (ppmu->limited_pmc_event(ev)) | |
1684 | return 1; | |
1685 | ||
1686 | /* | |
cdd6c482 | 1687 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1688 | * see if any alternative code goes on a limited PMC. |
1689 | */ | |
1690 | if (!ppmu->get_alternatives) | |
1691 | return 0; | |
1692 | ||
1693 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1694 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1695 | |
ef923214 | 1696 | return n > 0; |
ab7ef2e5 PM |
1697 | } |
1698 | ||
1699 | /* | |
cdd6c482 IM |
1700 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1701 | * and return the event_id code, or 0 if there is no such alternative. | |
1702 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1703 | */ |
ef923214 | 1704 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1705 | { |
ef923214 | 1706 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1707 | int n; |
1708 | ||
1709 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1710 | n = ppmu->get_alternatives(ev, flags, alt); | |
1711 | if (!n) | |
1712 | return 0; | |
1713 | return alt[0]; | |
1714 | } | |
1715 | ||
cdd6c482 IM |
1716 | /* Number of perf_events counting hardware events */ |
1717 | static atomic_t num_events; | |
7595d63b PM |
1718 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1719 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1720 | ||
1721 | /* | |
cdd6c482 | 1722 | * Release the PMU if this is the last perf_event. |
7595d63b | 1723 | */ |
cdd6c482 | 1724 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1725 | { |
cdd6c482 | 1726 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1727 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1728 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1729 | release_pmc_hardware(); |
1730 | mutex_unlock(&pmc_reserve_mutex); | |
1731 | } | |
1732 | } | |
1733 | ||
106b506c | 1734 | /* |
cdd6c482 | 1735 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1736 | */ |
1737 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1738 | { | |
1739 | unsigned long type, op, result; | |
1740 | int ev; | |
1741 | ||
1742 | if (!ppmu->cache_events) | |
1743 | return -EINVAL; | |
1744 | ||
1745 | /* unpack config */ | |
1746 | type = config & 0xff; | |
1747 | op = (config >> 8) & 0xff; | |
1748 | result = (config >> 16) & 0xff; | |
1749 | ||
1750 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1751 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1752 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1753 | return -EINVAL; | |
1754 | ||
1755 | ev = (*ppmu->cache_events)[type][op][result]; | |
1756 | if (ev == 0) | |
1757 | return -EOPNOTSUPP; | |
1758 | if (ev == -1) | |
1759 | return -EINVAL; | |
1760 | *eventp = ev; | |
1761 | return 0; | |
1762 | } | |
1763 | ||
b0a873eb | 1764 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1765 | { |
ef923214 PM |
1766 | u64 ev; |
1767 | unsigned long flags; | |
cdd6c482 IM |
1768 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1769 | u64 events[MAX_HWEVENTS]; | |
1770 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1771 | int n; |
7595d63b | 1772 | int err; |
cdd6c482 | 1773 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1774 | |
1775 | if (!ppmu) | |
b0a873eb PZ |
1776 | return -ENOENT; |
1777 | ||
3925f46b AK |
1778 | if (has_branch_stack(event)) { |
1779 | /* PMU has BHRB enabled */ | |
4d9690dd | 1780 | if (!(ppmu->flags & PPMU_ARCH_207S)) |
3925f46b AK |
1781 | return -EOPNOTSUPP; |
1782 | } | |
2481c5fa | 1783 | |
cdd6c482 | 1784 | switch (event->attr.type) { |
106b506c | 1785 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1786 | ev = event->attr.config; |
9aaa131a | 1787 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1788 | return -EOPNOTSUPP; |
4574910e | 1789 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1790 | break; |
1791 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1792 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1793 | if (err) |
b0a873eb | 1794 | return err; |
106b506c PM |
1795 | break; |
1796 | case PERF_TYPE_RAW: | |
cdd6c482 | 1797 | ev = event->attr.config; |
106b506c | 1798 | break; |
90c8f954 | 1799 | default: |
b0a873eb | 1800 | return -ENOENT; |
4574910e | 1801 | } |
b0a873eb | 1802 | |
cdd6c482 IM |
1803 | event->hw.config_base = ev; |
1804 | event->hw.idx = 0; | |
4574910e | 1805 | |
0475f9ea PM |
1806 | /* |
1807 | * If we are not running on a hypervisor, force the | |
1808 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1809 | * the user set it to. |
0475f9ea PM |
1810 | */ |
1811 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1812 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1813 | |
1814 | /* | |
cdd6c482 | 1815 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1816 | * PM_RUN_* events interchangeably with their non RUN_* |
1817 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1818 | * XXX we should check if the task is an idle task. | |
1819 | */ | |
1820 | flags = 0; | |
57fa7214 | 1821 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1822 | flags |= PPMU_ONLY_COUNT_RUN; |
1823 | ||
1824 | /* | |
cdd6c482 IM |
1825 | * If this machine has limited events, check whether this |
1826 | * event_id could go on a limited event. | |
ab7ef2e5 | 1827 | */ |
0bbd0d4b | 1828 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1829 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1830 | flags |= PPMU_LIMITED_PMC_OK; |
1831 | } else if (ppmu->limited_pmc_event(ev)) { | |
1832 | /* | |
cdd6c482 | 1833 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1834 | * but we can't use a limited PMC; see if any |
1835 | * alternative goes on a normal PMC. | |
1836 | */ | |
1837 | ev = normal_pmc_alternative(ev, flags); | |
1838 | if (!ev) | |
b0a873eb | 1839 | return -EINVAL; |
ab7ef2e5 PM |
1840 | } |
1841 | } | |
1842 | ||
330a1eb7 ME |
1843 | /* Extra checks for EBB */ |
1844 | err = ebb_event_check(event); | |
1845 | if (err) | |
1846 | return err; | |
1847 | ||
4574910e PM |
1848 | /* |
1849 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1850 | * other hardware events in the group. We assume the event |
4574910e PM |
1851 | * hasn't been linked into its leader's sibling list at this point. |
1852 | */ | |
1853 | n = 0; | |
cdd6c482 | 1854 | if (event->group_leader != event) { |
a8f90e90 | 1855 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1856 | ctrs, events, cflags); |
4574910e | 1857 | if (n < 0) |
b0a873eb | 1858 | return -EINVAL; |
4574910e | 1859 | } |
0475f9ea | 1860 | events[n] = ev; |
cdd6c482 | 1861 | ctrs[n] = event; |
ab7ef2e5 PM |
1862 | cflags[n] = flags; |
1863 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1864 | return -EINVAL; |
e51ee31e | 1865 | |
cdd6c482 | 1866 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1867 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
3925f46b AK |
1868 | |
1869 | if (has_branch_stack(event)) { | |
1870 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( | |
1871 | event->attr.branch_sample_type); | |
1872 | ||
68de8867 JS |
1873 | if (cpuhw->bhrb_filter == -1) { |
1874 | put_cpu_var(cpu_hw_events); | |
3925f46b | 1875 | return -EOPNOTSUPP; |
68de8867 | 1876 | } |
3925f46b AK |
1877 | } |
1878 | ||
cdd6c482 | 1879 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1880 | if (err) |
b0a873eb | 1881 | return -EINVAL; |
4574910e | 1882 | |
cdd6c482 IM |
1883 | event->hw.config = events[n]; |
1884 | event->hw.event_base = cflags[n]; | |
1885 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1886 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b | 1887 | |
330a1eb7 ME |
1888 | /* |
1889 | * For EBB events we just context switch the PMC value, we don't do any | |
1890 | * of the sample_period logic. We use hw.prev_count for this. | |
1891 | */ | |
1892 | if (is_ebb_event(event)) | |
1893 | local64_set(&event->hw.prev_count, 0); | |
1894 | ||
7595d63b PM |
1895 | /* |
1896 | * See if we need to reserve the PMU. | |
cdd6c482 | 1897 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1898 | * mutex to ensure that we don't race with another task doing |
1899 | * reserve_pmc_hardware or release_pmc_hardware. | |
1900 | */ | |
1901 | err = 0; | |
cdd6c482 | 1902 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1903 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1904 | if (atomic_read(&num_events) == 0 && |
1905 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1906 | err = -EBUSY; |
1907 | else | |
cdd6c482 | 1908 | atomic_inc(&num_events); |
7595d63b PM |
1909 | mutex_unlock(&pmc_reserve_mutex); |
1910 | } | |
cdd6c482 | 1911 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1912 | |
b0a873eb | 1913 | return err; |
4574910e PM |
1914 | } |
1915 | ||
35edc2a5 PZ |
1916 | static int power_pmu_event_idx(struct perf_event *event) |
1917 | { | |
1918 | return event->hw.idx; | |
1919 | } | |
1920 | ||
1c53a270 SB |
1921 | ssize_t power_events_sysfs_show(struct device *dev, |
1922 | struct device_attribute *attr, char *page) | |
1923 | { | |
1924 | struct perf_pmu_events_attr *pmu_attr; | |
1925 | ||
1926 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
1927 | ||
1928 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
1929 | } | |
1930 | ||
e51df2c1 | 1931 | static struct pmu power_pmu = { |
a4eaf7f1 PZ |
1932 | .pmu_enable = power_pmu_enable, |
1933 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1934 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1935 | .add = power_pmu_add, |
1936 | .del = power_pmu_del, | |
1937 | .start = power_pmu_start, | |
1938 | .stop = power_pmu_stop, | |
b0a873eb | 1939 | .read = power_pmu_read, |
b0a873eb PZ |
1940 | .start_txn = power_pmu_start_txn, |
1941 | .cancel_txn = power_pmu_cancel_txn, | |
1942 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1943 | .event_idx = power_pmu_event_idx, |
acba3c7e | 1944 | .sched_task = power_pmu_sched_task, |
b0a873eb PZ |
1945 | }; |
1946 | ||
4574910e | 1947 | /* |
57c0c15b | 1948 | * A counter has overflowed; update its count and record |
4574910e PM |
1949 | * things if requested. Note that interrupts are hard-disabled |
1950 | * here so there is no possibility of being interrupted. | |
1951 | */ | |
cdd6c482 | 1952 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1953 | struct pt_regs *regs) |
4574910e | 1954 | { |
cdd6c482 | 1955 | u64 period = event->hw.sample_period; |
4574910e PM |
1956 | s64 prev, delta, left; |
1957 | int record = 0; | |
1958 | ||
a4eaf7f1 PZ |
1959 | if (event->hw.state & PERF_HES_STOPPED) { |
1960 | write_pmc(event->hw.idx, 0); | |
1961 | return; | |
1962 | } | |
1963 | ||
4574910e | 1964 | /* we don't have to worry about interrupts here */ |
e7850595 | 1965 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 1966 | delta = check_and_compute_delta(prev, val); |
e7850595 | 1967 | local64_add(delta, &event->count); |
4574910e PM |
1968 | |
1969 | /* | |
cdd6c482 | 1970 | * See if the total period for this event has expired, |
4574910e PM |
1971 | * and update for the next period. |
1972 | */ | |
1973 | val = 0; | |
e7850595 | 1974 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
1975 | if (delta == 0) |
1976 | left++; | |
60db5e09 | 1977 | if (period) { |
4574910e | 1978 | if (left <= 0) { |
60db5e09 | 1979 | left += period; |
4574910e | 1980 | if (left <= 0) |
60db5e09 | 1981 | left = period; |
e6878835 | 1982 | record = siar_valid(regs); |
4bca770e | 1983 | event->hw.last_period = event->hw.sample_period; |
4574910e | 1984 | } |
98fb1807 PM |
1985 | if (left < 0x80000000LL) |
1986 | val = 0x80000000LL - left; | |
4574910e | 1987 | } |
4574910e | 1988 | |
a4eaf7f1 PZ |
1989 | write_pmc(event->hw.idx, val); |
1990 | local64_set(&event->hw.prev_count, val); | |
1991 | local64_set(&event->hw.period_left, left); | |
1992 | perf_event_update_userpage(event); | |
1993 | ||
4574910e PM |
1994 | /* |
1995 | * Finally record data if requested. | |
1996 | */ | |
0bbd0d4b | 1997 | if (record) { |
dc1d628a PZ |
1998 | struct perf_sample_data data; |
1999 | ||
fd0d000b | 2000 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 2001 | |
cdd6c482 | 2002 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
2003 | perf_get_data_addr(regs, &data.addr); |
2004 | ||
3925f46b AK |
2005 | if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { |
2006 | struct cpu_hw_events *cpuhw; | |
69111bac | 2007 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
3925f46b AK |
2008 | power_pmu_bhrb_read(cpuhw); |
2009 | data.br_stack = &cpuhw->bhrb_stack; | |
2010 | } | |
2011 | ||
a8b0ca17 | 2012 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 2013 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
2014 | } |
2015 | } | |
2016 | ||
2017 | /* | |
2018 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 2019 | * for an event_id. |
0bbd0d4b PM |
2020 | */ |
2021 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2022 | { | |
98fb1807 | 2023 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 2024 | |
98fb1807 PM |
2025 | if (flags) |
2026 | return flags; | |
cdd6c482 IM |
2027 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
2028 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
2029 | } |
2030 | ||
2031 | /* | |
2032 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 2033 | * for an event_id. |
0bbd0d4b PM |
2034 | */ |
2035 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
2036 | { | |
33904054 | 2037 | bool use_siar = regs_use_siar(regs); |
0bbd0d4b | 2038 | |
e6878835 | 2039 | if (use_siar && siar_valid(regs)) |
75382aa7 | 2040 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 2041 | else if (use_siar) |
2042 | return 0; // no valid instruction pointer | |
75382aa7 | 2043 | else |
1ce447b9 | 2044 | return regs->nip; |
4574910e PM |
2045 | } |
2046 | ||
bc09c219 | 2047 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 2048 | { |
0837e324 AB |
2049 | /* |
2050 | * Events on POWER7 can roll back if a speculative event doesn't | |
2051 | * eventually complete. Unfortunately in some rare cases they will | |
2052 | * raise a performance monitor exception. We need to catch this to | |
2053 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
2054 | * cycles from overflow. | |
2055 | * | |
2056 | * We only do this if the first pass fails to find any overflowing | |
2057 | * PMCs because a user might set a period of less than 256 and we | |
2058 | * don't want to mistakenly reset them. | |
2059 | */ | |
bc09c219 MN |
2060 | if ((0x80000000 - val) <= 256) |
2061 | return true; | |
2062 | ||
2063 | return false; | |
2064 | } | |
2065 | ||
2066 | static bool pmc_overflow(unsigned long val) | |
2067 | { | |
2068 | if ((int)val < 0) | |
0837e324 AB |
2069 | return true; |
2070 | ||
2071 | return false; | |
2072 | } | |
2073 | ||
4574910e PM |
2074 | /* |
2075 | * Performance monitor interrupt stuff | |
2076 | */ | |
cdd6c482 | 2077 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 2078 | { |
bc09c219 | 2079 | int i, j; |
69111bac | 2080 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 2081 | struct perf_event *event; |
bc09c219 MN |
2082 | unsigned long val[8]; |
2083 | int found, active; | |
ca8f2d7f PM |
2084 | int nmi; |
2085 | ||
ab7ef2e5 | 2086 | if (cpuhw->n_limited) |
a8f90e90 | 2087 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
2088 | mfspr(SPRN_PMC6)); |
2089 | ||
98fb1807 | 2090 | perf_read_regs(regs); |
0bbd0d4b | 2091 | |
98fb1807 | 2092 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
2093 | if (nmi) |
2094 | nmi_enter(); | |
2095 | else | |
2096 | irq_enter(); | |
4574910e | 2097 | |
bc09c219 MN |
2098 | /* Read all the PMCs since we'll need them a bunch of times */ |
2099 | for (i = 0; i < ppmu->n_counter; ++i) | |
2100 | val[i] = read_pmc(i + 1); | |
2101 | ||
2102 | /* Try to find what caused the IRQ */ | |
2103 | found = 0; | |
2104 | for (i = 0; i < ppmu->n_counter; ++i) { | |
2105 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 2106 | continue; |
bc09c219 MN |
2107 | if (is_limited_pmc(i + 1)) |
2108 | continue; /* these won't generate IRQs */ | |
2109 | /* | |
2110 | * We've found one that's overflowed. For active | |
2111 | * counters we need to log this. For inactive | |
2112 | * counters, we need to reset it anyway | |
2113 | */ | |
2114 | found = 1; | |
2115 | active = 0; | |
2116 | for (j = 0; j < cpuhw->n_events; ++j) { | |
2117 | event = cpuhw->event[j]; | |
2118 | if (event->hw.idx == (i + 1)) { | |
2119 | active = 1; | |
2120 | record_and_restart(event, val[i], regs); | |
2121 | break; | |
2122 | } | |
4574910e | 2123 | } |
bc09c219 MN |
2124 | if (!active) |
2125 | /* reset non active counters that have overflowed */ | |
2126 | write_pmc(i + 1, 0); | |
4574910e | 2127 | } |
bc09c219 MN |
2128 | if (!found && pvr_version_is(PVR_POWER7)) { |
2129 | /* check active counters for special buggy p7 overflow */ | |
2130 | for (i = 0; i < cpuhw->n_events; ++i) { | |
2131 | event = cpuhw->event[i]; | |
2132 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 2133 | continue; |
bc09c219 MN |
2134 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
2135 | /* event has overflowed in a buggy way*/ | |
2136 | found = 1; | |
2137 | record_and_restart(event, | |
2138 | val[event->hw.idx - 1], | |
2139 | regs); | |
2140 | } | |
4574910e PM |
2141 | } |
2142 | } | |
6772faa1 | 2143 | if (!found && !nmi && printk_ratelimit()) |
bc09c219 | 2144 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); |
4574910e PM |
2145 | |
2146 | /* | |
2147 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 2148 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 2149 | * and thus allow interrupts to occur again. |
cdd6c482 | 2150 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
2151 | * we get back out of this interrupt. |
2152 | */ | |
ab7ef2e5 | 2153 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 2154 | |
ca8f2d7f PM |
2155 | if (nmi) |
2156 | nmi_exit(); | |
2157 | else | |
db4fb5ac | 2158 | irq_exit(); |
4574910e PM |
2159 | } |
2160 | ||
57ecde42 | 2161 | int power_pmu_prepare_cpu(unsigned int cpu) |
01d0287f | 2162 | { |
cdd6c482 | 2163 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 2164 | |
57ecde42 TG |
2165 | if (ppmu) { |
2166 | memset(cpuhw, 0, sizeof(*cpuhw)); | |
2167 | cpuhw->mmcr[0] = MMCR0_FC; | |
3f6da390 | 2168 | } |
57ecde42 | 2169 | return 0; |
3f6da390 PZ |
2170 | } |
2171 | ||
061d19f2 | 2172 | int register_power_pmu(struct power_pmu *pmu) |
4574910e | 2173 | { |
079b3c56 PM |
2174 | if (ppmu) |
2175 | return -EBUSY; /* something's already registered */ | |
2176 | ||
2177 | ppmu = pmu; | |
2178 | pr_info("%s performance monitor hardware support registered\n", | |
2179 | pmu->name); | |
d095cd46 | 2180 | |
1c53a270 SB |
2181 | power_pmu.attr_groups = ppmu->attr_groups; |
2182 | ||
98fb1807 | 2183 | #ifdef MSR_HV |
d095cd46 PM |
2184 | /* |
2185 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
2186 | */ | |
2187 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 2188 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 2189 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 2190 | |
2e80a82a | 2191 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
57ecde42 TG |
2192 | cpuhp_setup_state(CPUHP_PERF_POWER, "PERF_POWER", |
2193 | power_pmu_prepare_cpu, NULL); | |
4574910e PM |
2194 | return 0; |
2195 | } |