[deliverable/linux.git] / arch / powerpc / perf / power7-pmu.c

/*
 * Performance counter support for POWER7 processors.
 *
 * Copyright 2009 Paul Mackerras, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/kernel.h>
#include <linux/perf_event.h>
#include <linux/string.h>
#include <asm/reg.h>
#include <asm/cputable.h>

/*
 * Bits in event code for POWER7
 */
#define PM_PMC_SH	16	/* PMC number (1-based) for direct events */
#define PM_PMC_MSK	0xf
#define PM_PMC_MSKS	(PM_PMC_MSK << PM_PMC_SH)
#define PM_UNIT_SH	12	/* TTMMUX number and setting - unit select */
#define PM_UNIT_MSK	0xf
#define PM_COMBINE_SH	11	/* Combined event bit */
#define PM_COMBINE_MSK	1
#define PM_COMBINE_MSKS	0x800
#define PM_L2SEL_SH	8	/* L2 event select */
#define PM_L2SEL_MSK	7
#define PM_PMCSEL_MSK	0xff

/*
 * Bits in MMCR1 for POWER7
 */
#define MMCR1_TTM0SEL_SH	60
#define MMCR1_TTM1SEL_SH	56
#define MMCR1_TTM2SEL_SH	52
#define MMCR1_TTM3SEL_SH	48
#define MMCR1_TTMSEL_MSK	0xf
#define MMCR1_L2SEL_SH		45
#define MMCR1_L2SEL_MSK		7
#define MMCR1_PMC1_COMBINE_SH	35
#define MMCR1_PMC2_COMBINE_SH	34
#define MMCR1_PMC3_COMBINE_SH	33
#define MMCR1_PMC4_COMBINE_SH	32
#define MMCR1_PMC1SEL_SH	24
#define MMCR1_PMC2SEL_SH	16
#define MMCR1_PMC3SEL_SH	8
#define MMCR1_PMC4SEL_SH	0
#define MMCR1_PMCSEL_SH(n)	(MMCR1_PMC1SEL_SH - (n) * 8)
#define MMCR1_PMCSEL_MSK	0xff

/*
 * Power7 event codes.
 */
#define	PME_PM_CYC			0x1e
#define	PME_PM_GCT_NOSLOT_CYC		0x100f8
#define	PME_PM_CMPLU_STALL		0x4000a
#define	PME_PM_INST_CMPL		0x2
#define	PME_PM_LD_REF_L1		0xc880
#define	PME_PM_LD_MISS_L1		0x400f0
#define	PME_PM_BRU_FIN			0x10068
#define	PME_PM_BRU_MPRED		0x400f6

/*
 * Layout of constraint bits:
 * 6666555555555544444444443333333333222222222211111111110000000000
 * 3210987654321098765432109876543210987654321098765432109876543210
 *                                              < ><  ><><><><><><>
 *                                              L2  NC P6P5P4P3P2P1
 *
 * L2 - 16-18 - Required L2SEL value (select field)
 *
 * NC - number of counters
 *     15: NC error 0x8000
 *     12-14: number of events needing PMC1-4 0x7000
 *
 * P6
 *     11: P6 error 0x800
 *     10-11: Count of events needing PMC6
 *
 * P1..P5
 *     0-9: Count of events needing PMC1..PMC5
 */

static int power7_get_constraint(u64 event, unsigned long *maskp,
				 unsigned long *valp)
{
	int pmc, sh, unit;
	unsigned long mask = 0, value = 0;

	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	if (pmc) {
		if (pmc > 6)
			return -1;
		sh = (pmc - 1) * 2;
		mask |= 2 << sh;
		value |= 1 << sh;
		if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4))
			return -1;
	}
	if (pmc < 5) {
		/* need a counter from PMC1-4 set */
		mask  |= 0x8000;
		value |= 0x1000;
	}

	unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
	if (unit == 6) {
		/* L2SEL must be identical across events */
		int l2sel = (event >> PM_L2SEL_SH) & PM_L2SEL_MSK;
		mask  |= 0x7 << 16;
		value |= l2sel << 16;
	}

	*maskp = mask;
	*valp = value;
	return 0;
}

#define MAX_ALT	2	/* at most 2 alternatives for any event */

static const unsigned int event_alternatives[][MAX_ALT] = {
	{ 0x200f2, 0x300f2 },		/* PM_INST_DISP */
	{ 0x200f4, 0x600f4 },		/* PM_RUN_CYC */
	{ 0x400fa, 0x500fa },		/* PM_RUN_INST_CMPL */
};

/*
 * Scan the alternatives table for a match and return the
 * index into the alternatives table if found, else -1.
 */
static int find_alternative(u64 event)
{
	int i, j;

	for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
		if (event < event_alternatives[i][0])
			break;
		for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
			if (event == event_alternatives[i][j])
				return i;
	}
	return -1;
}

static s64 find_alternative_decode(u64 event)
{
	int pmc, psel;

	/* this only handles the 4x decode events */
	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	psel = event & PM_PMCSEL_MSK;
	if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40)
		return event - (1 << PM_PMC_SH) + 8;
	if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48)
		return event + (1 << PM_PMC_SH) - 8;
	return -1;
}

static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
{
	int i, j, nalt = 1;
	s64 ae;

	alt[0] = event;
	nalt = 1;
	i = find_alternative(event);
	if (i >= 0) {
		for (j = 0; j < MAX_ALT; ++j) {
			ae = event_alternatives[i][j];
			if (ae && ae != event)
				alt[nalt++] = ae;
		}
	} else {
		ae = find_alternative_decode(event);
		if (ae > 0)
			alt[nalt++] = ae;
	}

	if (flags & PPMU_ONLY_COUNT_RUN) {
		/*
		 * We're only counting in RUN state,
		 * so PM_CYC is equivalent to PM_RUN_CYC
		 * and PM_INST_CMPL === PM_RUN_INST_CMPL.
		 * This doesn't include alternatives that don't provide
		 * any extra flexibility in assigning PMCs.
		 */
		j = nalt;
		for (i = 0; i < nalt; ++i) {
			switch (alt[i]) {
			case 0x1e:	/* PM_CYC */
				alt[j++] = 0x600f4;	/* PM_RUN_CYC */
				break;
			case 0x600f4:	/* PM_RUN_CYC */
				alt[j++] = 0x1e;
				break;
			case 0x2:	/* PM_PPC_CMPL */
				alt[j++] = 0x500fa;	/* PM_RUN_INST_CMPL */
				break;
			case 0x500fa:	/* PM_RUN_INST_CMPL */
				alt[j++] = 0x2;	/* PM_PPC_CMPL */
				break;
			}
		}
		nalt = j;
	}

	return nalt;
}

/*
 * Returns 1 if event counts things relating to marked instructions
 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
 */
static int power7_marked_instr_event(u64 event)
{
	int pmc, psel;
	int unit;

	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
	psel = event & PM_PMCSEL_MSK & ~1;	/* trim off edge/level bit */
	if (pmc >= 5)
		return 0;

	switch (psel >> 4) {
	case 2:
		return pmc == 2 || pmc == 4;
	case 3:
		if (psel == 0x3c)
			return pmc == 1;
		if (psel == 0x3e)
			return pmc != 2;
		return 1;
	case 4:
	case 5:
		return unit == 0xd;
	case 6:
		if (psel == 0x64)
			return pmc >= 3;
	case 8:
		return unit == 0xd;
	}
	return 0;
}

static int power7_compute_mmcr(u64 event[], int n_ev,
			       unsigned int hwc[], unsigned long mmcr[])
{
	unsigned long mmcr1 = 0;
	unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
	unsigned int pmc, unit, combine, l2sel, psel;
	unsigned int pmc_inuse = 0;
	int i;

	/* First pass to count resource use */
	for (i = 0; i < n_ev; ++i) {
		pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
		if (pmc) {
			if (pmc > 6)
				return -1;
			if (pmc_inuse & (1 << (pmc - 1)))
				return -1;
			pmc_inuse |= 1 << (pmc - 1);
		}
	}

	/* Second pass: assign PMCs, set all MMCR1 fields */
	for (i = 0; i < n_ev; ++i) {
		pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
		unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
		combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK;
		l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK;
		psel = event[i] & PM_PMCSEL_MSK;
		if (!pmc) {
			/* Bus event or any-PMC direct event */
			for (pmc = 0; pmc < 4; ++pmc) {
				if (!(pmc_inuse & (1 << pmc)))
					break;
			}
			if (pmc >= 4)
				return -1;
			pmc_inuse |= 1 << pmc;
		} else {
			/* Direct or decoded event */
			--pmc;
		}
		if (pmc <= 3) {
			mmcr1 |= (unsigned long) unit
				<< (MMCR1_TTM0SEL_SH - 4 * pmc);
			mmcr1 |= (unsigned long) combine
				<< (MMCR1_PMC1_COMBINE_SH - pmc);
			mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
			if (unit == 6)	/* L2 events */
				mmcr1 |= (unsigned long) l2sel
					<< MMCR1_L2SEL_SH;
		}
		if (power7_marked_instr_event(event[i]))
			mmcra |= MMCRA_SAMPLE_ENABLE;
		hwc[i] = pmc;
	}

	/* Return MMCRx values */
	mmcr[0] = 0;
	if (pmc_inuse & 1)
		mmcr[0] = MMCR0_PMC1CE;
	if (pmc_inuse & 0x3e)
		mmcr[0] |= MMCR0_PMCjCE;
	mmcr[1] = mmcr1;
	mmcr[2] = mmcra;
	return 0;
}

static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
{
	if (pmc <= 3)
		mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
}

static int power7_generic_events[] = {
	[PERF_COUNT_HW_CPU_CYCLES] =			PME_PM_CYC,
	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =	PME_PM_GCT_NOSLOT_CYC,
	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =	PME_PM_CMPLU_STALL,
	[PERF_COUNT_HW_INSTRUCTIONS] =			PME_PM_INST_CMPL,
	[PERF_COUNT_HW_CACHE_REFERENCES] =		PME_PM_LD_REF_L1,
	[PERF_COUNT_HW_CACHE_MISSES] =			PME_PM_LD_MISS_L1,
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =		PME_PM_BRU_FIN,
	[PERF_COUNT_HW_BRANCH_MISSES] =			PME_PM_BRU_MPRED,
};

#define C(x)	PERF_COUNT_HW_CACHE_##x

/*
 * Table of generalized cache-related events.
 * 0 means not supported, -1 means nonsensical, other values
 * are event codes.
 */
static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0xc880,		0x400f0	},
		[C(OP_WRITE)] = {	0,		0x300f0	},
		[C(OP_PREFETCH)] = {	0xd8b8,		0	},
	},
	[C(L1I)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0,		0x200fc	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	0x408a,		0	},
	},
	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0x16080,	0x26080	},
		[C(OP_WRITE)] = {	0x16082,	0x26082	},
		[C(OP_PREFETCH)] = {	0,		0	},
	},
	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0,		0x300fc	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
	[C(ITLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0,		0x400fc	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
	[C(BPU)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0x10068,	0x400f6	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
	[C(NODE)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	-1,		-1	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
};


GENERIC_EVENT_ATTR(cpu-cycles,			CYC);
GENERIC_EVENT_ATTR(stalled-cycles-frontend,	GCT_NOSLOT_CYC);
GENERIC_EVENT_ATTR(stalled-cycles-backend,	CMPLU_STALL);
GENERIC_EVENT_ATTR(instructions,		INST_CMPL);
GENERIC_EVENT_ATTR(cache-references,		LD_REF_L1);
GENERIC_EVENT_ATTR(cache-misses,		LD_MISS_L1);
GENERIC_EVENT_ATTR(branch-instructions,		BRU_FIN);
GENERIC_EVENT_ATTR(branch-misses,		BRU_MPRED);

POWER_EVENT_ATTR(CYC,				CYC);
POWER_EVENT_ATTR(GCT_NOSLOT_CYC,		GCT_NOSLOT_CYC);
POWER_EVENT_ATTR(CMPLU_STALL,			CMPLU_STALL);
POWER_EVENT_ATTR(INST_CMPL,			INST_CMPL);
POWER_EVENT_ATTR(LD_REF_L1,			LD_REF_L1);
POWER_EVENT_ATTR(LD_MISS_L1,			LD_MISS_L1);
POWER_EVENT_ATTR(BRU_FIN,			BRU_FIN)
POWER_EVENT_ATTR(BRU_MPRED,			BRU_MPRED);

static struct attribute *power7_events_attr[] = {
	GENERIC_EVENT_PTR(CYC),
	GENERIC_EVENT_PTR(GCT_NOSLOT_CYC),
	GENERIC_EVENT_PTR(CMPLU_STALL),
	GENERIC_EVENT_PTR(INST_CMPL),
	GENERIC_EVENT_PTR(LD_REF_L1),
	GENERIC_EVENT_PTR(LD_MISS_L1),
	GENERIC_EVENT_PTR(BRU_FIN),
	GENERIC_EVENT_PTR(BRU_MPRED),

	POWER_EVENT_PTR(CYC),
	POWER_EVENT_PTR(GCT_NOSLOT_CYC),
	POWER_EVENT_PTR(CMPLU_STALL),
	POWER_EVENT_PTR(INST_CMPL),
	POWER_EVENT_PTR(LD_REF_L1),
	POWER_EVENT_PTR(LD_MISS_L1),
	POWER_EVENT_PTR(BRU_FIN),
	POWER_EVENT_PTR(BRU_MPRED),
	NULL
};


static struct attribute_group power7_pmu_events_group = {
	.name = "events",
	.attrs = power7_events_attr,
};

PMU_FORMAT_ATTR(event, "config:0-19");

static struct attribute *power7_pmu_format_attr[] = {
	&format_attr_event.attr,
	NULL,
};

struct attribute_group power7_pmu_format_group = {
	.name = "format",
	.attrs = power7_pmu_format_attr,
};

static const struct attribute_group *power7_pmu_attr_groups[] = {
	&power7_pmu_format_group,
	&power7_pmu_events_group,
	NULL,
};

static struct power_pmu power7_pmu = {
	.name			= "POWER7",
	.n_counter		= 6,
	.max_alternatives	= MAX_ALT + 1,
	.add_fields		= 0x1555ul,
	.test_adder		= 0x3000ul,
	.compute_mmcr		= power7_compute_mmcr,
	.get_constraint		= power7_get_constraint,
	.get_alternatives	= power7_get_alternatives,
	.disable_pmc		= power7_disable_pmc,
	.flags			= PPMU_ALT_SIPR,
	.attr_groups		= power7_pmu_attr_groups,
	.n_generic		= ARRAY_SIZE(power7_generic_events),
	.generic_events		= power7_generic_events,
	.cache_events		= &power7_cache_events,
};

static int __init init_power7_pmu(void)
{
	if (!cur_cpu_spec->oprofile_cpu_type ||
	    strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
		return -ENODEV;

	if (pvr_version_is(PVR_POWER7p))
		power7_pmu.flags |= PPMU_SIAR_VALID;

	return register_power_pmu(&power7_pmu);
}

early_initcall(init_power7_pmu);
Commit	Line	Data
4da52960 PM	1	/*
	2	* Performance counter support for POWER7 processors.
	3	*
	4	* Copyright 2009 Paul Mackerras, IBM Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11	#include <linux/kernel.h>
cdd6c482	12	#include <linux/perf_event.h>
079b3c56	13	#include <linux/string.h>
4da52960	14	#include <asm/reg.h>
079b3c56	15	#include <asm/cputable.h>
4da52960 PM	16
	17	/*
	18	* Bits in event code for POWER7
	19	*/
	20	#define PM_PMC_SH 16 /* PMC number (1-based) for direct events */
	21	#define PM_PMC_MSK 0xf
	22	#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
	23	#define PM_UNIT_SH 12 /* TTMMUX number and setting - unit select */
	24	#define PM_UNIT_MSK 0xf
	25	#define PM_COMBINE_SH 11 /* Combined event bit */
	26	#define PM_COMBINE_MSK 1
	27	#define PM_COMBINE_MSKS 0x800
	28	#define PM_L2SEL_SH 8 /* L2 event select */
	29	#define PM_L2SEL_MSK 7
	30	#define PM_PMCSEL_MSK 0xff
	31
	32	/*
	33	* Bits in MMCR1 for POWER7
	34	*/
	35	#define MMCR1_TTM0SEL_SH 60
	36	#define MMCR1_TTM1SEL_SH 56
	37	#define MMCR1_TTM2SEL_SH 52
	38	#define MMCR1_TTM3SEL_SH 48
	39	#define MMCR1_TTMSEL_MSK 0xf
	40	#define MMCR1_L2SEL_SH 45
	41	#define MMCR1_L2SEL_MSK 7
	42	#define MMCR1_PMC1_COMBINE_SH 35
	43	#define MMCR1_PMC2_COMBINE_SH 34
	44	#define MMCR1_PMC3_COMBINE_SH 33
	45	#define MMCR1_PMC4_COMBINE_SH 32
	46	#define MMCR1_PMC1SEL_SH 24
	47	#define MMCR1_PMC2SEL_SH 16
	48	#define MMCR1_PMC3SEL_SH 8
	49	#define MMCR1_PMC4SEL_SH 0
	50	#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
	51	#define MMCR1_PMCSEL_MSK 0xff
	52
bbdc7aa4 SB	53	/*
	54	* Power7 event codes.
	55	*/
	56	#define PME_PM_CYC 0x1e
	57	#define PME_PM_GCT_NOSLOT_CYC 0x100f8
	58	#define PME_PM_CMPLU_STALL 0x4000a
	59	#define PME_PM_INST_CMPL 0x2
	60	#define PME_PM_LD_REF_L1 0xc880
	61	#define PME_PM_LD_MISS_L1 0x400f0
	62	#define PME_PM_BRU_FIN 0x10068
	63	#define PME_PM_BRU_MPRED 0x400f6
	64
4da52960 PM	65	/*
	66	* Layout of constraint bits:
	67	* 6666555555555544444444443333333333222222222211111111110000000000
	68	* 3210987654321098765432109876543210987654321098765432109876543210
da111957 ME	69	* < >< ><><><><><><>
	70	* L2 NC P6P5P4P3P2P1
	71	*
	72	* L2 - 16-18 - Required L2SEL value (select field)
4da52960 PM	73	*
	74	* NC - number of counters
	75	* 15: NC error 0x8000
	76	* 12-14: number of events needing PMC1-4 0x7000
	77	*
	78	* P6
	79	* 11: P6 error 0x800
	80	* 10-11: Count of events needing PMC6
	81	*
	82	* P1..P5
	83	* 0-9: Count of events needing PMC1..PMC5
	84	*/
	85
448d64f8 PM	86	static int power7_get_constraint(u64 event, unsigned long *maskp,
448d64f8 PM	87	unsigned long *valp)
4da52960	88	{
da111957	89	int pmc, sh, unit;
448d64f8	90	unsigned long mask = 0, value = 0;
4da52960 PM	91
	92	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	93	if (pmc) {
	94	if (pmc > 6)
	95	return -1;
	96	sh = (pmc - 1) * 2;
	97	mask \|= 2 << sh;
	98	value \|= 1 << sh;
	99	if (pmc >= 5 && !(event == 0x500fa \|\| event == 0x600f4))
	100	return -1;
	101	}
	102	if (pmc < 5) {
	103	/* need a counter from PMC1-4 set */
	104	mask \|= 0x8000;
	105	value \|= 0x1000;
	106	}
da111957 ME	107
	108	unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
	109	if (unit == 6) {
	110	/* L2SEL must be identical across events */
	111	int l2sel = (event >> PM_L2SEL_SH) & PM_L2SEL_MSK;
	112	mask \|= 0x7 << 16;
	113	value \|= l2sel << 16;
	114	}
	115
4da52960 PM	116	*maskp = mask;
	117	*valp = value;
	118	return 0;
	119	}
	120
	121	#define MAX_ALT 2 /* at most 2 alternatives for any event */
	122
	123	static const unsigned int event_alternatives[][MAX_ALT] = {
	124	{ 0x200f2, 0x300f2 }, /* PM_INST_DISP */
	125	{ 0x200f4, 0x600f4 }, /* PM_RUN_CYC */
	126	{ 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */
	127	};
	128
	129	/*
	130	* Scan the alternatives table for a match and return the
	131	* index into the alternatives table if found, else -1.
	132	*/
	133	static int find_alternative(u64 event)
	134	{
	135	int i, j;
	136
	137	for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
	138	if (event < event_alternatives[i][0])
	139	break;
	140	for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
	141	if (event == event_alternatives[i][j])
	142	return i;
	143	}
	144	return -1;
	145	}
	146
	147	static s64 find_alternative_decode(u64 event)
	148	{
	149	int pmc, psel;
	150
	151	/* this only handles the 4x decode events */
	152	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	153	psel = event & PM_PMCSEL_MSK;
	154	if ((pmc == 2 \|\| pmc == 4) && (psel & ~7) == 0x40)
	155	return event - (1 << PM_PMC_SH) + 8;
	156	if ((pmc == 1 \|\| pmc == 3) && (psel & ~7) == 0x48)
	157	return event + (1 << PM_PMC_SH) - 8;
	158	return -1;
	159	}
	160
	161	static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
	162	{
	163	int i, j, nalt = 1;
	164	s64 ae;
	165
	166	alt[0] = event;
	167	nalt = 1;
	168	i = find_alternative(event);
	169	if (i >= 0) {
	170	for (j = 0; j < MAX_ALT; ++j) {
	171	ae = event_alternatives[i][j];
	172	if (ae && ae != event)
	173	alt[nalt++] = ae;
	174	}
	175	} else {
	176	ae = find_alternative_decode(event);
	177	if (ae > 0)
	178	alt[nalt++] = ae;
	179	}
180
181	if (flags & PPMU_ONLY_COUNT_RUN) {
182	/*
183	* We're only counting in RUN state,
184	* so PM_CYC is equivalent to PM_RUN_CYC
185	* and PM_INST_CMPL === PM_RUN_INST_CMPL.
186	* This doesn't include alternatives that don't provide
187	* any extra flexibility in assigning PMCs.
188	*/
189	j = nalt;
190	for (i = 0; i < nalt; ++i) {
191	switch (alt[i]) {
192	case 0x1e: /* PM_CYC */
193	alt[j++] = 0x600f4; /* PM_RUN_CYC */
194	break;
195	case 0x600f4: /* PM_RUN_CYC */
196	alt[j++] = 0x1e;
197	break;
198	case 0x2: /* PM_PPC_CMPL */
199	alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
200	break;
201	case 0x500fa: /* PM_RUN_INST_CMPL */
202	alt[j++] = 0x2; /* PM_PPC_CMPL */
203	break;
204	}
205	}
206	nalt = j;
207	}
208
209	return nalt;
210	}
211
212	/*
213	* Returns 1 if event counts things relating to marked instructions
214	* and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
215	*/
216	static int power7_marked_instr_event(u64 event)
217	{
218	int pmc, psel;
219	int unit;
220
221	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
222	unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
223	psel = event & PM_PMCSEL_MSK & ~1; /* trim off edge/level bit */
224	if (pmc >= 5)
225	return 0;
226
227	switch (psel >> 4) {
228	case 2:
229	return pmc == 2 \|\| pmc == 4;
230	case 3:
231	if (psel == 0x3c)
232	return pmc == 1;
233	if (psel == 0x3e)
234	return pmc != 2;
235	return 1;
236	case 4:
237	case 5:
238	return unit == 0xd;
239	case 6:
240	if (psel == 0x64)
241	return pmc >= 3;
242	case 8:
243	return unit == 0xd;
244	}
245	return 0;
246	}
247
248	static int power7_compute_mmcr(u64 event[], int n_ev,
448d64f8	249	unsigned int hwc[], unsigned long mmcr[])
4da52960	250	{
448d64f8	251	unsigned long mmcr1 = 0;
81cd5ae3	252	unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS \| MMCRA_SDAR_ERAT_MISS;
4da52960 PM	253	unsigned int pmc, unit, combine, l2sel, psel;
	254	unsigned int pmc_inuse = 0;
	255	int i;
	256
	257	/* First pass to count resource use */
	258	for (i = 0; i < n_ev; ++i) {
	259	pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
	260	if (pmc) {
	261	if (pmc > 6)
	262	return -1;
	263	if (pmc_inuse & (1 << (pmc - 1)))
	264	return -1;
	265	pmc_inuse \|= 1 << (pmc - 1);
	266	}
	267	}
	268
	269	/* Second pass: assign PMCs, set all MMCR1 fields */
	270	for (i = 0; i < n_ev; ++i) {
	271	pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
	272	unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
	273	combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK;
	274	l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK;
	275	psel = event[i] & PM_PMCSEL_MSK;
	276	if (!pmc) {
	277	/* Bus event or any-PMC direct event */
	278	for (pmc = 0; pmc < 4; ++pmc) {
	279	if (!(pmc_inuse & (1 << pmc)))
	280	break;
	281	}
	282	if (pmc >= 4)
	283	return -1;
	284	pmc_inuse \|= 1 << pmc;
	285	} else {
	286	/* Direct or decoded event */
	287	--pmc;
	288	}
	289	if (pmc <= 3) {
448d64f8 PM	290	mmcr1 \|= (unsigned long) unit
	291	<< (MMCR1_TTM0SEL_SH - 4 * pmc);
	292	mmcr1 \|= (unsigned long) combine
	293	<< (MMCR1_PMC1_COMBINE_SH - pmc);
4da52960 PM	294	mmcr1 \|= psel << MMCR1_PMCSEL_SH(pmc);
4da52960 PM	295	if (unit == 6) /* L2 events */
448d64f8 PM	296	mmcr1 \|= (unsigned long) l2sel
448d64f8 PM	297	<< MMCR1_L2SEL_SH;
4da52960 PM	298	}
	299	if (power7_marked_instr_event(event[i]))
	300	mmcra \|= MMCRA_SAMPLE_ENABLE;
	301	hwc[i] = pmc;
	302	}
	303
	304	/* Return MMCRx values */
	305	mmcr[0] = 0;
	306	if (pmc_inuse & 1)
	307	mmcr[0] = MMCR0_PMC1CE;
	308	if (pmc_inuse & 0x3e)
	309	mmcr[0] \|= MMCR0_PMCjCE;
	310	mmcr[1] = mmcr1;
	311	mmcr[2] = mmcra;
	312	return 0;
	313	}
	314
448d64f8	315	static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
4da52960 PM	316	{
4da52960 PM	317	if (pmc <= 3)
448d64f8	318	mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
4da52960 PM	319	}
	320
	321	static int power7_generic_events[] = {
bbdc7aa4 SB	322	[PERF_COUNT_HW_CPU_CYCLES] = PME_PM_CYC,
	323	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PME_PM_GCT_NOSLOT_CYC,
	324	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PME_PM_CMPLU_STALL,
	325	[PERF_COUNT_HW_INSTRUCTIONS] = PME_PM_INST_CMPL,
	326	[PERF_COUNT_HW_CACHE_REFERENCES] = PME_PM_LD_REF_L1,
	327	[PERF_COUNT_HW_CACHE_MISSES] = PME_PM_LD_MISS_L1,
	328	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PME_PM_BRU_FIN,
	329	[PERF_COUNT_HW_BRANCH_MISSES] = PME_PM_BRU_MPRED,
4da52960 PM	330	};
4da52960 PM	331
106b506c PM	332	#define C(x) PERF_COUNT_HW_CACHE_##x
	333
	334	/*
	335	* Table of generalized cache-related events.
	336	* 0 means not supported, -1 means nonsensical, other values
	337	* are event codes.
	338	*/
	339	static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
	340	[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
a3df6f7d	341	[C(OP_READ)] = { 0xc880, 0x400f0 },
106b506c PM	342	[C(OP_WRITE)] = { 0, 0x300f0 },
	343	[C(OP_PREFETCH)] = { 0xd8b8, 0 },
	344	},
	345	[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
	346	[C(OP_READ)] = { 0, 0x200fc },
	347	[C(OP_WRITE)] = { -1, -1 },
	348	[C(OP_PREFETCH)] = { 0x408a, 0 },
	349	},
8be6e8f3	350	[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
a3df6f7d PM	351	[C(OP_READ)] = { 0x16080, 0x26080 },
a3df6f7d PM	352	[C(OP_WRITE)] = { 0x16082, 0x26082 },
106b506c PM	353	[C(OP_PREFETCH)] = { 0, 0 },
	354	},
	355	[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
	356	[C(OP_READ)] = { 0, 0x300fc },
	357	[C(OP_WRITE)] = { -1, -1 },
	358	[C(OP_PREFETCH)] = { -1, -1 },
	359	},
	360	[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
	361	[C(OP_READ)] = { 0, 0x400fc },
	362	[C(OP_WRITE)] = { -1, -1 },
	363	[C(OP_PREFETCH)] = { -1, -1 },
	364	},
	365	[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
	366	[C(OP_READ)] = { 0x10068, 0x400f6 },
	367	[C(OP_WRITE)] = { -1, -1 },
	368	[C(OP_PREFETCH)] = { -1, -1 },
	369	},
89d6c0b5 PZ	370	[C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
	371	[C(OP_READ)] = { -1, -1 },
	372	[C(OP_WRITE)] = { -1, -1 },
	373	[C(OP_PREFETCH)] = { -1, -1 },
	374	},
106b506c PM	375	};
106b506c PM	376
1c53a270 SB	377
	378	GENERIC_EVENT_ATTR(cpu-cycles, CYC);
	379	GENERIC_EVENT_ATTR(stalled-cycles-frontend, GCT_NOSLOT_CYC);
	380	GENERIC_EVENT_ATTR(stalled-cycles-backend, CMPLU_STALL);
	381	GENERIC_EVENT_ATTR(instructions, INST_CMPL);
	382	GENERIC_EVENT_ATTR(cache-references, LD_REF_L1);
	383	GENERIC_EVENT_ATTR(cache-misses, LD_MISS_L1);
	384	GENERIC_EVENT_ATTR(branch-instructions, BRU_FIN);
	385	GENERIC_EVENT_ATTR(branch-misses, BRU_MPRED);
	386
886c3b2d SB	387	POWER_EVENT_ATTR(CYC, CYC);
	388	POWER_EVENT_ATTR(GCT_NOSLOT_CYC, GCT_NOSLOT_CYC);
	389	POWER_EVENT_ATTR(CMPLU_STALL, CMPLU_STALL);
	390	POWER_EVENT_ATTR(INST_CMPL, INST_CMPL);
	391	POWER_EVENT_ATTR(LD_REF_L1, LD_REF_L1);
	392	POWER_EVENT_ATTR(LD_MISS_L1, LD_MISS_L1);
	393	POWER_EVENT_ATTR(BRU_FIN, BRU_FIN)
	394	POWER_EVENT_ATTR(BRU_MPRED, BRU_MPRED);
	395
1c53a270 SB	396	static struct attribute *power7_events_attr[] = {
	397	GENERIC_EVENT_PTR(CYC),
	398	GENERIC_EVENT_PTR(GCT_NOSLOT_CYC),
	399	GENERIC_EVENT_PTR(CMPLU_STALL),
	400	GENERIC_EVENT_PTR(INST_CMPL),
	401	GENERIC_EVENT_PTR(LD_REF_L1),
	402	GENERIC_EVENT_PTR(LD_MISS_L1),
	403	GENERIC_EVENT_PTR(BRU_FIN),
	404	GENERIC_EVENT_PTR(BRU_MPRED),
886c3b2d SB	405
	406	POWER_EVENT_PTR(CYC),
	407	POWER_EVENT_PTR(GCT_NOSLOT_CYC),
	408	POWER_EVENT_PTR(CMPLU_STALL),
	409	POWER_EVENT_PTR(INST_CMPL),
	410	POWER_EVENT_PTR(LD_REF_L1),
	411	POWER_EVENT_PTR(LD_MISS_L1),
	412	POWER_EVENT_PTR(BRU_FIN),
	413	POWER_EVENT_PTR(BRU_MPRED),
1c53a270 SB	414	NULL
	415	};
	416
	417
	418	static struct attribute_group power7_pmu_events_group = {
	419	.name = "events",
	420	.attrs = power7_events_attr,
	421	};
	422
3bf7b07e SB	423	PMU_FORMAT_ATTR(event, "config:0-19");
	424
	425	static struct attribute *power7_pmu_format_attr[] = {
	426	&format_attr_event.attr,
	427	NULL,
	428	};
	429
	430	struct attribute_group power7_pmu_format_group = {
	431	.name = "format",
	432	.attrs = power7_pmu_format_attr,
	433	};
	434
1c53a270	435	static const struct attribute_group *power7_pmu_attr_groups[] = {
3bf7b07e	436	&power7_pmu_format_group,
1c53a270 SB	437	&power7_pmu_events_group,
	438	NULL,
	439	};
	440
079b3c56 PM	441	static struct power_pmu power7_pmu = {
079b3c56 PM	442	.name = "POWER7",
448d64f8 PM	443	.n_counter = 6,
	444	.max_alternatives = MAX_ALT + 1,
	445	.add_fields = 0x1555ul,
	446	.test_adder = 0x3000ul,
	447	.compute_mmcr = power7_compute_mmcr,
	448	.get_constraint = power7_get_constraint,
	449	.get_alternatives = power7_get_alternatives,
	450	.disable_pmc = power7_disable_pmc,
0a456fc5	451	.flags = PPMU_ALT_SIPR,
1c53a270	452	.attr_groups = power7_pmu_attr_groups,
448d64f8 PM	453	.n_generic = ARRAY_SIZE(power7_generic_events),
	454	.generic_events = power7_generic_events,
	455	.cache_events = &power7_cache_events,
4da52960	456	};
079b3c56	457
77c2342a	458	static int __init init_power7_pmu(void)
079b3c56	459	{
e0d82a0a BH	460	if (!cur_cpu_spec->oprofile_cpu_type \|\|
e0d82a0a BH	461	strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
079b3c56 PM	462	return -ENODEV;
079b3c56 PM	463
e6878835	464	if (pvr_version_is(PVR_POWER7p))
	465	power7_pmu.flags \|= PPMU_SIAR_VALID;
	466
079b3c56 PM	467	return register_power_pmu(&power7_pmu);
	468	}
	469
004417a6	470	early_initcall(init_power7_pmu);