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Merge branch 'locking-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / powerpc / perf / power8-pmu.c
CommitLineData
e05b9b9e
ME		 1/*
2 * Performance counter support for POWER8 processors.
3 *
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
5 * Copyright 2013 Michael Ellerman, IBM Corporation.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
c2e37a26
ME		 13#define pr_fmt(fmt) "power8-pmu: " fmt
14
e05b9b9e
ME		 15#include <linux/kernel.h>
16#include <linux/perf_event.h>
17#include <asm/firmware.h>
9de5cb0f 18#include <asm/cputable.h>
e05b9b9e 19
e05b9b9e
ME		 20/*
21 * Some power8 event codes.
22 */
e0728b50
SB		 23#define EVENT(_name, _code) _name = _code,
24
25enum {
26#include "power8-events-list.h"
27};
2fdd313f 28
e0728b50 29#undef EVENT
e05b9b9e
ME		 30
31/*
32 * Raw event encoding for POWER8:
33 *
34 * 60 56 52 48 44 40 36 32
35 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
ba969237
ME		 36 * | | [ ] [ thresh_cmp ] [ thresh_ctl ]
37 * | | | |
38 * | | *- IFM (Linux) thresh start/stop OR FAB match -*
39 * | *- BHRB (Linux)
40 * *- EBB (Linux)
e05b9b9e
ME		 41 *
42 * 28 24 20 16 12 8 4 0
43 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
44 * [ ] [ sample ] [cache] [ pmc ] [unit ] c m [ pmcxsel ]
45 * | | | | |
46 * | | | | *- mark
47 * | | *- L1/L2/L3 cache_sel |
48 * | | |
49 * | *- sampling mode for marked events *- combine
50 * |
51 * *- thresh_sel
52 *
53 * Below uses IBM bit numbering.
54 *
55 * MMCR1[x:y] = unit (PMCxUNIT)
56 * MMCR1[x] = combine (PMCxCOMB)
57 *
58 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
59 * # PM_MRK_FAB_RSP_MATCH
60 * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
61 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
62 * # PM_MRK_FAB_RSP_MATCH_CYC
63 * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
64 * else
65 * MMCRA[48:55] = thresh_ctl (THRESH START/END)
66 *
67 * if thresh_sel:
68 * MMCRA[45:47] = thresh_sel
69 *
70 * if thresh_cmp:
71 * MMCRA[22:24] = thresh_cmp[0:2]
72 * MMCRA[25:31] = thresh_cmp[3:9]
73 *
74 * if unit == 6 or unit == 7
75 * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL)
76 * else if unit == 8 or unit == 9:
77 * if cache_sel[0] == 0: # L3 bank
78 * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0)
79 * else if cache_sel[0] == 1:
80 * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1)
81 * else if cache_sel[1]: # L1 event
82 * MMCR1[16] = cache_sel[2]
83 * MMCR1[17] = cache_sel[3]
84 *
85 * if mark:
86 * MMCRA[63] = 1 (SAMPLE_ENABLE)
87 * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG)
88 * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE)
ba969237
ME		 89 *
90 * if EBB and BHRB:
91 * MMCRA[32:33] = IFM
e05b9b9e
ME		 92 *
93 */
94
4df48999 95#define EVENT_EBB_MASK 1ull
fb568d76 96#define EVENT_EBB_SHIFT PERF_EVENT_CONFIG_EBB_SHIFT
ba969237
ME		 97#define EVENT_BHRB_MASK 1ull
98#define EVENT_BHRB_SHIFT 62
99#define EVENT_WANTS_BHRB (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)
100#define EVENT_IFM_MASK 3ull
101#define EVENT_IFM_SHIFT 60
e05b9b9e
ME		 102#define EVENT_THR_CMP_SHIFT 40 /* Threshold CMP value */
103#define EVENT_THR_CMP_MASK 0x3ff
104#define EVENT_THR_CTL_SHIFT 32 /* Threshold control value (start/stop) */
105#define EVENT_THR_CTL_MASK 0xffull
106#define EVENT_THR_SEL_SHIFT 29 /* Threshold select value */
107#define EVENT_THR_SEL_MASK 0x7
108#define EVENT_THRESH_SHIFT 29 /* All threshold bits */
109#define EVENT_THRESH_MASK 0x1fffffull
110#define EVENT_SAMPLE_SHIFT 24 /* Sampling mode & eligibility */
111#define EVENT_SAMPLE_MASK 0x1f
112#define EVENT_CACHE_SEL_SHIFT 20 /* L2/L3 cache select */
113#define EVENT_CACHE_SEL_MASK 0xf
114#define EVENT_IS_L1 (4 << EVENT_CACHE_SEL_SHIFT)
115#define EVENT_PMC_SHIFT 16 /* PMC number (1-based) */
116#define EVENT_PMC_MASK 0xf
117#define EVENT_UNIT_SHIFT 12 /* Unit */
118#define EVENT_UNIT_MASK 0xf
119#define EVENT_COMBINE_SHIFT 11 /* Combine bit */
120#define EVENT_COMBINE_MASK 0x1
121#define EVENT_MARKED_SHIFT 8 /* Marked bit */
122#define EVENT_MARKED_MASK 0x1
123#define EVENT_IS_MARKED (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
124#define EVENT_PSEL_MASK 0xff /* PMCxSEL value */
125
ba969237
ME		 126/* Bits defined by Linux */
127#define EVENT_LINUX_MASK \
128 ((EVENT_EBB_MASK << EVENT_EBB_SHIFT) | \
129 (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT) | \
130 (EVENT_IFM_MASK << EVENT_IFM_SHIFT))
131
d8bec4c9
ME		 132#define EVENT_VALID_MASK \
133 ((EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \
134 (EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \
135 (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \
136 (EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \
137 (EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \
138 (EVENT_COMBINE_MASK << EVENT_COMBINE_SHIFT) | \
139 (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
ba969237 140 EVENT_LINUX_MASK | \
d8bec4c9
ME		 141 EVENT_PSEL_MASK)
142
b1113557
AK		 143/* MMCRA IFM bits - POWER8 */
144#define POWER8_MMCRA_IFM1 0x0000000040000000UL
145#define POWER8_MMCRA_IFM2 0x0000000080000000UL
146#define POWER8_MMCRA_IFM3 0x00000000C0000000UL
147
148#define ONLY_PLM \
149 (PERF_SAMPLE_BRANCH_USER |\
150 PERF_SAMPLE_BRANCH_KERNEL |\
151 PERF_SAMPLE_BRANCH_HV)
152
e05b9b9e
ME		 153/*
154 * Layout of constraint bits:
155 *
156 * 60 56 52 48 44 40 36 32
157 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
158 * [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
159 * |
160 * thresh_sel -*
161 *
162 * 28 24 20 16 12 8 4 0
163 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
ba969237
ME		 164 * [ ] | [ ] [ sample ] [ ] [6] [5] [4] [3] [2] [1]
165 * | | | |
166 * BHRB IFM -* | | | Count of events for each PMC.
167 * EBB -* | | p1, p2, p3, p4, p5, p6.
168 * L1 I/D qualifier -* |
e05b9b9e
ME		 169 * nc - number of counters -*
170 *
171 * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
172 * we want the low bit of each field to be added to any existing value.
173 *
174 * Everything else is a value field.
175 */
176
177#define CNST_FAB_MATCH_VAL(v) (((v) & EVENT_THR_CTL_MASK) << 56)
178#define CNST_FAB_MATCH_MASK CNST_FAB_MATCH_VAL(EVENT_THR_CTL_MASK)
179
180/* We just throw all the threshold bits into the constraint */
181#define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32)
182#define CNST_THRESH_MASK CNST_THRESH_VAL(EVENT_THRESH_MASK)
183
4df48999
ME		 184#define CNST_EBB_VAL(v) (((v) & EVENT_EBB_MASK) << 24)
185#define CNST_EBB_MASK CNST_EBB_VAL(EVENT_EBB_MASK)
186
ba969237
ME		 187#define CNST_IFM_VAL(v) (((v) & EVENT_IFM_MASK) << 25)
188#define CNST_IFM_MASK CNST_IFM_VAL(EVENT_IFM_MASK)
189
e05b9b9e
ME		 190#define CNST_L1_QUAL_VAL(v) (((v) & 3) << 22)
191#define CNST_L1_QUAL_MASK CNST_L1_QUAL_VAL(3)
192
193#define CNST_SAMPLE_VAL(v) (((v) & EVENT_SAMPLE_MASK) << 16)
194#define CNST_SAMPLE_MASK CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK)
195
196/*
197 * For NC we are counting up to 4 events. This requires three bits, and we need
198 * the fifth event to overflow and set the 4th bit. To achieve that we bias the
199 * fields by 3 in test_adder.
200 */
201#define CNST_NC_SHIFT 12
202#define CNST_NC_VAL (1 << CNST_NC_SHIFT)
203#define CNST_NC_MASK (8 << CNST_NC_SHIFT)
204#define POWER8_TEST_ADDER (3 << CNST_NC_SHIFT)
205
206/*
207 * For the per-PMC fields we have two bits. The low bit is added, so if two
208 * events ask for the same PMC the sum will overflow, setting the high bit,
209 * indicating an error. So our mask sets the high bit.
210 */
211#define CNST_PMC_SHIFT(pmc) ((pmc - 1) * 2)
212#define CNST_PMC_VAL(pmc) (1 << CNST_PMC_SHIFT(pmc))
213#define CNST_PMC_MASK(pmc) (2 << CNST_PMC_SHIFT(pmc))
214
215/* Our add_fields is defined as: */
216#define POWER8_ADD_FIELDS \
217 CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \
218 CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL
219
220
221/* Bits in MMCR1 for POWER8 */
222#define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1)))
223#define MMCR1_COMBINE_SHIFT(pmc) (35 - ((pmc) - 1))
224#define MMCR1_PMCSEL_SHIFT(pmc) (24 - (((pmc) - 1)) * 8)
a53b27b3 225#define MMCR1_FAB_SHIFT 36
e05b9b9e
ME		 226#define MMCR1_DC_QUAL_SHIFT 47
227#define MMCR1_IC_QUAL_SHIFT 46
228
229/* Bits in MMCRA for POWER8 */
230#define MMCRA_SAMP_MODE_SHIFT 1
231#define MMCRA_SAMP_ELIG_SHIFT 4
232#define MMCRA_THR_CTL_SHIFT 8
233#define MMCRA_THR_SEL_SHIFT 16
234#define MMCRA_THR_CMP_SHIFT 32
235#define MMCRA_SDAR_MODE_TLB (1ull << 42)
ba969237 236#define MMCRA_IFM_SHIFT 30
e05b9b9e 237
9de5cb0f
ME		 238/* Bits in MMCR2 for POWER8 */
239#define MMCR2_FCS(pmc) (1ull << (63 - (((pmc) - 1) * 9)))
240#define MMCR2_FCP(pmc) (1ull << (62 - (((pmc) - 1) * 9)))
241#define MMCR2_FCH(pmc) (1ull << (57 - (((pmc) - 1) * 9)))
242
e05b9b9e
ME		 243
244static inline bool event_is_fab_match(u64 event)
245{
246 /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
247 event &= 0xff0fe;
248
249 /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */
250 return (event == 0x30056 || event == 0x4f052);
251}
252
253static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
254{
4df48999 255 unsigned int unit, pmc, cache, ebb;
e05b9b9e
ME		 256 unsigned long mask, value;
257
258 mask = value = 0;
259
d8bec4c9
ME		 260 if (event & ~EVENT_VALID_MASK)
261 return -1;
262
4df48999
ME		 263 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
264 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
265 cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK;
fb568d76 266 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK;
4df48999 267
e05b9b9e 268 if (pmc) {
7cbba630
ME		 269 u64 base_event;
270
e05b9b9e
ME		 271 if (pmc > 6)
272 return -1;
273
7cbba630 274 /* Ignore Linux defined bits when checking event below */
ba969237 275 base_event = event & ~EVENT_LINUX_MASK;
e05b9b9e 276
7cbba630 277 if (pmc >= 5 && base_event != 0x500fa && base_event != 0x600f4)
e05b9b9e 278 return -1;
7cbba630
ME		 279
280 mask |= CNST_PMC_MASK(pmc);
281 value |= CNST_PMC_VAL(pmc);
e05b9b9e
ME		 282 }
283
284 if (pmc <= 4) {
285 /*
286 * Add to number of counters in use. Note this includes events with
287 * a PMC of 0 - they still need a PMC, it's just assigned later.
288 * Don't count events on PMC 5 & 6, there is only one valid event
289 * on each of those counters, and they are handled above.
290 */
291 mask |= CNST_NC_MASK;
292 value |= CNST_NC_VAL;
293 }
294
295 if (unit >= 6 && unit <= 9) {
296 /*
297 * L2/L3 events contain a cache selector field, which is
298 * supposed to be programmed into MMCRC. However MMCRC is only
299 * HV writable, and there is no API for guest kernels to modify
300 * it. The solution is for the hypervisor to initialise the
301 * field to zeroes, and for us to only ever allow events that
e9aaac1a
ME		 302 * have a cache selector of zero. The bank selector (bit 3) is
303 * irrelevant, as long as the rest of the value is 0.
e05b9b9e 304 */
e9aaac1a 305 if (cache & 0x7)
e05b9b9e
ME		 306 return -1;
307
308 } else if (event & EVENT_IS_L1) {
309 mask |= CNST_L1_QUAL_MASK;
310 value |= CNST_L1_QUAL_VAL(cache);
311 }
312
313 if (event & EVENT_IS_MARKED) {
314 mask |= CNST_SAMPLE_MASK;
315 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
316 }
317
318 /*
319 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
320 * the threshold control bits are used for the match value.
321 */
322 if (event_is_fab_match(event)) {
323 mask |= CNST_FAB_MATCH_MASK;
324 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
325 } else {
326 /*
327 * Check the mantissa upper two bits are not zero, unless the
328 * exponent is also zero. See the THRESH_CMP_MANTISSA doc.
329 */
330 unsigned int cmp, exp;
331
332 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
333 exp = cmp >> 7;
334
335 if (exp && (cmp & 0x60) == 0)
336 return -1;
337
338 mask |= CNST_THRESH_MASK;
339 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
340 }
341
4df48999
ME		 342 if (!pmc && ebb)
343 /* EBB events must specify the PMC */
344 return -1;
345
ba969237
ME		 346 if (event & EVENT_WANTS_BHRB) {
347 if (!ebb)
348 /* Only EBB events can request BHRB */
349 return -1;
350
351 mask |= CNST_IFM_MASK;
352 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
353 }
354
4df48999
ME		 355 /*
356 * All events must agree on EBB, either all request it or none.
357 * EBB events are pinned & exclusive, so this should never actually
358 * hit, but we leave it as a fallback in case.
359 */
360 mask |= CNST_EBB_VAL(ebb);
361 value |= CNST_EBB_MASK;
362
e05b9b9e
ME		 363 *maskp = mask;
364 *valp = value;
365
366 return 0;
367}
368
369static int power8_compute_mmcr(u64 event[], int n_ev,
8abd818f
ME		 370 unsigned int hwc[], unsigned long mmcr[],
371 struct perf_event *pevents[])
e05b9b9e 372{
9de5cb0f 373 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
e05b9b9e
ME		 374 unsigned int pmc, pmc_inuse;
375 int i;
376
377 pmc_inuse = 0;
378
379 /* First pass to count resource use */
380 for (i = 0; i < n_ev; ++i) {
381 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
382 if (pmc)
383 pmc_inuse |= 1 << pmc;
384 }
385
446957ba 386 /* In continuous sampling mode, update SDAR on TLB miss */
e05b9b9e 387 mmcra = MMCRA_SDAR_MODE_TLB;
9de5cb0f 388 mmcr1 = mmcr2 = 0;
e05b9b9e
ME		 389
390 /* Second pass: assign PMCs, set all MMCR1 fields */
391 for (i = 0; i < n_ev; ++i) {
392 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
393 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
394 combine = (event[i] >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK;
395 psel = event[i] & EVENT_PSEL_MASK;
396
397 if (!pmc) {
398 for (pmc = 1; pmc <= 4; ++pmc) {
399 if (!(pmc_inuse & (1 << pmc)))
400 break;
401 }
402
403 pmc_inuse |= 1 << pmc;
404 }
405
406 if (pmc <= 4) {
407 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
408 mmcr1 |= combine << MMCR1_COMBINE_SHIFT(pmc);
409 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
410 }
411
412 if (event[i] & EVENT_IS_L1) {
413 cache = event[i] >> EVENT_CACHE_SEL_SHIFT;
414 mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT;
415 cache >>= 1;
416 mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT;
417 }
418
419 if (event[i] & EVENT_IS_MARKED) {
420 mmcra |= MMCRA_SAMPLE_ENABLE;
421
422 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
423 if (val) {
424 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT;
425 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
426 }
427 }
428
429 /*
430 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
431 * the threshold bits are used for the match value.
432 */
433 if (event_is_fab_match(event[i])) {
a53b27b3
ME		 434 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
435 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
e05b9b9e
ME		 436 } else {
437 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
438 mmcra |= val << MMCRA_THR_CTL_SHIFT;
439 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
440 mmcra |= val << MMCRA_THR_SEL_SHIFT;
441 val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
442 mmcra |= val << MMCRA_THR_CMP_SHIFT;
443 }
444
ba969237
ME		 445 if (event[i] & EVENT_WANTS_BHRB) {
446 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
447 mmcra |= val << MMCRA_IFM_SHIFT;
448 }
449
9de5cb0f
ME		 450 if (pevents[i]->attr.exclude_user)
451 mmcr2 |= MMCR2_FCP(pmc);
452
453 if (pevents[i]->attr.exclude_hv)
454 mmcr2 |= MMCR2_FCH(pmc);
455
456 if (pevents[i]->attr.exclude_kernel) {
457 if (cpu_has_feature(CPU_FTR_HVMODE))
458 mmcr2 |= MMCR2_FCH(pmc);
459 else
460 mmcr2 |= MMCR2_FCS(pmc);
461 }
462
e05b9b9e
ME		 463 hwc[i] = pmc - 1;
464 }
465
466 /* Return MMCRx values */
467 mmcr[0] = 0;
468
469 /* pmc_inuse is 1-based */
470 if (pmc_inuse & 2)
471 mmcr[0] = MMCR0_PMC1CE;
472
473 if (pmc_inuse & 0x7c)
474 mmcr[0] |= MMCR0_PMCjCE;
475
7a7a41f9
ME		 476 /* If we're not using PMC 5 or 6, freeze them */
477 if (!(pmc_inuse & 0x60))
478 mmcr[0] |= MMCR0_FC56;
479
e05b9b9e
ME		 480 mmcr[1] = mmcr1;
481 mmcr[2] = mmcra;
9de5cb0f 482 mmcr[3] = mmcr2;
e05b9b9e
ME		 483
484 return 0;
485}
486
487#define MAX_ALT 2
488
489/* Table of alternatives, sorted by column 0 */
490static const unsigned int event_alternatives[][MAX_ALT] = {
491 { 0x10134, 0x301e2 }, /* PM_MRK_ST_CMPL */
492 { 0x10138, 0x40138 }, /* PM_BR_MRK_2PATH */
493 { 0x18082, 0x3e05e }, /* PM_L3_CO_MEPF */
494 { 0x1d14e, 0x401e8 }, /* PM_MRK_DATA_FROM_L2MISS */
495 { 0x1e054, 0x4000a }, /* PM_CMPLU_STALL */
496 { 0x20036, 0x40036 }, /* PM_BR_2PATH */
497 { 0x200f2, 0x300f2 }, /* PM_INST_DISP */
498 { 0x200f4, 0x600f4 }, /* PM_RUN_CYC */
499 { 0x2013c, 0x3012e }, /* PM_MRK_FILT_MATCH */
500 { 0x3e054, 0x400f0 }, /* PM_LD_MISS_L1 */
501 { 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */
502};
503
504/*
505 * Scan the alternatives table for a match and return the
506 * index into the alternatives table if found, else -1.
507 */
508static int find_alternative(u64 event)
509{
510 int i, j;
511
512 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
513 if (event < event_alternatives[i][0])
514 break;
515
516 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
517 if (event == event_alternatives[i][j])
518 return i;
519 }
520
521 return -1;
522}
523
524static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[])
525{
526 int i, j, num_alt = 0;
527 u64 alt_event;
528
529 alt[num_alt++] = event;
530
531 i = find_alternative(event);
532 if (i >= 0) {
533 /* Filter out the original event, it's already in alt[0] */
534 for (j = 0; j < MAX_ALT; ++j) {
535 alt_event = event_alternatives[i][j];
536 if (alt_event && alt_event != event)
537 alt[num_alt++] = alt_event;
538 }
539 }
540
541 if (flags & PPMU_ONLY_COUNT_RUN) {
542 /*
543 * We're only counting in RUN state, so PM_CYC is equivalent to
544 * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL.
545 */
546 j = num_alt;
547 for (i = 0; i < num_alt; ++i) {
548 switch (alt[i]) {
549 case 0x1e: /* PM_CYC */
550 alt[j++] = 0x600f4; /* PM_RUN_CYC */
551 break;
552 case 0x600f4: /* PM_RUN_CYC */
553 alt[j++] = 0x1e;
554 break;
555 case 0x2: /* PM_PPC_CMPL */
556 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
557 break;
558 case 0x500fa: /* PM_RUN_INST_CMPL */
559 alt[j++] = 0x2; /* PM_PPC_CMPL */
560 break;
561 }
562 }
563 num_alt = j;
564 }
565
566 return num_alt;
567}
568
569static void power8_disable_pmc(unsigned int pmc, unsigned long mmcr[])
570{
571 if (pmc <= 3)
572 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
573}
574
e0728b50
SB		 575GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
576GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_GCT_NOSLOT_CYC);
577GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
578GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
579GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN);
580GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
581GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
582GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
583
584CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
585CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
586
587CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
588CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
589CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
590CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
591CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
592
593CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
594CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
595CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);
596CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
597CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);
598
599CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
600CACHE_EVENT_ATTR(branch-loads, PM_BRU_FIN);
601CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
602CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
603
604static struct attribute *power8_events_attr[] = {
605 GENERIC_EVENT_PTR(PM_CYC),
606 GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC),
607 GENERIC_EVENT_PTR(PM_CMPLU_STALL),
608 GENERIC_EVENT_PTR(PM_INST_CMPL),
609 GENERIC_EVENT_PTR(PM_BRU_FIN),
610 GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
611 GENERIC_EVENT_PTR(PM_LD_REF_L1),
612 GENERIC_EVENT_PTR(PM_LD_MISS_L1),
613
614 CACHE_EVENT_PTR(PM_LD_MISS_L1),
615 CACHE_EVENT_PTR(PM_LD_REF_L1),
616 CACHE_EVENT_PTR(PM_L1_PREF),
617 CACHE_EVENT_PTR(PM_ST_MISS_L1),
618 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
619 CACHE_EVENT_PTR(PM_INST_FROM_L1),
620 CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
621 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
622 CACHE_EVENT_PTR(PM_DATA_FROM_L3),
623 CACHE_EVENT_PTR(PM_L3_PREF_ALL),
624 CACHE_EVENT_PTR(PM_L2_ST_MISS),
625 CACHE_EVENT_PTR(PM_L2_ST),
626
627 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
628 CACHE_EVENT_PTR(PM_BRU_FIN),
629
630 CACHE_EVENT_PTR(PM_DTLB_MISS),
631 CACHE_EVENT_PTR(PM_ITLB_MISS),
632 NULL
633};
634
635static struct attribute_group power8_pmu_events_group = {
636 .name = "events",
637 .attrs = power8_events_attr,
638};
639
e05b9b9e
ME		 640PMU_FORMAT_ATTR(event, "config:0-49");
641PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
642PMU_FORMAT_ATTR(mark, "config:8");
643PMU_FORMAT_ATTR(combine, "config:11");
644PMU_FORMAT_ATTR(unit, "config:12-15");
645PMU_FORMAT_ATTR(pmc, "config:16-19");
646PMU_FORMAT_ATTR(cache_sel, "config:20-23");
647PMU_FORMAT_ATTR(sample_mode, "config:24-28");
648PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
649PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
650PMU_FORMAT_ATTR(thresh_start, "config:36-39");
651PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
652
653static struct attribute *power8_pmu_format_attr[] = {
654 &format_attr_event.attr,
655 &format_attr_pmcxsel.attr,
656 &format_attr_mark.attr,
657 &format_attr_combine.attr,
658 &format_attr_unit.attr,
659 &format_attr_pmc.attr,
660 &format_attr_cache_sel.attr,
661 &format_attr_sample_mode.attr,
662 &format_attr_thresh_sel.attr,
663 &format_attr_thresh_stop.attr,
664 &format_attr_thresh_start.attr,
665 &format_attr_thresh_cmp.attr,
666 NULL,
667};
668
669struct attribute_group power8_pmu_format_group = {
670 .name = "format",
671 .attrs = power8_pmu_format_attr,
672};
673
674static const struct attribute_group *power8_pmu_attr_groups[] = {
675 &power8_pmu_format_group,
e0728b50 676 &power8_pmu_events_group,
e05b9b9e
ME		 677 NULL,
678};
679
680static int power8_generic_events[] = {
681 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
682 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC,
683 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
684 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
685 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN,
686 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
2fdd313f
ME		 687 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
688 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
e05b9b9e
ME		 689};
690
b1113557
AK		 691static u64 power8_bhrb_filter_map(u64 branch_sample_type)
692{
693 u64 pmu_bhrb_filter = 0;
b1113557 694
7689bdca 695 /* BHRB and regular PMU events share the same privilege state
b1113557 696 * filter configuration. BHRB is always recorded along with a
7689bdca
AK		 697 * regular PMU event. As the privilege state filter is handled
698 * in the basic PMC configuration of the accompanying regular
699 * PMU event, we ignore any separate BHRB specific request.
b1113557 700 */
b1113557
AK		 701
702 /* No branch filter requested */
703 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
704 return pmu_bhrb_filter;
705
706 /* Invalid branch filter options - HW does not support */
707 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
708 return -1;
709
710 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
711 return -1;
712
24f1a79a
SE		 713 if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
714 return -1;
715
b1113557
AK		 716 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
717 pmu_bhrb_filter |= POWER8_MMCRA_IFM1;
718 return pmu_bhrb_filter;
719 }
720
721 /* Every thing else is unsupported */
722 return -1;
723}
724
725static void power8_config_bhrb(u64 pmu_bhrb_filter)
726{
727 /* Enable BHRB filter in PMU */
728 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
729}
730
2fdd313f
ME		 731#define C(x) PERF_COUNT_HW_CACHE_##x
732
733/*
734 * Table of generalized cache-related events.
735 * 0 means not supported, -1 means nonsensical, other values
736 * are event codes.
737 */
738static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
739 [ C(L1D) ] = {
740 [ C(OP_READ) ] = {
741 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
742 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
743 },
744 [ C(OP_WRITE) ] = {
745 [ C(RESULT_ACCESS) ] = 0,
746 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
747 },
748 [ C(OP_PREFETCH) ] = {
749 [ C(RESULT_ACCESS) ] = PM_L1_PREF,
750 [ C(RESULT_MISS) ] = 0,
751 },
752 },
753 [ C(L1I) ] = {
754 [ C(OP_READ) ] = {
755 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
756 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
757 },
758 [ C(OP_WRITE) ] = {
759 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
760 [ C(RESULT_MISS) ] = -1,
761 },
762 [ C(OP_PREFETCH) ] = {
763 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
764 [ C(RESULT_MISS) ] = 0,
765 },
766 },
767 [ C(LL) ] = {
768 [ C(OP_READ) ] = {
769 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
770 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
771 },
772 [ C(OP_WRITE) ] = {
773 [ C(RESULT_ACCESS) ] = PM_L2_ST,
774 [ C(RESULT_MISS) ] = PM_L2_ST_MISS,
775 },
776 [ C(OP_PREFETCH) ] = {
777 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
778 [ C(RESULT_MISS) ] = 0,
779 },
780 },
781 [ C(DTLB) ] = {
782 [ C(OP_READ) ] = {
783 [ C(RESULT_ACCESS) ] = 0,
784 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
785 },
786 [ C(OP_WRITE) ] = {
787 [ C(RESULT_ACCESS) ] = -1,
788 [ C(RESULT_MISS) ] = -1,
789 },
790 [ C(OP_PREFETCH) ] = {
791 [ C(RESULT_ACCESS) ] = -1,
792 [ C(RESULT_MISS) ] = -1,
793 },
794 },
795 [ C(ITLB) ] = {
796 [ C(OP_READ) ] = {
797 [ C(RESULT_ACCESS) ] = 0,
798 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
799 },
800 [ C(OP_WRITE) ] = {
801 [ C(RESULT_ACCESS) ] = -1,
802 [ C(RESULT_MISS) ] = -1,
803 },
804 [ C(OP_PREFETCH) ] = {
805 [ C(RESULT_ACCESS) ] = -1,
806 [ C(RESULT_MISS) ] = -1,
807 },
808 },
809 [ C(BPU) ] = {
810 [ C(OP_READ) ] = {
811 [ C(RESULT_ACCESS) ] = PM_BRU_FIN,
812 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
813 },
814 [ C(OP_WRITE) ] = {
815 [ C(RESULT_ACCESS) ] = -1,
816 [ C(RESULT_MISS) ] = -1,
817 },
818 [ C(OP_PREFETCH) ] = {
819 [ C(RESULT_ACCESS) ] = -1,
820 [ C(RESULT_MISS) ] = -1,
821 },
822 },
823 [ C(NODE) ] = {
824 [ C(OP_READ) ] = {
825 [ C(RESULT_ACCESS) ] = -1,
826 [ C(RESULT_MISS) ] = -1,
827 },
828 [ C(OP_WRITE) ] = {
829 [ C(RESULT_ACCESS) ] = -1,
830 [ C(RESULT_MISS) ] = -1,
831 },
832 [ C(OP_PREFETCH) ] = {
833 [ C(RESULT_ACCESS) ] = -1,
834 [ C(RESULT_MISS) ] = -1,
835 },
836 },
837};
838
839#undef C
840
e05b9b9e
ME		 841static struct power_pmu power8_pmu = {
842 .name = "POWER8",
843 .n_counter = 6,
844 .max_alternatives = MAX_ALT + 1,
845 .add_fields = POWER8_ADD_FIELDS,
846 .test_adder = POWER8_TEST_ADDER,
847 .compute_mmcr = power8_compute_mmcr,
b1113557
AK		 848 .config_bhrb = power8_config_bhrb,
849 .bhrb_filter_map = power8_bhrb_filter_map,
e05b9b9e
ME		 850 .get_constraint = power8_get_constraint,
851 .get_alternatives = power8_get_alternatives,
852 .disable_pmc = power8_disable_pmc,
370f06c8 853 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
e05b9b9e
ME		 854 .n_generic = ARRAY_SIZE(power8_generic_events),
855 .generic_events = power8_generic_events,
2fdd313f 856 .cache_events = &power8_cache_events,
e05b9b9e 857 .attr_groups = power8_pmu_attr_groups,
b1113557 858 .bhrb_nr = 32,
e05b9b9e
ME		 859};
860
861static int __init init_power8_pmu(void)
862{
5d7ead00
ME		 863 int rc;
864
e05b9b9e
ME		 865 if (!cur_cpu_spec->oprofile_cpu_type ||
866 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8"))
867 return -ENODEV;
868
5d7ead00
ME		 869 rc = register_power_pmu(&power8_pmu);
870 if (rc)
871 return rc;
872
873 /* Tell userspace that EBB is supported */
874 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
875
c2e37a26
ME		 876 if (cpu_has_feature(CPU_FTR_PMAO_BUG))
877 pr_info("PMAO restore workaround active.\n");
878
5d7ead00 879 return 0;
e05b9b9e
ME		 880}
881early_initcall(init_power8_pmu);
Linux kernel - Deliverables
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