[deliverable/linux.git] / arch / powerpc / perf / power9-pmu.c

/*
 * Performance counter support for POWER9 processors.
 *
 * Copyright 2009 Paul Mackerras, IBM Corporation.
 * Copyright 2013 Michael Ellerman, IBM Corporation.
 * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or later version.
 */

#define pr_fmt(fmt)	"power9-pmu: " fmt

#include "isa207-common.h"

/*
 * Some power9 event codes.
 */
#define EVENT(_name, _code)	_name = _code,

enum {
#include "power9-events-list.h"
};

#undef EVENT

/* MMCRA IFM bits - POWER9 */
#define POWER9_MMCRA_IFM1		0x0000000040000000UL
#define POWER9_MMCRA_IFM2		0x0000000080000000UL
#define POWER9_MMCRA_IFM3		0x00000000C0000000UL


PMU_FORMAT_ATTR(event,		"config:0-49");
PMU_FORMAT_ATTR(pmcxsel,	"config:0-7");
PMU_FORMAT_ATTR(mark,		"config:8");
PMU_FORMAT_ATTR(combine,	"config:11");
PMU_FORMAT_ATTR(unit,		"config:12-15");
PMU_FORMAT_ATTR(pmc,		"config:16-19");
PMU_FORMAT_ATTR(cache_sel,	"config:20-23");
PMU_FORMAT_ATTR(sample_mode,	"config:24-28");
PMU_FORMAT_ATTR(thresh_sel,	"config:29-31");
PMU_FORMAT_ATTR(thresh_stop,	"config:32-35");
PMU_FORMAT_ATTR(thresh_start,	"config:36-39");
PMU_FORMAT_ATTR(thresh_cmp,	"config:40-49");

static struct attribute *power9_pmu_format_attr[] = {
	&format_attr_event.attr,
	&format_attr_pmcxsel.attr,
	&format_attr_mark.attr,
	&format_attr_combine.attr,
	&format_attr_unit.attr,
	&format_attr_pmc.attr,
	&format_attr_cache_sel.attr,
	&format_attr_sample_mode.attr,
	&format_attr_thresh_sel.attr,
	&format_attr_thresh_stop.attr,
	&format_attr_thresh_start.attr,
	&format_attr_thresh_cmp.attr,
	NULL,
};

struct attribute_group power9_pmu_format_group = {
	.name = "format",
	.attrs = power9_pmu_format_attr,
};

static const struct attribute_group *power9_pmu_attr_groups[] = {
	&power9_pmu_format_group,
	NULL,
};

static int power9_generic_events[] = {
	[PERF_COUNT_HW_CPU_CYCLES] =			PM_CYC,
	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =	PM_ICT_NOSLOT_CYC,
	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =	PM_CMPLU_STALL,
	[PERF_COUNT_HW_INSTRUCTIONS] =			PM_INST_CMPL,
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =		PM_BRU_CMPL,
	[PERF_COUNT_HW_BRANCH_MISSES] =			PM_BR_MPRED_CMPL,
	[PERF_COUNT_HW_CACHE_REFERENCES] =		PM_LD_REF_L1,
	[PERF_COUNT_HW_CACHE_MISSES] =			PM_LD_MISS_L1_FIN,
};

static u64 power9_bhrb_filter_map(u64 branch_sample_type)
{
	u64 pmu_bhrb_filter = 0;

	/* BHRB and regular PMU events share the same privilege state
	 * filter configuration. BHRB is always recorded along with a
	 * regular PMU event. As the privilege state filter is handled
	 * in the basic PMC configuration of the accompanying regular
	 * PMU event, we ignore any separate BHRB specific request.
	 */

	/* No branch filter requested */
	if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
		return pmu_bhrb_filter;

	/* Invalid branch filter options - HW does not support */
	if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
		return -1;

	if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
		return -1;

	if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
		return -1;

	if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
		pmu_bhrb_filter |= POWER9_MMCRA_IFM1;
		return pmu_bhrb_filter;
	}

	/* Every thing else is unsupported */
	return -1;
}

static void power9_config_bhrb(u64 pmu_bhrb_filter)
{
	/* Enable BHRB filter in PMU */
	mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
}

#define C(x)	PERF_COUNT_HW_CACHE_##x

/*
 * Table of generalized cache-related events.
 * 0 means not supported, -1 means nonsensical, other values
 * are event codes.
 */
static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
	[ C(L1D) ] = {
		[ C(OP_READ) ] = {
			[ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
			[ C(RESULT_MISS)   ] = PM_LD_MISS_L1_FIN,
		},
		[ C(OP_WRITE) ] = {
			[ C(RESULT_ACCESS) ] = 0,
			[ C(RESULT_MISS)   ] = PM_ST_MISS_L1,
		},
		[ C(OP_PREFETCH) ] = {
			[ C(RESULT_ACCESS) ] = PM_L1_PREF,
			[ C(RESULT_MISS)   ] = 0,
		},
	},
	[ C(L1I) ] = {
		[ C(OP_READ) ] = {
			[ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
			[ C(RESULT_MISS)   ] = PM_L1_ICACHE_MISS,
		},
		[ C(OP_WRITE) ] = {
			[ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
			[ C(RESULT_MISS)   ] = -1,
		},
		[ C(OP_PREFETCH) ] = {
			[ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
			[ C(RESULT_MISS)   ] = 0,
		},
	},
	[ C(LL) ] = {
		[ C(OP_READ) ] = {
			[ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
			[ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
		},
		[ C(OP_WRITE) ] = {
			[ C(RESULT_ACCESS) ] = PM_L2_ST,
			[ C(RESULT_MISS)   ] = PM_L2_ST_MISS,
		},
		[ C(OP_PREFETCH) ] = {
			[ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
			[ C(RESULT_MISS)   ] = 0,
		},
	},
	[ C(DTLB) ] = {
		[ C(OP_READ) ] = {
			[ C(RESULT_ACCESS) ] = 0,
			[ C(RESULT_MISS)   ] = PM_DTLB_MISS,
		},
		[ C(OP_WRITE) ] = {
			[ C(RESULT_ACCESS) ] = -1,
			[ C(RESULT_MISS)   ] = -1,
		},
		[ C(OP_PREFETCH) ] = {
			[ C(RESULT_ACCESS) ] = -1,
			[ C(RESULT_MISS)   ] = -1,
		},
	},
	[ C(ITLB) ] = {
		[ C(OP_READ) ] = {
			[ C(RESULT_ACCESS) ] = 0,
			[ C(RESULT_MISS)   ] = PM_ITLB_MISS,
		},
		[ C(OP_WRITE) ] = {
			[ C(RESULT_ACCESS) ] = -1,
			[ C(RESULT_MISS)   ] = -1,
		},
		[ C(OP_PREFETCH) ] = {
			[ C(RESULT_ACCESS) ] = -1,
			[ C(RESULT_MISS)   ] = -1,
		},
	},
	[ C(BPU) ] = {
		[ C(OP_READ) ] = {
			[ C(RESULT_ACCESS) ] = PM_BRU_CMPL,
			[ C(RESULT_MISS)   ] = PM_BR_MPRED_CMPL,
		},
		[ C(OP_WRITE) ] = {
			[ C(RESULT_ACCESS) ] = -1,
			[ C(RESULT_MISS)   ] = -1,
		},
		[ C(OP_PREFETCH) ] = {
			[ C(RESULT_ACCESS) ] = -1,
			[ C(RESULT_MISS)   ] = -1,
		},
	},
	[ C(NODE) ] = {
		[ C(OP_READ) ] = {
			[ C(RESULT_ACCESS) ] = -1,
			[ C(RESULT_MISS)   ] = -1,
		},
		[ C(OP_WRITE) ] = {
			[ C(RESULT_ACCESS) ] = -1,
			[ C(RESULT_MISS)   ] = -1,
		},
		[ C(OP_PREFETCH) ] = {
			[ C(RESULT_ACCESS) ] = -1,
			[ C(RESULT_MISS)   ] = -1,
		},
	},
};

#undef C

static struct power_pmu power9_pmu = {
	.name			= "POWER9",
	.n_counter		= MAX_PMU_COUNTERS,
	.add_fields		= ISA207_ADD_FIELDS,
	.test_adder		= ISA207_TEST_ADDER,
	.compute_mmcr		= isa207_compute_mmcr,
	.config_bhrb		= power9_config_bhrb,
	.bhrb_filter_map	= power9_bhrb_filter_map,
	.get_constraint		= isa207_get_constraint,
	.disable_pmc		= isa207_disable_pmc,
	.flags			= PPMU_HAS_SIER | PPMU_ARCH_207S,
	.n_generic		= ARRAY_SIZE(power9_generic_events),
	.generic_events		= power9_generic_events,
	.cache_events		= &power9_cache_events,
	.attr_groups		= power9_pmu_attr_groups,
	.bhrb_nr		= 32,
};

static int __init init_power9_pmu(void)
{
	int rc;

	/* Comes from cpu_specs[] */
	if (!cur_cpu_spec->oprofile_cpu_type ||
	    strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9"))
		return -ENODEV;

	rc = register_power_pmu(&power9_pmu);
	if (rc)
		return rc;

	/* Tell userspace that EBB is supported */
	cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;

	return 0;
}
early_initcall(init_power9_pmu);
Commit	Line	Data
8c002dbd MS	1	/*
	2	* Performance counter support for POWER9 processors.
	3	*
	4	* Copyright 2009 Paul Mackerras, IBM Corporation.
	5	* Copyright 2013 Michael Ellerman, IBM Corporation.
	6	* Copyright 2016 Madhavan Srinivasan, IBM Corporation.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version
	11	* 2 of the License, or later version.
	12	*/
	13
	14	#define pr_fmt(fmt) "power9-pmu: " fmt
	15
	16	#include "isa207-common.h"
	17
	18	/*
	19	* Some power9 event codes.
	20	*/
	21	#define EVENT(_name, _code) _name = _code,
	22
	23	enum {
	24	#include "power9-events-list.h"
	25	};
	26
	27	#undef EVENT
	28
	29	/* MMCRA IFM bits - POWER9 */
	30	#define POWER9_MMCRA_IFM1 0x0000000040000000UL
	31	#define POWER9_MMCRA_IFM2 0x0000000080000000UL
	32	#define POWER9_MMCRA_IFM3 0x00000000C0000000UL
	33
	34
	35	PMU_FORMAT_ATTR(event, "config:0-49");
	36	PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
	37	PMU_FORMAT_ATTR(mark, "config:8");
	38	PMU_FORMAT_ATTR(combine, "config:11");
	39	PMU_FORMAT_ATTR(unit, "config:12-15");
	40	PMU_FORMAT_ATTR(pmc, "config:16-19");
	41	PMU_FORMAT_ATTR(cache_sel, "config:20-23");
	42	PMU_FORMAT_ATTR(sample_mode, "config:24-28");
	43	PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
	44	PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
	45	PMU_FORMAT_ATTR(thresh_start, "config:36-39");
	46	PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
	47
	48	static struct attribute *power9_pmu_format_attr[] = {
	49	&format_attr_event.attr,
	50	&format_attr_pmcxsel.attr,
	51	&format_attr_mark.attr,
	52	&format_attr_combine.attr,
	53	&format_attr_unit.attr,
	54	&format_attr_pmc.attr,
	55	&format_attr_cache_sel.attr,
	56	&format_attr_sample_mode.attr,
	57	&format_attr_thresh_sel.attr,
	58	&format_attr_thresh_stop.attr,
	59	&format_attr_thresh_start.attr,
	60	&format_attr_thresh_cmp.attr,
	61	NULL,
	62	};
	63
	64	struct attribute_group power9_pmu_format_group = {
65	.name = "format",
66	.attrs = power9_pmu_format_attr,
67	};
68
69	static const struct attribute_group *power9_pmu_attr_groups[] = {
70	&power9_pmu_format_group,
71	NULL,
72	};
73
74	static int power9_generic_events[] = {
75	[PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
76	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
77	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
78	[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
79	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_CMPL,
80	[PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
81	[PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
82	[PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN,
83	};
84
85	static u64 power9_bhrb_filter_map(u64 branch_sample_type)
86	{
87	u64 pmu_bhrb_filter = 0;
88
89	/* BHRB and regular PMU events share the same privilege state
90	* filter configuration. BHRB is always recorded along with a
91	* regular PMU event. As the privilege state filter is handled
92	* in the basic PMC configuration of the accompanying regular
93	* PMU event, we ignore any separate BHRB specific request.
94	*/
95
96	/* No branch filter requested */
97	if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
98	return pmu_bhrb_filter;
99
100	/* Invalid branch filter options - HW does not support */
101	if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
102	return -1;
103
104	if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
105	return -1;
106
107	if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
108	return -1;
109
110	if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
111	pmu_bhrb_filter \|= POWER9_MMCRA_IFM1;
112	return pmu_bhrb_filter;
113	}
114
115	/* Every thing else is unsupported */
116	return -1;
117	}
118
119	static void power9_config_bhrb(u64 pmu_bhrb_filter)
120	{
121	/* Enable BHRB filter in PMU */
122	mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) \| pmu_bhrb_filter));
123	}
124
125	#define C(x) PERF_COUNT_HW_CACHE_##x
126
127	/*
128	* Table of generalized cache-related events.
129	* 0 means not supported, -1 means nonsensical, other values
130	* are event codes.
131	*/
132	static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
133	[ C(L1D) ] = {
134	[ C(OP_READ) ] = {
135	[ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
136	[ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
137	},
138	[ C(OP_WRITE) ] = {
139	[ C(RESULT_ACCESS) ] = 0,
140	[ C(RESULT_MISS) ] = PM_ST_MISS_L1,
141	},
142	[ C(OP_PREFETCH) ] = {
143	[ C(RESULT_ACCESS) ] = PM_L1_PREF,
144	[ C(RESULT_MISS) ] = 0,
145	},
146	},
147	[ C(L1I) ] = {
148	[ C(OP_READ) ] = {
149	[ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
150	[ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
151	},
152	[ C(OP_WRITE) ] = {
153	[ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
154	[ C(RESULT_MISS) ] = -1,
155	},
156	[ C(OP_PREFETCH) ] = {
157	[ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
158	[ C(RESULT_MISS) ] = 0,
159	},
160	},
161	[ C(LL) ] = {
162	[ C(OP_READ) ] = {
163	[ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
164	[ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
165	},
166	[ C(OP_WRITE) ] = {
167	[ C(RESULT_ACCESS) ] = PM_L2_ST,
168	[ C(RESULT_MISS) ] = PM_L2_ST_MISS,
169	},
170	[ C(OP_PREFETCH) ] = {
171	[ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
172	[ C(RESULT_MISS) ] = 0,
173	},
174	},
175	[ C(DTLB) ] = {
176	[ C(OP_READ) ] = {
177	[ C(RESULT_ACCESS) ] = 0,
178	[ C(RESULT_MISS) ] = PM_DTLB_MISS,
179	},
180	[ C(OP_WRITE) ] = {
181	[ C(RESULT_ACCESS) ] = -1,
182	[ C(RESULT_MISS) ] = -1,
183	},
184	[ C(OP_PREFETCH) ] = {
185	[ C(RESULT_ACCESS) ] = -1,
186	[ C(RESULT_MISS) ] = -1,
187	},
188	},
189	[ C(ITLB) ] = {
190	[ C(OP_READ) ] = {
191	[ C(RESULT_ACCESS) ] = 0,
192	[ C(RESULT_MISS) ] = PM_ITLB_MISS,
193	},
194	[ C(OP_WRITE) ] = {
195	[ C(RESULT_ACCESS) ] = -1,
196	[ C(RESULT_MISS) ] = -1,
197	},
198	[ C(OP_PREFETCH) ] = {
199	[ C(RESULT_ACCESS) ] = -1,
200	[ C(RESULT_MISS) ] = -1,
201	},
202	},
203	[ C(BPU) ] = {
204	[ C(OP_READ) ] = {
205	[ C(RESULT_ACCESS) ] = PM_BRU_CMPL,
206	[ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
207	},
208	[ C(OP_WRITE) ] = {
209	[ C(RESULT_ACCESS) ] = -1,
210	[ C(RESULT_MISS) ] = -1,
211	},
212	[ C(OP_PREFETCH) ] = {
213	[ C(RESULT_ACCESS) ] = -1,
214	[ C(RESULT_MISS) ] = -1,
215	},
216	},
217	[ C(NODE) ] = {
218	[ C(OP_READ) ] = {
219	[ C(RESULT_ACCESS) ] = -1,
220	[ C(RESULT_MISS) ] = -1,
221	},
222	[ C(OP_WRITE) ] = {
223	[ C(RESULT_ACCESS) ] = -1,
224	[ C(RESULT_MISS) ] = -1,
225	},
226	[ C(OP_PREFETCH) ] = {
227	[ C(RESULT_ACCESS) ] = -1,
228	[ C(RESULT_MISS) ] = -1,
229	},
230	},
231	};
232
233	#undef C
234
235	static struct power_pmu power9_pmu = {
236	.name = "POWER9",
237	.n_counter = MAX_PMU_COUNTERS,
238	.add_fields = ISA207_ADD_FIELDS,
239	.test_adder = ISA207_TEST_ADDER,
240	.compute_mmcr = isa207_compute_mmcr,
241	.config_bhrb = power9_config_bhrb,
242	.bhrb_filter_map = power9_bhrb_filter_map,
243	.get_constraint = isa207_get_constraint,
244	.disable_pmc = isa207_disable_pmc,
245	.flags = PPMU_HAS_SIER \| PPMU_ARCH_207S,
246	.n_generic = ARRAY_SIZE(power9_generic_events),
247	.generic_events = power9_generic_events,
248	.cache_events = &power9_cache_events,
249	.attr_groups = power9_pmu_attr_groups,
250	.bhrb_nr = 32,
251	};
252
253	static int __init init_power9_pmu(void)
254	{
255	int rc;
256
257	/* Comes from cpu_specs[] */
258	if (!cur_cpu_spec->oprofile_cpu_type \|\|
259	strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9"))
260	return -ENODEV;
261
262	rc = register_power_pmu(&power9_pmu);
263	if (rc)
264	return rc;
265
266	/* Tell userspace that EBB is supported */
267	cur_cpu_spec->cpu_user_features2 \|= PPC_FEATURE2_EBB;
268
269	return 0;
270	}
271	early_initcall(init_power9_pmu);