projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| e00c5498 SW |
1 | /* |
| 2 | * Common PowerQUICC II code. | |
| 3 | * | |
| 4 | * Author: Scott Wood <scottwood@freescale.com> | |
| 5 | * Copyright (c) 2007 Freescale Semiconductor | |
| 6 | * | |
| 7 | * Based on code by Vitaly Bordug <vbordug@ru.mvista.com> | |
| 8 | * pq2_restart fix by Wade Farnsworth <wfarnsworth@mvista.com> | |
| 9 | * Copyright (c) 2006 MontaVista Software, Inc. | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or modify it | |
| 12 | * under the terms of the GNU General Public License as published by the | |
| 13 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 14 | * option) any later version. | |
| 15 | */ | |
| 16 | ||
| 17 | #include <asm/cpm2.h> | |
| 18 | #include <asm/io.h> | |
| 19 | #include <asm/pci-bridge.h> | |
| e00c5498 SW |
20 | |
| 21 | #include <platforms/82xx/pq2.h> | |
| 22 | ||
| 23 | #define RMR_CSRE 0x00000001 | |
| 24 | ||
| 25 | void pq2_restart(char *cmd) | |
| 26 | { | |
| 27 | local_irq_disable(); | |
| 28 | setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE); | |
| 29 | ||
| 30 | /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */ | |
| 31 | mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR)); | |
| 32 | in_8(&cpm2_immr->im_clkrst.res[0]); | |
| 33 | ||
| 34 | panic("Restart failed\n"); | |
| 35 | } | |
| 36 | ||
| 37 | #ifdef CONFIG_PCI | |
| 38 | static int pq2_pci_exclude_device(struct pci_controller *hose, | |
| 39 | u_char bus, u8 devfn) | |
| 40 | { | |
| 41 | if (bus == 0 && PCI_SLOT(devfn) == 0) | |
| 42 | return PCIBIOS_DEVICE_NOT_FOUND; | |
| 43 | else | |
| 44 | return PCIBIOS_SUCCESSFUL; | |
| 45 | } | |
| 46 | ||
| 47 | static void __init pq2_pci_add_bridge(struct device_node *np) | |
| 48 | { | |
| 49 | struct pci_controller *hose; | |
| 50 | struct resource r; | |
| 51 | ||
| 52 | if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b) | |
| 53 | goto err; | |
| 54 | ||
| 0e47ff1c | 55 | pci_add_flags(PCI_REASSIGN_ALL_BUS); |
| e00c5498 SW |
56 | |
| 57 | hose = pcibios_alloc_controller(np); | |
| 58 | if (!hose) | |
| 59 | return; | |
| 60 | ||
| 44ef3390 | 61 | hose->dn = np; |
| e00c5498 SW |
62 | |
| 63 | setup_indirect_pci(hose, r.start + 0x100, r.start + 0x104, 0); | |
| 64 | pci_process_bridge_OF_ranges(hose, np, 1); | |
| 65 | ||
| 66 | return; | |
| 67 | ||
| 68 | err: | |
| 69 | printk(KERN_ERR "No valid PCI reg property in device tree\n"); | |
| 70 | } | |
| 71 | ||
| 72 | void __init pq2_init_pci(void) | |
| 73 | { | |
| e49f1e20 | 74 | struct device_node *np; |
| e00c5498 SW |
75 | |
| 76 | ppc_md.pci_exclude_device = pq2_pci_exclude_device; | |
| 77 | ||
| e49f1e20 | 78 | for_each_compatible_node(np, NULL, "fsl,pq2-pci") |
| e00c5498 SW |
79 | pq2_pci_add_bridge(np); |
| 80 | } | |
| 81 | #endif |