[deliverable/linux.git] / arch / powerpc / platforms / 82xx / pq2ads-pci-pic.c

/*
 * PQ2 ADS-style PCI interrupt controller
 *
 * Copyright 2007 Freescale Semiconductor, Inc.
 * Author: Scott Wood <scottwood@freescale.com>
 *
 * Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
 * Copyright (c) 2006 MontaVista Software, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/slab.h>

#include <asm/io.h>
#include <asm/prom.h>
#include <asm/cpm2.h>

#include "pq2.h"

static DEFINE_RAW_SPINLOCK(pci_pic_lock);

struct pq2ads_pci_pic {
	struct device_node *node;
	struct irq_domain *host;

	struct {
		u32 stat;
		u32 mask;
	} __iomem *regs;
};

#define NUM_IRQS 32

static void pq2ads_pci_mask_irq(struct irq_data *d)
{
	struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
	int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;

	if (irq != -1) {
		unsigned long flags;
		raw_spin_lock_irqsave(&pci_pic_lock, flags);

		setbits32(&priv->regs->mask, 1 << irq);
		mb();

		raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
	}
}

static void pq2ads_pci_unmask_irq(struct irq_data *d)
{
	struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
	int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;

	if (irq != -1) {
		unsigned long flags;

		raw_spin_lock_irqsave(&pci_pic_lock, flags);
		clrbits32(&priv->regs->mask, 1 << irq);
		raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
	}
}

static struct irq_chip pq2ads_pci_ic = {
	.name = "PQ2 ADS PCI",
	.irq_mask = pq2ads_pci_mask_irq,
	.irq_mask_ack = pq2ads_pci_mask_irq,
	.irq_ack = pq2ads_pci_mask_irq,
	.irq_unmask = pq2ads_pci_unmask_irq,
	.irq_enable = pq2ads_pci_unmask_irq,
	.irq_disable = pq2ads_pci_mask_irq
};

static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
	u32 stat, mask, pend;
	int bit;

	for (;;) {
		stat = in_be32(&priv->regs->stat);
		mask = in_be32(&priv->regs->mask);

		pend = stat & ~mask;

		if (!pend)
			break;

		for (bit = 0; pend != 0; ++bit, pend <<= 1) {
			if (pend & 0x80000000) {
				int virq = irq_linear_revmap(priv->host, bit);
				generic_handle_irq(virq);
			}
		}
	}
}

static int pci_pic_host_map(struct irq_domain *h, unsigned int virq,
			    irq_hw_number_t hw)
{
	irq_set_status_flags(virq, IRQ_LEVEL);
	irq_set_chip_data(virq, h->host_data);
	irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
	return 0;
}

static const struct irq_domain_ops pci_pic_host_ops = {
	.map = pci_pic_host_map,
};

int __init pq2ads_pci_init_irq(void)
{
	struct pq2ads_pci_pic *priv;
	struct irq_domain *host;
	struct device_node *np;
	int ret = -ENODEV;
	int irq;

	np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
	if (!np) {
		printk(KERN_ERR "No pci pic node in device tree.\n");
		of_node_put(np);
		goto out;
	}

	irq = irq_of_parse_and_map(np, 0);
	if (irq == NO_IRQ) {
		printk(KERN_ERR "No interrupt in pci pic node.\n");
		of_node_put(np);
		goto out;
	}

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		of_node_put(np);
		ret = -ENOMEM;
		goto out_unmap_irq;
	}

	/* PCI interrupt controller registers: status and mask */
	priv->regs = of_iomap(np, 0);
	if (!priv->regs) {
		printk(KERN_ERR "Cannot map PCI PIC registers.\n");
		goto out_free_kmalloc;
	}

	/* mask all PCI interrupts */
	out_be32(&priv->regs->mask, ~0);
	mb();

	host = irq_domain_add_linear(np, NUM_IRQS, &pci_pic_host_ops, priv);
	if (!host) {
		ret = -ENOMEM;
		goto out_unmap_regs;
	}

	priv->host = host;
	irq_set_handler_data(irq, priv);
	irq_set_chained_handler(irq, pq2ads_pci_irq_demux);

	of_node_put(np);
	return 0;

out_unmap_regs:
	iounmap(priv->regs);
out_free_kmalloc:
	kfree(priv);
	of_node_put(np);
out_unmap_irq:
	irq_dispose_mapping(irq);
out:
	return ret;
}
Commit	Line	Data
e00c5498 SW	1	/*
	2	* PQ2 ADS-style PCI interrupt controller
	3	*
	4	* Copyright 2007 Freescale Semiconductor, Inc.
	5	* Author: Scott Wood <scottwood@freescale.com>
	6	*
	7	* Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
	8	* Copyright (c) 2006 MontaVista Software, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published
	12	* by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/spinlock.h>
	17	#include <linux/irq.h>
	18	#include <linux/types.h>
5a0e3ad6	19	#include <linux/slab.h>
e00c5498 SW	20
	21	#include <asm/io.h>
	22	#include <asm/prom.h>
	23	#include <asm/cpm2.h>
	24
	25	#include "pq2.h"
	26
0e5d359c	27	static DEFINE_RAW_SPINLOCK(pci_pic_lock);
e00c5498 SW	28
	29	struct pq2ads_pci_pic {
	30	struct device_node *node;
bae1d8f1	31	struct irq_domain *host;
e00c5498 SW	32
	33	struct {
	34	u32 stat;
	35	u32 mask;
	36	} __iomem *regs;
	37	};
	38
	39	#define NUM_IRQS 32
	40
e4891eb0	41	static void pq2ads_pci_mask_irq(struct irq_data *d)
e00c5498	42	{
e4891eb0	43	struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
476eb491	44	int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
e00c5498 SW	45
	46	if (irq != -1) {
	47	unsigned long flags;
0e5d359c	48	raw_spin_lock_irqsave(&pci_pic_lock, flags);
e00c5498 SW	49
	50	setbits32(&priv->regs->mask, 1 << irq);
	51	mb();
	52
0e5d359c	53	raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
e00c5498 SW	54	}
	55	}
	56
e4891eb0	57	static void pq2ads_pci_unmask_irq(struct irq_data *d)
e00c5498	58	{
e4891eb0	59	struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
476eb491	60	int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
e00c5498 SW	61
	62	if (irq != -1) {
	63	unsigned long flags;
	64
0e5d359c	65	raw_spin_lock_irqsave(&pci_pic_lock, flags);
e00c5498	66	clrbits32(&priv->regs->mask, 1 << irq);
0e5d359c	67	raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
e00c5498 SW	68	}
	69	}
	70
	71	static struct irq_chip pq2ads_pci_ic = {
e00c5498	72	.name = "PQ2 ADS PCI",
e4891eb0 LB	73	.irq_mask = pq2ads_pci_mask_irq,
	74	.irq_mask_ack = pq2ads_pci_mask_irq,
	75	.irq_ack = pq2ads_pci_mask_irq,
	76	.irq_unmask = pq2ads_pci_unmask_irq,
	77	.irq_enable = pq2ads_pci_unmask_irq,
	78	.irq_disable = pq2ads_pci_mask_irq
e00c5498 SW	79	};
	80
	81	static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
	82	{
ec775d0e	83	struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
e00c5498 SW	84	u32 stat, mask, pend;
	85	int bit;
	86
	87	for (;;) {
	88	stat = in_be32(&priv->regs->stat);
	89	mask = in_be32(&priv->regs->mask);
	90
	91	pend = stat & ~mask;
	92
	93	if (!pend)
	94	break;
	95
	96	for (bit = 0; pend != 0; ++bit, pend <<= 1) {
	97	if (pend & 0x80000000) {
	98	int virq = irq_linear_revmap(priv->host, bit);
	99	generic_handle_irq(virq);
	100	}
	101	}
	102	}
	103	}
	104
bae1d8f1	105	static int pci_pic_host_map(struct irq_domain *h, unsigned int virq,
e00c5498 SW	106	irq_hw_number_t hw)
e00c5498 SW	107	{
98488db9	108	irq_set_status_flags(virq, IRQ_LEVEL);
ec775d0e TG	109	irq_set_chip_data(virq, h->host_data);
ec775d0e TG	110	irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
e00c5498 SW	111	return 0;
	112	}
	113
9f70b8eb	114	static const struct irq_domain_ops pci_pic_host_ops = {
e00c5498	115	.map = pci_pic_host_map,
e00c5498 SW	116	};
	117
	118	int __init pq2ads_pci_init_irq(void)
	119	{
	120	struct pq2ads_pci_pic *priv;
bae1d8f1	121	struct irq_domain *host;
e00c5498 SW	122	struct device_node *np;
	123	int ret = -ENODEV;
	124	int irq;
	125
	126	np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
	127	if (!np) {
	128	printk(KERN_ERR "No pci pic node in device tree.\n");
	129	of_node_put(np);
	130	goto out;
	131	}
	132
	133	irq = irq_of_parse_and_map(np, 0);
	134	if (irq == NO_IRQ) {
	135	printk(KERN_ERR "No interrupt in pci pic node.\n");
	136	of_node_put(np);
	137	goto out;
	138	}
	139
ea96025a	140	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
e00c5498 SW	141	if (!priv) {
	142	of_node_put(np);
	143	ret = -ENOMEM;
	144	goto out_unmap_irq;
	145	}
	146
	147	/* PCI interrupt controller registers: status and mask */
	148	priv->regs = of_iomap(np, 0);
	149	if (!priv->regs) {
	150	printk(KERN_ERR "Cannot map PCI PIC registers.\n");
03737439	151	goto out_free_kmalloc;
e00c5498 SW	152	}
	153
	154	/* mask all PCI interrupts */
	155	out_be32(&priv->regs->mask, ~0);
	156	mb();
	157
a8db8cf0	158	host = irq_domain_add_linear(np, NUM_IRQS, &pci_pic_host_ops, priv);
e00c5498 SW	159	if (!host) {
	160	ret = -ENOMEM;
	161	goto out_unmap_regs;
	162	}
	163
e00c5498	164	priv->host = host;
ec775d0e TG	165	irq_set_handler_data(irq, priv);
ec775d0e TG	166	irq_set_chained_handler(irq, pq2ads_pci_irq_demux);
e00c5498 SW	167
	168	of_node_put(np);
	169	return 0;
	170
	171	out_unmap_regs:
	172	iounmap(priv->regs);
03737439 JK	173	out_free_kmalloc:
03737439 JK	174	kfree(priv);
e00c5498 SW	175	of_node_put(np);
	176	out_unmap_irq:
	177	irq_dispose_mapping(irq);
	178	out:
	179	return ret;
	180	}