projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 30f59336 KG |
1 | /* |
| 2 | * misc setup functions for MPC83xx | |
| 3 | * | |
| 4 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify it | |
| 7 | * under the terms of the GNU General Public License as published by the | |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 9 | * option) any later version. | |
| 10 | */ | |
| 11 | ||
| 30f59336 KG |
12 | #include <linux/stddef.h> |
| 13 | #include <linux/kernel.h> | |
| d4fb5ebd | 14 | #include <linux/of_platform.h> |
| 30f59336 KG |
15 | |
| 16 | #include <asm/io.h> | |
| 17 | #include <asm/hw_irq.h> | |
| d4fb5ebd DES |
18 | #include <asm/ipic.h> |
| 19 | #include <asm/qe_ic.h> | |
| 30f59336 KG |
20 | #include <sysdev/fsl_soc.h> |
| 21 | ||
| 22 | #include "mpc83xx.h" | |
| 23 | ||
| c75f902b KG |
24 | static __be32 __iomem *restart_reg_base; |
| 25 | ||
| 26 | static int __init mpc83xx_restart_init(void) | |
| 27 | { | |
| 28 | /* map reset restart_reg_baseister space */ | |
| 29 | restart_reg_base = ioremap(get_immrbase() + 0x900, 0xff); | |
| 30 | ||
| 31 | return 0; | |
| 32 | } | |
| 33 | ||
| 34 | arch_initcall(mpc83xx_restart_init); | |
| 35 | ||
| 30f59336 KG |
36 | void mpc83xx_restart(char *cmd) |
| 37 | { | |
| 38 | #define RST_OFFSET 0x00000900 | |
| 39 | #define RST_PROT_REG 0x00000018 | |
| 40 | #define RST_CTRL_REG 0x0000001c | |
| 30f59336 KG |
41 | |
| 42 | local_irq_disable(); | |
| 43 | ||
| c75f902b KG |
44 | if (restart_reg_base) { |
| 45 | /* enable software reset "RSTE" */ | |
| 46 | out_be32(restart_reg_base + (RST_PROT_REG >> 2), 0x52535445); | |
| 47 | ||
| 48 | /* set software hard reset */ | |
| 49 | out_be32(restart_reg_base + (RST_CTRL_REG >> 2), 0x2); | |
| 50 | } else { | |
| 51 | printk (KERN_EMERG "Error: Restart registers not mapped, spinning!\n"); | |
| 52 | } | |
| 30f59336 | 53 | |
| 30f59336 KG |
54 | for (;;) ; |
| 55 | } | |
| 56 | ||
| 57 | long __init mpc83xx_time_init(void) | |
| 58 | { | |
| 59 | #define SPCR_OFFSET 0x00000110 | |
| 60 | #define SPCR_TBEN 0x00400000 | |
| 61 | __be32 __iomem *spcr = ioremap(get_immrbase() + SPCR_OFFSET, 4); | |
| 62 | __be32 tmp; | |
| 63 | ||
| 64 | tmp = in_be32(spcr); | |
| 65 | out_be32(spcr, tmp | SPCR_TBEN); | |
| 66 | ||
| 67 | iounmap(spcr); | |
| 68 | ||
| 69 | return 0; | |
| 70 | } | |
| d4fb5ebd DES |
71 | |
| 72 | void __init mpc83xx_ipic_init_IRQ(void) | |
| 73 | { | |
| 74 | struct device_node *np; | |
| 75 | ||
| 76 | /* looking for fsl,pq2pro-pic which is asl compatible with fsl,ipic */ | |
| 77 | np = of_find_compatible_node(NULL, NULL, "fsl,ipic"); | |
| 78 | if (!np) | |
| 79 | np = of_find_node_by_type(NULL, "ipic"); | |
| 80 | if (!np) | |
| 81 | return; | |
| 82 | ||
| 83 | ipic_init(np, 0); | |
| 84 | ||
| 85 | of_node_put(np); | |
| 86 | ||
| 87 | /* Initialize the default interrupt mapping priorities, | |
| 88 | * in case the boot rom changed something on us. | |
| 89 | */ | |
| 90 | ipic_set_default_priority(); | |
| 91 | } | |
| 92 | ||
| 93 | #ifdef CONFIG_QUICC_ENGINE | |
| 94 | void __init mpc83xx_qe_init_IRQ(void) | |
| 95 | { | |
| 96 | struct device_node *np; | |
| 97 | ||
| 98 | np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); | |
| 99 | if (!np) { | |
| 100 | np = of_find_node_by_type(NULL, "qeic"); | |
| 101 | if (!np) | |
| 102 | return; | |
| 103 | } | |
| 104 | qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic); | |
| 105 | of_node_put(np); | |
| 106 | } | |
| 107 | ||
| 108 | void __init mpc83xx_ipic_and_qe_init_IRQ(void) | |
| 109 | { | |
| 110 | mpc83xx_ipic_init_IRQ(); | |
| 111 | mpc83xx_qe_init_IRQ(); | |
| 112 | } | |
| 113 | #endif /* CONFIG_QUICC_ENGINE */ |