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9020fc96 KP |
1 | /* |
2 | * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. | |
3 | * | |
4 | * Description: | |
5 | * MPC832xE MDS board specific routines. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/stddef.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/reboot.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/kdev_t.h> | |
20 | #include <linux/major.h> | |
21 | #include <linux/console.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/seq_file.h> | |
24 | #include <linux/root_dev.h> | |
25 | #include <linux/initrd.h> | |
882407b9 JL |
26 | #include <linux/of_platform.h> |
27 | #include <linux/of_device.h> | |
9020fc96 KP |
28 | |
29 | #include <asm/system.h> | |
30 | #include <asm/atomic.h> | |
31 | #include <asm/time.h> | |
32 | #include <asm/io.h> | |
33 | #include <asm/machdep.h> | |
34 | #include <asm/ipic.h> | |
9020fc96 KP |
35 | #include <asm/irq.h> |
36 | #include <asm/prom.h> | |
37 | #include <asm/udbg.h> | |
38 | #include <sysdev/fsl_soc.h> | |
76fe1ffc | 39 | #include <sysdev/fsl_pci.h> |
9020fc96 KP |
40 | #include <asm/qe.h> |
41 | #include <asm/qe_ic.h> | |
42 | ||
43 | #include "mpc83xx.h" | |
9020fc96 KP |
44 | |
45 | #undef DEBUG | |
46 | #ifdef DEBUG | |
47 | #define DBG(fmt...) udbg_printf(fmt) | |
48 | #else | |
49 | #define DBG(fmt...) | |
50 | #endif | |
51 | ||
9020fc96 KP |
52 | /* ************************************************************************ |
53 | * | |
54 | * Setup the architecture | |
55 | * | |
56 | */ | |
57 | static void __init mpc832x_sys_setup_arch(void) | |
58 | { | |
59 | struct device_node *np; | |
81b36a0b | 60 | u8 __iomem *bcsr_regs = NULL; |
9020fc96 KP |
61 | |
62 | if (ppc_md.progress) | |
63 | ppc_md.progress("mpc832x_sys_setup_arch()", 0); | |
64 | ||
9020fc96 KP |
65 | /* Map BCSR area */ |
66 | np = of_find_node_by_name(NULL, "bcsr"); | |
81b36a0b | 67 | if (np) { |
9020fc96 KP |
68 | struct resource res; |
69 | ||
70 | of_address_to_resource(np, 0, &res); | |
28f65c11 | 71 | bcsr_regs = ioremap(res.start, resource_size(&res)); |
9020fc96 KP |
72 | of_node_put(np); |
73 | } | |
74 | ||
75 | #ifdef CONFIG_PCI | |
c9438aff | 76 | for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") |
09b55f76 | 77 | mpc83xx_add_bridge(np); |
9020fc96 KP |
78 | #endif |
79 | ||
80 | #ifdef CONFIG_QUICC_ENGINE | |
81 | qe_reset(); | |
82 | ||
06cd9396 | 83 | if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { |
9020fc96 KP |
84 | par_io_init(np); |
85 | of_node_put(np); | |
86 | ||
87 | for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) | |
88 | par_io_of_config(np); | |
89 | } | |
90 | ||
91 | if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) | |
92 | != NULL){ | |
d8ecbb93 KP |
93 | /* Reset the Ethernet PHYs */ |
94 | #define BCSR8_FETH_RST 0x50 | |
81b36a0b | 95 | clrbits8(&bcsr_regs[8], BCSR8_FETH_RST); |
9020fc96 | 96 | udelay(1000); |
81b36a0b | 97 | setbits8(&bcsr_regs[8], BCSR8_FETH_RST); |
9020fc96 KP |
98 | iounmap(bcsr_regs); |
99 | of_node_put(np); | |
100 | } | |
9020fc96 | 101 | #endif /* CONFIG_QUICC_ENGINE */ |
9020fc96 KP |
102 | } |
103 | ||
f7993ed5 KG |
104 | static struct of_device_id mpc832x_ids[] = { |
105 | { .type = "soc", }, | |
106 | { .compatible = "soc", }, | |
cf0d19fb | 107 | { .compatible = "simple-bus", }, |
f7993ed5 | 108 | { .type = "qe", }, |
a2dd70a1 | 109 | { .compatible = "fsl,qe", }, |
f7993ed5 KG |
110 | {}, |
111 | }; | |
112 | ||
8746ed3d KP |
113 | static int __init mpc832x_declare_of_platform_devices(void) |
114 | { | |
f7993ed5 KG |
115 | /* Publish the QE devices */ |
116 | of_platform_bus_probe(NULL, mpc832x_ids, NULL); | |
8746ed3d KP |
117 | |
118 | return 0; | |
119 | } | |
6392f184 | 120 | machine_device_initcall(mpc832x_mds, mpc832x_declare_of_platform_devices); |
8746ed3d | 121 | |
e60bd7f1 | 122 | static void __init mpc832x_sys_init_IRQ(void) |
9020fc96 | 123 | { |
9020fc96 KP |
124 | struct device_node *np; |
125 | ||
126 | np = of_find_node_by_type(NULL, "ipic"); | |
127 | if (!np) | |
128 | return; | |
129 | ||
130 | ipic_init(np, 0); | |
131 | ||
132 | /* Initialize the default interrupt mapping priorities, | |
133 | * in case the boot rom changed something on us. | |
134 | */ | |
135 | ipic_set_default_priority(); | |
136 | of_node_put(np); | |
137 | ||
138 | #ifdef CONFIG_QUICC_ENGINE | |
a2dd70a1 AV |
139 | np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); |
140 | if (!np) { | |
141 | np = of_find_node_by_type(NULL, "qeic"); | |
142 | if (!np) | |
143 | return; | |
144 | } | |
cccd2102 | 145 | qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic); |
9020fc96 KP |
146 | of_node_put(np); |
147 | #endif /* CONFIG_QUICC_ENGINE */ | |
148 | } | |
149 | ||
9020fc96 KP |
150 | /* |
151 | * Called very early, MMU is off, device-tree isn't unflattened | |
152 | */ | |
153 | static int __init mpc832x_sys_probe(void) | |
154 | { | |
336c3c2e | 155 | unsigned long root = of_get_flat_dt_root(); |
9020fc96 | 156 | |
336c3c2e | 157 | return of_flat_dt_is_compatible(root, "MPC832xMDS"); |
9020fc96 KP |
158 | } |
159 | ||
160 | define_machine(mpc832x_mds) { | |
161 | .name = "MPC832x MDS", | |
162 | .probe = mpc832x_sys_probe, | |
163 | .setup_arch = mpc832x_sys_setup_arch, | |
164 | .init_IRQ = mpc832x_sys_init_IRQ, | |
165 | .get_irq = ipic_get_irq, | |
166 | .restart = mpc83xx_restart, | |
167 | .time_init = mpc83xx_time_init, | |
168 | .calibrate_decr = generic_calibrate_decr, | |
169 | .progress = udbg_progress, | |
170 | }; |