spi_mpc83xx: rework chip selects handling
[deliverable/linux.git] / arch / powerpc / platforms / 83xx / mpc832x_rdb.c
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1/*
2 * arch/powerpc/platforms/83xx/mpc832x_rdb.c
3 *
4 * Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved.
5 *
6 * Description:
7 * MPC832x RDB board specific routines.
8 * This file is based on mpc832x_mds.c and mpc8313_rdb.c
9 * Author: Michael Barkowski <michael.barkowski@freescale.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/pci.h>
ba3bdff5 18#include <linux/interrupt.h>
8237bf08 19#include <linux/spi/spi.h>
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20#include <linux/spi/mmc_spi.h>
21#include <linux/mmc/host.h>
882407b9 22#include <linux/of_platform.h>
23308c54 23
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24#include <asm/time.h>
25#include <asm/ipic.h>
26#include <asm/udbg.h>
27#include <asm/qe.h>
28#include <asm/qe_ic.h>
8237bf08 29#include <sysdev/fsl_soc.h>
76fe1ffc 30#include <sysdev/fsl_pci.h>
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31
32#include "mpc83xx.h"
33
34#undef DEBUG
35#ifdef DEBUG
36#define DBG(fmt...) udbg_printf(fmt)
37#else
38#define DBG(fmt...)
39#endif
40
20cfb41b 41#ifdef CONFIG_QUICC_ENGINE
364fdbc0 42static void mpc83xx_spi_cs_control(struct spi_device *spi, bool on)
8237bf08 43{
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44 pr_debug("%s %d %d\n", __func__, spi->chip_select, on);
45 par_io_data_set(3, 13, on);
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46}
47
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48static struct mmc_spi_platform_data mpc832x_mmc_pdata = {
49 .ocr_mask = MMC_VDD_33_34,
50};
51
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52static struct spi_board_info mpc832x_spi_boardinfo = {
53 .bus_num = 0x4c0,
54 .chip_select = 0,
55 .max_speed_hz = 50000000,
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56 .modalias = "mmc_spi",
57 .platform_data = &mpc832x_mmc_pdata,
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58};
59
60static int __init mpc832x_spi_init(void)
61{
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62 par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */
63 par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */
64 par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */
65 par_io_config_pin(3, 3, 2, 0, 1, 0); /* SPI1 SEL, I */
66
67 par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS, O */
68 par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */
69 par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */
70
364fdbc0 71 return fsl_spi_init(&mpc832x_spi_boardinfo, 1, mpc83xx_spi_cs_control);
8237bf08 72}
6392f184 73machine_device_initcall(mpc832x_rdb, mpc832x_spi_init);
20cfb41b 74#endif /* CONFIG_QUICC_ENGINE */
8237bf08 75
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76/* ************************************************************************
77 *
78 * Setup the architecture
79 *
80 */
81static void __init mpc832x_rdb_setup_arch(void)
82{
c9ec87e5 83#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
23308c54 84 struct device_node *np;
c9ec87e5 85#endif
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86
87 if (ppc_md.progress)
88 ppc_md.progress("mpc832x_rdb_setup_arch()", 0);
89
90#ifdef CONFIG_PCI
c9438aff 91 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
09b55f76 92 mpc83xx_add_bridge(np);
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93#endif
94
95#ifdef CONFIG_QUICC_ENGINE
96 qe_reset();
97
aafa1955 98 if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
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99 par_io_init(np);
100 of_node_put(np);
101
102 for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
103 par_io_of_config(np);
104 }
105#endif /* CONFIG_QUICC_ENGINE */
106}
107
108static struct of_device_id mpc832x_ids[] = {
109 { .type = "soc", },
110 { .compatible = "soc", },
cf0d19fb 111 { .compatible = "simple-bus", },
23308c54 112 { .type = "qe", },
a2dd70a1 113 { .compatible = "fsl,qe", },
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114 {},
115};
116
117static int __init mpc832x_declare_of_platform_devices(void)
118{
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119 /* Publish the QE devices */
120 of_platform_bus_probe(NULL, mpc832x_ids, NULL);
121
122 return 0;
123}
6392f184 124machine_device_initcall(mpc832x_rdb, mpc832x_declare_of_platform_devices);
23308c54 125
81b36a0b 126static void __init mpc832x_rdb_init_IRQ(void)
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127{
128
129 struct device_node *np;
130
131 np = of_find_node_by_type(NULL, "ipic");
132 if (!np)
133 return;
134
135 ipic_init(np, 0);
136
137 /* Initialize the default interrupt mapping priorities,
138 * in case the boot rom changed something on us.
139 */
140 ipic_set_default_priority();
141 of_node_put(np);
142
143#ifdef CONFIG_QUICC_ENGINE
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144 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
145 if (!np) {
146 np = of_find_node_by_type(NULL, "qeic");
147 if (!np)
148 return;
149 }
cccd2102 150 qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
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151 of_node_put(np);
152#endif /* CONFIG_QUICC_ENGINE */
153}
154
155/*
156 * Called very early, MMU is off, device-tree isn't unflattened
157 */
158static int __init mpc832x_rdb_probe(void)
159{
160 unsigned long root = of_get_flat_dt_root();
161
162 return of_flat_dt_is_compatible(root, "MPC832xRDB");
163}
164
165define_machine(mpc832x_rdb) {
166 .name = "MPC832x RDB",
167 .probe = mpc832x_rdb_probe,
168 .setup_arch = mpc832x_rdb_setup_arch,
169 .init_IRQ = mpc832x_rdb_init_IRQ,
170 .get_irq = ipic_get_irq,
171 .restart = mpc83xx_restart,
172 .time_init = mpc83xx_time_init,
173 .calibrate_decr = generic_calibrate_decr,
174 .progress = udbg_progress,
175};
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