[deliverable/linux.git] / arch / powerpc / platforms / 83xx / usb.c

/*
 * Freescale 83xx USB SOC setup code
 *
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 * Author: Li Yang
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */


#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/of.h>

#include <asm/io.h>
#include <asm/prom.h>
#include <sysdev/fsl_soc.h>

#include "mpc83xx.h"


#ifdef CONFIG_PPC_MPC834x
int mpc834x_usb_cfg(void)
{
	unsigned long sccr, sicrl, sicrh;
	void __iomem *immap;
	struct device_node *np = NULL;
	int port0_is_dr = 0, port1_is_dr = 0;
	const void *prop, *dr_mode;

	immap = ioremap(get_immrbase(), 0x1000);
	if (!immap)
		return -ENOMEM;

	/* Read registers */
	/* Note: DR and MPH must use the same clock setting in SCCR */
	sccr = in_be32(immap + MPC83XX_SCCR_OFFS) & ~MPC83XX_SCCR_USB_MASK;
	sicrl = in_be32(immap + MPC83XX_SICRL_OFFS) & ~MPC834X_SICRL_USB_MASK;
	sicrh = in_be32(immap + MPC83XX_SICRH_OFFS) & ~MPC834X_SICRH_USB_UTMI;

	np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
	if (np) {
		sccr |= MPC83XX_SCCR_USB_DRCM_11;  /* 1:3 */

		prop = of_get_property(np, "phy_type", NULL);
		if (prop && (!strcmp(prop, "utmi") ||
					!strcmp(prop, "utmi_wide"))) {
			sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
			sicrh |= MPC834X_SICRH_USB_UTMI;
			port1_is_dr = 1;
		} else if (prop && !strcmp(prop, "serial")) {
			dr_mode = of_get_property(np, "dr_mode", NULL);
			if (dr_mode && !strcmp(dr_mode, "otg")) {
				sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
				port1_is_dr = 1;
			} else {
				sicrl |= MPC834X_SICRL_USB0;
			}
		} else if (prop && !strcmp(prop, "ulpi")) {
			sicrl |= MPC834X_SICRL_USB0;
		} else {
			printk(KERN_WARNING "834x USB PHY type not supported\n");
		}
		port0_is_dr = 1;
		of_node_put(np);
	}
	np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph");
	if (np) {
		sccr |= MPC83XX_SCCR_USB_MPHCM_11; /* 1:3 */

		prop = of_get_property(np, "port0", NULL);
		if (prop) {
			if (port0_is_dr)
				printk(KERN_WARNING
					"834x USB port0 can't be used by both DR and MPH!\n");
			sicrl &= ~MPC834X_SICRL_USB0;
		}
		prop = of_get_property(np, "port1", NULL);
		if (prop) {
			if (port1_is_dr)
				printk(KERN_WARNING
					"834x USB port1 can't be used by both DR and MPH!\n");
			sicrl &= ~MPC834X_SICRL_USB1;
		}
		of_node_put(np);
	}

	/* Write back */
	out_be32(immap + MPC83XX_SCCR_OFFS, sccr);
	out_be32(immap + MPC83XX_SICRL_OFFS, sicrl);
	out_be32(immap + MPC83XX_SICRH_OFFS, sicrh);

	iounmap(immap);
	return 0;
}
#endif /* CONFIG_PPC_MPC834x */

#ifdef CONFIG_PPC_MPC831x
int mpc831x_usb_cfg(void)
{
	u32 temp;
	void __iomem *immap, *usb_regs;
	struct device_node *np = NULL;
	struct device_node *immr_node = NULL;
	const void *prop;
	struct resource res;
	int ret = 0;
#ifdef CONFIG_USB_OTG
	const void *dr_mode;
#endif

	np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
	if (!np)
		return -ENODEV;
	prop = of_get_property(np, "phy_type", NULL);

	/* Map IMMR space for pin and clock settings */
	immap = ioremap(get_immrbase(), 0x1000);
	if (!immap) {
		of_node_put(np);
		return -ENOMEM;
	}

	/* Configure clock */
	immr_node = of_get_parent(np);
	if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
		clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
		                MPC8315_SCCR_USB_MASK,
		                MPC8315_SCCR_USB_DRCM_01);
	else
		clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
		                MPC83XX_SCCR_USB_MASK,
		                MPC83XX_SCCR_USB_DRCM_11);

	/* Configure pin mux for ULPI.  There is no pin mux for UTMI */
	if (prop && !strcmp(prop, "ulpi")) {
		if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) {
			clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
					MPC8315_SICRL_USB_MASK,
					MPC8315_SICRL_USB_ULPI);
			clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
					MPC8315_SICRH_USB_MASK,
					MPC8315_SICRH_USB_ULPI);
		} else {
			clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
					MPC831X_SICRL_USB_MASK,
					MPC831X_SICRL_USB_ULPI);
			clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
					MPC831X_SICRH_USB_MASK,
					MPC831X_SICRH_USB_ULPI);
		}
	}

	iounmap(immap);

	if (immr_node)
		of_node_put(immr_node);

	/* Map USB SOC space */
	ret = of_address_to_resource(np, 0, &res);
	if (ret) {
		of_node_put(np);
		return ret;
	}
	usb_regs = ioremap(res.start, res.end - res.start + 1);

	/* Using on-chip PHY */
	if (prop && (!strcmp(prop, "utmi_wide") ||
		     !strcmp(prop, "utmi"))) {
		u32 refsel;

		if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
			refsel = CONTROL_REFSEL_24MHZ;
		else
			refsel = CONTROL_REFSEL_48MHZ;
		/* Set UTMI_PHY_EN and REFSEL */
		out_be32(usb_regs + FSL_USB2_CONTROL_OFFS,
				CONTROL_UTMI_PHY_EN | refsel);
	/* Using external UPLI PHY */
	} else if (prop && !strcmp(prop, "ulpi")) {
		/* Set PHY_CLK_SEL to ULPI */
		temp = CONTROL_PHY_CLK_SEL_ULPI;
#ifdef CONFIG_USB_OTG
		/* Set OTG_PORT */
		dr_mode = of_get_property(np, "dr_mode", NULL);
		if (dr_mode && !strcmp(dr_mode, "otg"))
			temp |= CONTROL_OTG_PORT;
#endif /* CONFIG_USB_OTG */
		out_be32(usb_regs + FSL_USB2_CONTROL_OFFS, temp);
	} else {
		printk(KERN_WARNING "831x USB PHY type not supported\n");
		ret = -EINVAL;
	}

	iounmap(usb_regs);
	of_node_put(np);
	return ret;
}
#endif /* CONFIG_PPC_MPC831x */

#ifdef CONFIG_PPC_MPC837x
int mpc837x_usb_cfg(void)
{
	void __iomem *immap;
	struct device_node *np = NULL;
	const void *prop;
	int ret = 0;

	np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
	if (!np || !of_device_is_available(np))
		return -ENODEV;
	prop = of_get_property(np, "phy_type", NULL);

	if (!prop || (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) {
		printk(KERN_WARNING "837x USB PHY type not supported\n");
		of_node_put(np);
		return -EINVAL;
	}

	/* Map IMMR space for pin and clock settings */
	immap = ioremap(get_immrbase(), 0x1000);
	if (!immap) {
		of_node_put(np);
		return -ENOMEM;
	}

	/* Configure clock */
	clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11,
			MPC837X_SCCR_USB_DRCM_11);

	/* Configure pin mux for ULPI/serial */
	clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK,
			MPC837X_SICRL_USB_ULPI);

	iounmap(immap);
	of_node_put(np);
	return ret;
}
#endif /* CONFIG_PPC_MPC837x */
Commit	Line	Data
e5a94af8 LY	1	/*
	2	* Freescale 83xx USB SOC setup code
	3	*
	4	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	5	* Author: Li Yang
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*/
	12
	13
	14	#include <linux/stddef.h>
	15	#include <linux/kernel.h>
	16	#include <linux/errno.h>
c026c987	17	#include <linux/of.h>
e5a94af8 LY	18
	19	#include <asm/io.h>
	20	#include <asm/prom.h>
	21	#include <sysdev/fsl_soc.h>
	22
	23	#include "mpc83xx.h"
	24
	25
b38308ac	26	#ifdef CONFIG_PPC_MPC834x
e5a94af8 LY	27	int mpc834x_usb_cfg(void)
	28	{
	29	unsigned long sccr, sicrl, sicrh;
	30	void __iomem *immap;
	31	struct device_node *np = NULL;
	32	int port0_is_dr = 0, port1_is_dr = 0;
	33	const void prop, dr_mode;
	34
	35	immap = ioremap(get_immrbase(), 0x1000);
	36	if (!immap)
	37	return -ENOMEM;
	38
	39	/* Read registers */
	40	/* Note: DR and MPH must use the same clock setting in SCCR */
	41	sccr = in_be32(immap + MPC83XX_SCCR_OFFS) & ~MPC83XX_SCCR_USB_MASK;
	42	sicrl = in_be32(immap + MPC83XX_SICRL_OFFS) & ~MPC834X_SICRL_USB_MASK;
	43	sicrh = in_be32(immap + MPC83XX_SICRH_OFFS) & ~MPC834X_SICRH_USB_UTMI;
	44
866b6ddd	45	np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
e5a94af8 LY	46	if (np) {
	47	sccr \|= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */
	48
	49	prop = of_get_property(np, "phy_type", NULL);
	50	if (prop && (!strcmp(prop, "utmi") \|\|
	51	!strcmp(prop, "utmi_wide"))) {
	52	sicrl \|= MPC834X_SICRL_USB0 \| MPC834X_SICRL_USB1;
	53	sicrh \|= MPC834X_SICRH_USB_UTMI;
	54	port1_is_dr = 1;
	55	} else if (prop && !strcmp(prop, "serial")) {
	56	dr_mode = of_get_property(np, "dr_mode", NULL);
	57	if (dr_mode && !strcmp(dr_mode, "otg")) {
	58	sicrl \|= MPC834X_SICRL_USB0 \| MPC834X_SICRL_USB1;
	59	port1_is_dr = 1;
	60	} else {
	61	sicrl \|= MPC834X_SICRL_USB0;
	62	}
	63	} else if (prop && !strcmp(prop, "ulpi")) {
	64	sicrl \|= MPC834X_SICRL_USB0;
	65	} else {
	66	printk(KERN_WARNING "834x USB PHY type not supported\n");
	67	}
	68	port0_is_dr = 1;
	69	of_node_put(np);
	70	}
866b6ddd	71	np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph");
e5a94af8 LY	72	if (np) {
	73	sccr \|= MPC83XX_SCCR_USB_MPHCM_11; /* 1:3 */
	74
	75	prop = of_get_property(np, "port0", NULL);
	76	if (prop) {
	77	if (port0_is_dr)
	78	printk(KERN_WARNING
	79	"834x USB port0 can't be used by both DR and MPH!\n");
39db0fd9	80	sicrl &= ~MPC834X_SICRL_USB0;
e5a94af8 LY	81	}
	82	prop = of_get_property(np, "port1", NULL);
	83	if (prop) {
	84	if (port1_is_dr)
	85	printk(KERN_WARNING
	86	"834x USB port1 can't be used by both DR and MPH!\n");
39db0fd9	87	sicrl &= ~MPC834X_SICRL_USB1;
e5a94af8 LY	88	}
	89	of_node_put(np);
	90	}
	91
	92	/* Write back */
	93	out_be32(immap + MPC83XX_SCCR_OFFS, sccr);
	94	out_be32(immap + MPC83XX_SICRL_OFFS, sicrl);
	95	out_be32(immap + MPC83XX_SICRH_OFFS, sicrh);
	96
	97	iounmap(immap);
	98	return 0;
	99	}
b38308ac	100	#endif /* CONFIG_PPC_MPC834x */
e5a94af8 LY	101
	102	#ifdef CONFIG_PPC_MPC831x
	103	int mpc831x_usb_cfg(void)
	104	{
	105	u32 temp;
	106	void __iomem immap, usb_regs;
	107	struct device_node *np = NULL;
b74a7e50	108	struct device_node *immr_node = NULL;
e5a94af8 LY	109	const void *prop;
	110	struct resource res;
	111	int ret = 0;
	112	#ifdef CONFIG_USB_OTG
	113	const void *dr_mode;
	114	#endif
	115
866b6ddd	116	np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
e5a94af8 LY	117	if (!np)
	118	return -ENODEV;
	119	prop = of_get_property(np, "phy_type", NULL);
	120
	121	/* Map IMMR space for pin and clock settings */
	122	immap = ioremap(get_immrbase(), 0x1000);
	123	if (!immap) {
	124	of_node_put(np);
	125	return -ENOMEM;
	126	}
	127
	128	/* Configure clock */
b74a7e50 KP	129	immr_node = of_get_parent(np);
	130	if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
	131	clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
	132	MPC8315_SCCR_USB_MASK,
1a9ebc0c	133	MPC8315_SCCR_USB_DRCM_01);
b74a7e50 KP	134	else
	135	clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
	136	MPC83XX_SCCR_USB_MASK,
	137	MPC83XX_SCCR_USB_DRCM_11);
e5a94af8 LY	138
e5a94af8 LY	139	/* Configure pin mux for ULPI. There is no pin mux for UTMI */
7ac33417	140	if (prop && !strcmp(prop, "ulpi")) {
c0a20159 AV	141	if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) {
	142	clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
	143	MPC8315_SICRL_USB_MASK,
	144	MPC8315_SICRL_USB_ULPI);
	145	clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
	146	MPC8315_SICRH_USB_MASK,
	147	MPC8315_SICRH_USB_ULPI);
	148	} else {
	149	clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
	150	MPC831X_SICRL_USB_MASK,
	151	MPC831X_SICRL_USB_ULPI);
	152	clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
	153	MPC831X_SICRH_USB_MASK,
	154	MPC831X_SICRH_USB_ULPI);
	155	}
e5a94af8 LY	156	}
	157
	158	iounmap(immap);
	159
b74a7e50 KP	160	if (immr_node)
	161	of_node_put(immr_node);
	162
e5a94af8 LY	163	/* Map USB SOC space */
	164	ret = of_address_to_resource(np, 0, &res);
	165	if (ret) {
	166	of_node_put(np);
	167	return ret;
	168	}
	169	usb_regs = ioremap(res.start, res.end - res.start + 1);
	170
	171	/* Using on-chip PHY */
7ac33417 CG	172	if (prop && (!strcmp(prop, "utmi_wide") \|\|
7ac33417 CG	173	!strcmp(prop, "utmi"))) {
1a9ebc0c AV	174	u32 refsel;
	175
	176	if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
	177	refsel = CONTROL_REFSEL_24MHZ;
	178	else
	179	refsel = CONTROL_REFSEL_48MHZ;
	180	/* Set UTMI_PHY_EN and REFSEL */
e5a94af8	181	out_be32(usb_regs + FSL_USB2_CONTROL_OFFS,
1a9ebc0c	182	CONTROL_UTMI_PHY_EN \| refsel);
e5a94af8	183	/* Using external UPLI PHY */
7ac33417	184	} else if (prop && !strcmp(prop, "ulpi")) {
e5a94af8 LY	185	/* Set PHY_CLK_SEL to ULPI */
	186	temp = CONTROL_PHY_CLK_SEL_ULPI;
	187	#ifdef CONFIG_USB_OTG
	188	/* Set OTG_PORT */
	189	dr_mode = of_get_property(np, "dr_mode", NULL);
	190	if (dr_mode && !strcmp(dr_mode, "otg"))
	191	temp \|= CONTROL_OTG_PORT;
	192	#endif /* CONFIG_USB_OTG */
	193	out_be32(usb_regs + FSL_USB2_CONTROL_OFFS, temp);
	194	} else {
	195	printk(KERN_WARNING "831x USB PHY type not supported\n");
	196	ret = -EINVAL;
	197	}
	198
	199	iounmap(usb_regs);
	200	of_node_put(np);
	201	return ret;
	202	}
	203	#endif /* CONFIG_PPC_MPC831x */
e10241d8 LY	204
	205	#ifdef CONFIG_PPC_MPC837x
	206	int mpc837x_usb_cfg(void)
	207	{
	208	void __iomem *immap;
	209	struct device_node *np = NULL;
	210	const void *prop;
	211	int ret = 0;
	212
866b6ddd	213	np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
c026c987	214	if (!np \|\| !of_device_is_available(np))
e10241d8 LY	215	return -ENODEV;
	216	prop = of_get_property(np, "phy_type", NULL);
	217
	218	if (!prop \|\| (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) {
	219	printk(KERN_WARNING "837x USB PHY type not supported\n");
	220	of_node_put(np);
	221	return -EINVAL;
	222	}
	223
	224	/* Map IMMR space for pin and clock settings */
	225	immap = ioremap(get_immrbase(), 0x1000);
	226	if (!immap) {
	227	of_node_put(np);
	228	return -ENOMEM;
	229	}
	230
	231	/* Configure clock */
	232	clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11,
	233	MPC837X_SCCR_USB_DRCM_11);
	234
	235	/* Configure pin mux for ULPI/serial */
	236	clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK,
	237	MPC837X_SICRL_USB_ULPI);
	238
	239	iounmap(immap);
	240	of_node_put(np);
	241	return ret;
	242	}
	243	#endif /* CONFIG_PPC_MPC837x */