Commit | Line | Data |
---|---|---|
63dafe57 BB |
1 | /* |
2 | * MPC85xx setup and early boot code plus other random bits. | |
3 | * | |
4 | * Maintained by Kumar Gala (see MAINTAINERS for contact information) | |
5 | * | |
6 | * Copyright 2005 Freescale Semiconductor Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
63dafe57 BB |
14 | #include <linux/stddef.h> |
15 | #include <linux/kernel.h> | |
63dafe57 BB |
16 | #include <linux/pci.h> |
17 | #include <linux/kdev_t.h> | |
63dafe57 | 18 | #include <linux/delay.h> |
63dafe57 | 19 | #include <linux/seq_file.h> |
8abc8f5f | 20 | #include <linux/of_platform.h> |
63dafe57 | 21 | |
63dafe57 | 22 | #include <asm/time.h> |
63dafe57 | 23 | #include <asm/machdep.h> |
63dafe57 | 24 | #include <asm/pci-bridge.h> |
63dafe57 BB |
25 | #include <asm/mpic.h> |
26 | #include <mm/mmu_decl.h> | |
27 | #include <asm/udbg.h> | |
28 | ||
29 | #include <sysdev/fsl_soc.h> | |
3f6c5dae | 30 | #include <sysdev/fsl_pci.h> |
63dafe57 | 31 | |
902f392d VB |
32 | #ifdef CONFIG_CPM2 |
33 | #include <asm/cpm2.h> | |
34 | #include <sysdev/cpm2_pic.h> | |
902f392d VB |
35 | #endif |
36 | ||
543a07b1 DES |
37 | #include "mpc85xx.h" |
38 | ||
27630bec | 39 | static void __init mpc85xx_ads_pic_init(void) |
63dafe57 | 40 | { |
e55d7f73 | 41 | struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN, |
b533f8ae | 42 | 0, 256, " OpenPIC "); |
4c86cd9c | 43 | BUG_ON(mpic == NULL); |
4c86cd9c | 44 | mpic_init(mpic); |
902f392d | 45 | |
543a07b1 | 46 | mpc85xx_cpm2_pic_init(); |
63dafe57 BB |
47 | } |
48 | ||
63dafe57 BB |
49 | /* |
50 | * Setup the architecture | |
51 | */ | |
902f392d | 52 | #ifdef CONFIG_CPM2 |
8abc8f5f SW |
53 | struct cpm_pin { |
54 | int port, pin, flags; | |
55 | }; | |
56 | ||
e5091842 | 57 | static const struct cpm_pin mpc8560_ads_pins[] = { |
8abc8f5f SW |
58 | /* SCC1 */ |
59 | {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
60 | {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | |
61 | {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
62 | ||
63 | /* SCC2 */ | |
2308c954 VB |
64 | {2, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
65 | {2, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
8abc8f5f SW |
66 | {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
67 | {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
68 | {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
69 | ||
70 | /* FCC2 */ | |
71 | {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
72 | {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
73 | {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
74 | {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
75 | {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
76 | {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
77 | {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
78 | {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
79 | {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
80 | {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
81 | {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
82 | {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | |
83 | {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
84 | {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
85 | {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */ | |
86 | {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */ | |
87 | ||
88 | /* FCC3 */ | |
89 | {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
90 | {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
91 | {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
8abc8f5f SW |
92 | {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
93 | {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
94 | {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
95 | {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
96 | {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
97 | {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
98 | {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
99 | {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
100 | {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
101 | {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
2308c954 VB |
102 | {2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK16 */ |
103 | {2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK15 */ | |
104 | {2, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
8abc8f5f SW |
105 | }; |
106 | ||
107 | static void __init init_ioports(void) | |
902f392d | 108 | { |
8abc8f5f SW |
109 | int i; |
110 | ||
111 | for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) { | |
a5dc66e2 | 112 | const struct cpm_pin *pin = &mpc8560_ads_pins[i]; |
8abc8f5f | 113 | cpm2_set_pin(pin->port, pin->pin, pin->flags); |
d3465c92 | 114 | } |
902f392d | 115 | |
8abc8f5f SW |
116 | cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX); |
117 | cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX); | |
118 | cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX); | |
119 | cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX); | |
120 | cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX); | |
121 | cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX); | |
122 | cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX); | |
123 | cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX); | |
902f392d VB |
124 | } |
125 | #endif | |
126 | ||
fbc94e7c | 127 | static void __init mpc85xx_ads_setup_arch(void) |
63dafe57 | 128 | { |
63dafe57 BB |
129 | if (ppc_md.progress) |
130 | ppc_md.progress("mpc85xx_ads_setup_arch()", 0); | |
131 | ||
902f392d VB |
132 | #ifdef CONFIG_CPM2 |
133 | cpm2_reset(); | |
8abc8f5f | 134 | init_ioports(); |
902f392d VB |
135 | #endif |
136 | ||
905e75c4 | 137 | fsl_pci_assign_primary(); |
63dafe57 BB |
138 | } |
139 | ||
27630bec | 140 | static void mpc85xx_ads_show_cpuinfo(struct seq_file *m) |
63dafe57 BB |
141 | { |
142 | uint pvid, svid, phid1; | |
63dafe57 BB |
143 | |
144 | pvid = mfspr(SPRN_PVR); | |
145 | svid = mfspr(SPRN_SVR); | |
146 | ||
147 | seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n"); | |
63dafe57 BB |
148 | seq_printf(m, "PVR\t\t: 0x%x\n", pvid); |
149 | seq_printf(m, "SVR\t\t: 0x%x\n", svid); | |
150 | ||
151 | /* Display cpu Pll setting */ | |
152 | phid1 = mfspr(SPRN_HID1); | |
153 | seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); | |
63dafe57 BB |
154 | } |
155 | ||
905e75c4 | 156 | machine_arch_initcall(mpc85xx_ads, mpc85xx_common_publish_devices); |
8abc8f5f | 157 | |
72d2c3e0 KG |
158 | /* |
159 | * Called very early, device-tree isn't unflattened | |
160 | */ | |
161 | static int __init mpc85xx_ads_probe(void) | |
63dafe57 | 162 | { |
6936c625 KG |
163 | unsigned long root = of_get_flat_dt_root(); |
164 | ||
165 | return of_flat_dt_is_compatible(root, "MPC85xxADS"); | |
63dafe57 | 166 | } |
72d2c3e0 KG |
167 | |
168 | define_machine(mpc85xx_ads) { | |
169 | .name = "MPC85xx ADS", | |
170 | .probe = mpc85xx_ads_probe, | |
171 | .setup_arch = mpc85xx_ads_setup_arch, | |
172 | .init_IRQ = mpc85xx_ads_pic_init, | |
173 | .show_cpuinfo = mpc85xx_ads_show_cpuinfo, | |
174 | .get_irq = mpic_get_irq, | |
e1c1575f | 175 | .restart = fsl_rstcr_restart, |
72d2c3e0 KG |
176 | .calibrate_decr = generic_calibrate_decr, |
177 | .progress = udbg_progress, | |
178 | }; |