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[deliverable/linux.git] / arch / powerpc / platforms / 85xx / mpc85xx_ds.c
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d93daf84 1/*
7f50382d 2 * MPC85xx DS Board Setup
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3 *
4 * Author Xianghua Xiao (x.xiao@freescale.com)
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5 * Roy Zang <tie-fei.zang@freescale.com>
6 * - Add PCI/PCI Exprees support
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7 * Copyright 2007 Freescale Semiconductor Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/stddef.h>
16#include <linux/kernel.h>
f16dab98 17#include <linux/pci.h>
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18#include <linux/kdev_t.h>
19#include <linux/delay.h>
20#include <linux/seq_file.h>
f16dab98 21#include <linux/interrupt.h>
1028d4f1 22#include <linux/of_platform.h>
d93daf84 23
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24#include <asm/time.h>
25#include <asm/machdep.h>
f16dab98 26#include <asm/pci-bridge.h>
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27#include <mm/mmu_decl.h>
28#include <asm/prom.h>
29#include <asm/udbg.h>
30#include <asm/mpic.h>
31#include <asm/i8259.h>
152d0182 32#include <asm/swiotlb.h>
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33
34#include <sysdev/fsl_soc.h>
f16dab98 35#include <sysdev/fsl_pci.h>
582d3e09 36#include "smp.h"
d93daf84 37
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38#include "mpc85xx.h"
39
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40#undef DEBUG
41
42#ifdef DEBUG
e48b1b45 43#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
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44#else
45#define DBG(fmt, args...)
46#endif
47
f16dab98 48#ifdef CONFIG_PPC_I8259
bd0b9ac4 49static void mpc85xx_8259_cascade(struct irq_desc *desc)
f16dab98 50{
ec775d0e 51 struct irq_chip *chip = irq_desc_get_chip(desc);
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52 unsigned int cascade_irq = i8259_irq();
53
54 if (cascade_irq != NO_IRQ) {
55 generic_handle_irq(cascade_irq);
56 }
712d5d79 57 chip->irq_eoi(&desc->irq_data);
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58}
59#endif /* CONFIG_PPC_I8259 */
d93daf84 60
7f50382d 61void __init mpc85xx_ds_pic_init(void)
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62{
63 struct mpic *mpic;
d93daf84 64#ifdef CONFIG_PPC_I8259
996983b7 65 struct device_node *np;
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66 struct device_node *cascade_node = NULL;
67 int cascade_irq;
68#endif
06be64a3 69 unsigned long root = of_get_flat_dt_root();
d93daf84 70
06be64a3 71 if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
996983b7 72 mpic = mpic_alloc(NULL, 0,
e55d7f73 73 MPIC_NO_RESET |
5019609f 74 MPIC_BIG_ENDIAN |
a63e23b9 75 MPIC_SINGLE_DEST_CPU,
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76 0, 256, " OpenPIC ");
77 } else {
996983b7 78 mpic = mpic_alloc(NULL, 0,
5019609f 79 MPIC_BIG_ENDIAN |
3c10c9c4 80 MPIC_SINGLE_DEST_CPU,
b533f8ae 81 0, 256, " OpenPIC ");
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82 }
83
d93daf84 84 BUG_ON(mpic == NULL);
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85 mpic_init(mpic);
86
87#ifdef CONFIG_PPC_I8259
88 /* Initialize the i8259 controller */
89 for_each_node_by_type(np, "interrupt-controller")
55b61fec 90 if (of_device_is_compatible(np, "chrp,iic")) {
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91 cascade_node = np;
92 break;
93 }
94
95 if (cascade_node == NULL) {
96 printk(KERN_DEBUG "Could not find i8259 PIC\n");
97 return;
98 }
99
100 cascade_irq = irq_of_parse_and_map(cascade_node, 0);
101 if (cascade_irq == NO_IRQ) {
102 printk(KERN_ERR "Failed to map cascade interrupt\n");
103 return;
104 }
105
7f50382d 106 DBG("mpc85xxds: cascade mapped to irq %d\n", cascade_irq);
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107
108 i8259_init(cascade_node, 0);
109 of_node_put(cascade_node);
110
ec775d0e 111 irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade);
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112#endif /* CONFIG_PPC_I8259 */
113}
114
f16dab98 115#ifdef CONFIG_PCI
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116extern int uli_exclude_device(struct pci_controller *hose,
117 u_char bus, u_char devfn);
f16dab98 118
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119static struct device_node *pci_with_uli;
120
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121static int mpc85xx_exclude_device(struct pci_controller *hose,
122 u_char bus, u_char devfn)
f16dab98 123{
91a6f347 124 if (hose->dn == pci_with_uli)
b66510cb 125 return uli_exclude_device(hose, bus, devfn);
f16dab98 126
b66510cb 127 return PCIBIOS_SUCCESSFUL;
f16dab98 128}
f16dab98 129#endif /* CONFIG_PCI */
d93daf84 130
905e75c4 131static void __init mpc85xx_ds_uli_init(void)
d93daf84 132{
f16dab98 133#ifdef CONFIG_PCI
91a6f347 134 struct device_node *node;
f16dab98 135
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136 /* See if we have a ULI under the primary */
137
138 node = of_find_node_by_name(NULL, "uli1575");
139 while ((pci_with_uli = of_get_parent(node))) {
140 of_node_put(node);
141 node = pci_with_uli;
142
143 if (pci_with_uli == fsl_pci_primary) {
144 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
145 break;
c9438aff 146 }
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147 }
148#endif
91a6f347 149}
f16dab98 150
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151/*
152 * Setup the architecture
153 */
154static void __init mpc85xx_ds_setup_arch(void)
155{
156 if (ppc_md.progress)
157 ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
8bd3947a 158
688ba1db 159 swiotlb_detect_4g();
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160 fsl_pci_assign_primary();
161 mpc85xx_ds_uli_init();
91a6f347 162 mpc85xx_smp_init();
152d0182 163
7f50382d 164 printk("MPC85xx DS board from Freescale Semiconductor\n");
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165}
166
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167/*
168 * Called very early, device-tree isn't unflattened
169 */
170static int __init mpc8544_ds_probe(void)
171{
172 unsigned long root = of_get_flat_dt_root();
173
91a6f347 174 return !!of_flat_dt_is_compatible(root, "MPC8544DS");
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175}
176
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177machine_arch_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
178machine_arch_initcall(mpc8572_ds, mpc85xx_common_publish_devices);
179machine_arch_initcall(p2020_ds, mpc85xx_common_publish_devices);
1028d4f1 180
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181machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
182machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
183machine_arch_initcall(p2020_ds, swiotlb_setup_bus_notifier);
184
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185/*
186 * Called very early, device-tree isn't unflattened
187 */
188static int __init mpc8572_ds_probe(void)
189{
190 unsigned long root = of_get_flat_dt_root();
191
91a6f347 192 return !!of_flat_dt_is_compatible(root, "fsl,MPC8572DS");
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193}
194
195/*
196 * Called very early, device-tree isn't unflattened
197 */
198static int __init p2020_ds_probe(void)
199{
200 unsigned long root = of_get_flat_dt_root();
201
91a6f347 202 return !!of_flat_dt_is_compatible(root, "fsl,P2020DS");
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203}
204
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205define_machine(mpc8544_ds) {
206 .name = "MPC8544 DS",
207 .probe = mpc8544_ds_probe,
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208 .setup_arch = mpc85xx_ds_setup_arch,
209 .init_IRQ = mpc85xx_ds_pic_init,
2af8569d 210#ifdef CONFIG_PCI
f16dab98 211 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
48b16180 212 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
2af8569d 213#endif
d93daf84 214 .get_irq = mpic_get_irq,
e1c1575f 215 .restart = fsl_rstcr_restart,
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216 .calibrate_decr = generic_calibrate_decr,
217 .progress = udbg_progress,
218};
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219
220define_machine(mpc8572_ds) {
221 .name = "MPC8572 DS",
222 .probe = mpc8572_ds_probe,
223 .setup_arch = mpc85xx_ds_setup_arch,
224 .init_IRQ = mpc85xx_ds_pic_init,
225#ifdef CONFIG_PCI
226 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
48b16180 227 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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228#endif
229 .get_irq = mpic_get_irq,
e1c1575f 230 .restart = fsl_rstcr_restart,
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231 .calibrate_decr = generic_calibrate_decr,
232 .progress = udbg_progress,
233};
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234
235define_machine(p2020_ds) {
236 .name = "P2020 DS",
237 .probe = p2020_ds_probe,
238 .setup_arch = mpc85xx_ds_setup_arch,
239 .init_IRQ = mpc85xx_ds_pic_init,
240#ifdef CONFIG_PCI
241 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
48b16180 242 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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243#endif
244 .get_irq = mpic_get_irq,
245 .restart = fsl_rstcr_restart,
246 .calibrate_decr = generic_calibrate_decr,
247 .progress = udbg_progress,
248};
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