[deliverable/linux.git] / arch / powerpc / platforms / 85xx / mpc85xx_ds.c

/*
 * MPC85xx DS Board Setup
 *
 * Author Xianghua Xiao (x.xiao@freescale.com)
 * Roy Zang <tie-fei.zang@freescale.com>
 * 	- Add PCI/PCI Exprees support
 * Copyright 2007 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/of_platform.h>
#include <linux/memblock.h>

#include <asm/system.h>
#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <asm/i8259.h>
#include <asm/swiotlb.h>

#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>

#include "mpc85xx.h"

#undef DEBUG

#ifdef DEBUG
#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
#else
#define DBG(fmt, args...)
#endif

#ifdef CONFIG_PPC_I8259
static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int cascade_irq = i8259_irq();

	if (cascade_irq != NO_IRQ) {
		generic_handle_irq(cascade_irq);
	}
	chip->irq_eoi(&desc->irq_data);
}
#endif	/* CONFIG_PPC_I8259 */

void __init mpc85xx_ds_pic_init(void)
{
	struct mpic *mpic;
	struct resource r;
	struct device_node *np;
#ifdef CONFIG_PPC_I8259
	struct device_node *cascade_node = NULL;
	int cascade_irq;
#endif
	unsigned long root = of_get_flat_dt_root();

	np = of_find_node_by_type(NULL, "open-pic");
	if (np == NULL) {
		printk(KERN_ERR "Could not find open-pic node\n");
		return;
	}

	if (of_address_to_resource(np, 0, &r)) {
		printk(KERN_ERR "Failed to map mpic register space\n");
		of_node_put(np);
		return;
	}

	if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
		mpic = mpic_alloc(np, r.start,
			MPIC_PRIMARY |
			MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
			MPIC_SINGLE_DEST_CPU,
			0, 256, " OpenPIC  ");
	} else {
		mpic = mpic_alloc(np, r.start,
			  MPIC_PRIMARY | MPIC_WANTS_RESET |
			  MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
			  MPIC_SINGLE_DEST_CPU,
			0, 256, " OpenPIC  ");
	}

	BUG_ON(mpic == NULL);
	of_node_put(np);

	mpic_init(mpic);

#ifdef CONFIG_PPC_I8259
	/* Initialize the i8259 controller */
	for_each_node_by_type(np, "interrupt-controller")
	    if (of_device_is_compatible(np, "chrp,iic")) {
		cascade_node = np;
		break;
	}

	if (cascade_node == NULL) {
		printk(KERN_DEBUG "Could not find i8259 PIC\n");
		return;
	}

	cascade_irq = irq_of_parse_and_map(cascade_node, 0);
	if (cascade_irq == NO_IRQ) {
		printk(KERN_ERR "Failed to map cascade interrupt\n");
		return;
	}

	DBG("mpc85xxds: cascade mapped to irq %d\n", cascade_irq);

	i8259_init(cascade_node, 0);
	of_node_put(cascade_node);

	irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade);
#endif	/* CONFIG_PPC_I8259 */
}

#ifdef CONFIG_PCI
static int primary_phb_addr;
extern int uli_exclude_device(struct pci_controller *hose,
				u_char bus, u_char devfn);

static int mpc85xx_exclude_device(struct pci_controller *hose,
				   u_char bus, u_char devfn)
{
	struct device_node* node;
	struct resource rsrc;

	node = hose->dn;
	of_address_to_resource(node, 0, &rsrc);

	if ((rsrc.start & 0xfffff) == primary_phb_addr) {
		return uli_exclude_device(hose, bus, devfn);
	}

	return PCIBIOS_SUCCESSFUL;
}
#endif	/* CONFIG_PCI */

/*
 * Setup the architecture
 */
#ifdef CONFIG_SMP
extern void __init mpc85xx_smp_init(void);
#endif
static void __init mpc85xx_ds_setup_arch(void)
{
#ifdef CONFIG_PCI
	struct device_node *np;
	struct pci_controller *hose;
#endif
	dma_addr_t max = 0xffffffff;

	if (ppc_md.progress)
		ppc_md.progress("mpc85xx_ds_setup_arch()", 0);

#ifdef CONFIG_PCI
	for_each_node_by_type(np, "pci") {
		if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
		    of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
		    of_device_is_compatible(np, "fsl,p2020-pcie")) {
			struct resource rsrc;
			of_address_to_resource(np, 0, &rsrc);
			if ((rsrc.start & 0xfffff) == primary_phb_addr)
				fsl_add_bridge(np, 1);
			else
				fsl_add_bridge(np, 0);

			hose = pci_find_hose_for_OF_device(np);
			max = min(max, hose->dma_window_base_cur +
					hose->dma_window_size);
		}
	}

	ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif

#ifdef CONFIG_SMP
	mpc85xx_smp_init();
#endif

#ifdef CONFIG_SWIOTLB
	if (memblock_end_of_DRAM() > max) {
		ppc_swiotlb_enable = 1;
		set_pci_dma_ops(&swiotlb_dma_ops);
		ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
	}
#endif

	printk("MPC85xx DS board from Freescale Semiconductor\n");
}

/*
 * Called very early, device-tree isn't unflattened
 */
static int __init mpc8544_ds_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	if (of_flat_dt_is_compatible(root, "MPC8544DS")) {
#ifdef CONFIG_PCI
		primary_phb_addr = 0xb000;
#endif
		return 1;
	}

	return 0;
}

static struct of_device_id __initdata mpc85xxds_ids[] = {
	{ .type = "soc", },
	{ .compatible = "soc", },
	{ .compatible = "simple-bus", },
	{ .compatible = "gianfar", },
	{},
};

static int __init mpc85xxds_publish_devices(void)
{
	return of_platform_bus_probe(NULL, mpc85xxds_ids, NULL);
}
machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices);
machine_device_initcall(p2020_ds, mpc85xxds_publish_devices);

machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
machine_arch_initcall(p2020_ds, swiotlb_setup_bus_notifier);

/*
 * Called very early, device-tree isn't unflattened
 */
static int __init mpc8572_ds_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS")) {
#ifdef CONFIG_PCI
		primary_phb_addr = 0x8000;
#endif
		return 1;
	}

	return 0;
}

/*
 * Called very early, device-tree isn't unflattened
 */
static int __init p2020_ds_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) {
#ifdef CONFIG_PCI
		primary_phb_addr = 0x9000;
#endif
		return 1;
	}

	return 0;
}

define_machine(mpc8544_ds) {
	.name			= "MPC8544 DS",
	.probe			= mpc8544_ds_probe,
	.setup_arch		= mpc85xx_ds_setup_arch,
	.init_IRQ		= mpc85xx_ds_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};

define_machine(mpc8572_ds) {
	.name			= "MPC8572 DS",
	.probe			= mpc8572_ds_probe,
	.setup_arch		= mpc85xx_ds_setup_arch,
	.init_IRQ		= mpc85xx_ds_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};

define_machine(p2020_ds) {
	.name			= "P2020 DS",
	.probe			= p2020_ds_probe,
	.setup_arch		= mpc85xx_ds_setup_arch,
	.init_IRQ		= mpc85xx_ds_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};
Commit	Line	Data
d93daf84	1	/*
7f50382d	2	* MPC85xx DS Board Setup
d93daf84 JL	3	*
d93daf84 JL	4	* Author Xianghua Xiao (x.xiao@freescale.com)
f16dab98 RZ	5	* Roy Zang <tie-fei.zang@freescale.com>
f16dab98 RZ	6	* - Add PCI/PCI Exprees support
d93daf84 JL	7	* Copyright 2007 Freescale Semiconductor Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*/
	14
	15	#include <linux/stddef.h>
	16	#include <linux/kernel.h>
f16dab98	17	#include <linux/pci.h>
d93daf84 JL	18	#include <linux/kdev_t.h>
	19	#include <linux/delay.h>
	20	#include <linux/seq_file.h>
f16dab98	21	#include <linux/interrupt.h>
1028d4f1	22	#include <linux/of_platform.h>
95f72d1e	23	#include <linux/memblock.h>
d93daf84 JL	24
	25	#include <asm/system.h>
	26	#include <asm/time.h>
	27	#include <asm/machdep.h>
f16dab98	28	#include <asm/pci-bridge.h>
d93daf84 JL	29	#include <mm/mmu_decl.h>
	30	#include <asm/prom.h>
	31	#include <asm/udbg.h>
	32	#include <asm/mpic.h>
	33	#include <asm/i8259.h>
152d0182	34	#include <asm/swiotlb.h>
d93daf84 JL	35
d93daf84 JL	36	#include <sysdev/fsl_soc.h>
f16dab98	37	#include <sysdev/fsl_pci.h>
d93daf84	38
543a07b1 DES	39	#include "mpc85xx.h"
543a07b1 DES	40
d93daf84 JL	41	#undef DEBUG
	42
	43	#ifdef DEBUG
e48b1b45	44	#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
d93daf84 JL	45	#else
	46	#define DBG(fmt, args...)
	47	#endif
	48
f16dab98	49	#ifdef CONFIG_PPC_I8259
7f50382d	50	static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
f16dab98	51	{
ec775d0e	52	struct irq_chip *chip = irq_desc_get_chip(desc);
f16dab98 RZ	53	unsigned int cascade_irq = i8259_irq();
	54
	55	if (cascade_irq != NO_IRQ) {
	56	generic_handle_irq(cascade_irq);
	57	}
712d5d79	58	chip->irq_eoi(&desc->irq_data);
f16dab98 RZ	59	}
f16dab98 RZ	60	#endif /* CONFIG_PPC_I8259 */
d93daf84	61
7f50382d	62	void __init mpc85xx_ds_pic_init(void)
d93daf84 JL	63	{
	64	struct mpic *mpic;
	65	struct resource r;
a712b65c	66	struct device_node *np;
d93daf84 JL	67	#ifdef CONFIG_PPC_I8259
	68	struct device_node *cascade_node = NULL;
	69	int cascade_irq;
	70	#endif
06be64a3	71	unsigned long root = of_get_flat_dt_root();
d93daf84	72
b93eeba4	73	np = of_find_node_by_type(NULL, "open-pic");
d93daf84 JL	74	if (np == NULL) {
	75	printk(KERN_ERR "Could not find open-pic node\n");
	76	return;
	77	}
	78
	79	if (of_address_to_resource(np, 0, &r)) {
	80	printk(KERN_ERR "Failed to map mpic register space\n");
	81	of_node_put(np);
	82	return;
	83	}
	84
06be64a3 HW	85	if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
	86	mpic = mpic_alloc(np, r.start,
	87	MPIC_PRIMARY \|
a63e23b9 FB	88	MPIC_BIG_ENDIAN \| MPIC_BROKEN_FRR_NIRQS \|
a63e23b9 FB	89	MPIC_SINGLE_DEST_CPU,
06be64a3 HW	90	0, 256, " OpenPIC ");
	91	} else {
	92	mpic = mpic_alloc(np, r.start,
741edc49	93	MPIC_PRIMARY \| MPIC_WANTS_RESET \|
3c10c9c4 KG	94	MPIC_BIG_ENDIAN \| MPIC_BROKEN_FRR_NIRQS \|
3c10c9c4 KG	95	MPIC_SINGLE_DEST_CPU,
b533f8ae	96	0, 256, " OpenPIC ");
06be64a3 HW	97	}
06be64a3 HW	98
d93daf84	99	BUG_ON(mpic == NULL);
a712b65c	100	of_node_put(np);
d93daf84	101
d93daf84 JL	102	mpic_init(mpic);
	103
	104	#ifdef CONFIG_PPC_I8259
	105	/* Initialize the i8259 controller */
	106	for_each_node_by_type(np, "interrupt-controller")
55b61fec	107	if (of_device_is_compatible(np, "chrp,iic")) {
d93daf84 JL	108	cascade_node = np;
	109	break;
	110	}
	111
	112	if (cascade_node == NULL) {
	113	printk(KERN_DEBUG "Could not find i8259 PIC\n");
	114	return;
	115	}
	116
	117	cascade_irq = irq_of_parse_and_map(cascade_node, 0);
	118	if (cascade_irq == NO_IRQ) {
	119	printk(KERN_ERR "Failed to map cascade interrupt\n");
	120	return;
	121	}
	122
7f50382d	123	DBG("mpc85xxds: cascade mapped to irq %d\n", cascade_irq);
d93daf84 JL	124
	125	i8259_init(cascade_node, 0);
	126	of_node_put(cascade_node);
	127
ec775d0e	128	irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade);
d93daf84 JL	129	#endif /* CONFIG_PPC_I8259 */
	130	}
	131
f16dab98	132	#ifdef CONFIG_PCI
7f50382d	133	static int primary_phb_addr;
b66510cb KG	134	extern int uli_exclude_device(struct pci_controller *hose,
b66510cb KG	135	u_char bus, u_char devfn);
f16dab98	136
b66510cb KG	137	static int mpc85xx_exclude_device(struct pci_controller *hose,
b66510cb KG	138	u_char bus, u_char devfn)
f16dab98	139	{
7f50382d	140	struct device_node* node;
b66510cb	141	struct resource rsrc;
f16dab98	142
44ef3390	143	node = hose->dn;
b66510cb	144	of_address_to_resource(node, 0, &rsrc);
f16dab98	145
7f50382d	146	if ((rsrc.start & 0xfffff) == primary_phb_addr) {
b66510cb KG	147	return uli_exclude_device(hose, bus, devfn);
b66510cb KG	148	}
f16dab98	149
b66510cb	150	return PCIBIOS_SUCCESSFUL;
f16dab98	151	}
f16dab98	152	#endif /* CONFIG_PCI */
d93daf84 JL	153
	154	/*
	155	* Setup the architecture
	156	*/
8bd3947a KG	157	#ifdef CONFIG_SMP
	158	extern void __init mpc85xx_smp_init(void);
	159	#endif
7f50382d	160	static void __init mpc85xx_ds_setup_arch(void)
d93daf84	161	{
f16dab98 RZ	162	#ifdef CONFIG_PCI
f16dab98 RZ	163	struct device_node *np;
152d0182	164	struct pci_controller *hose;
f16dab98	165	#endif
152d0182	166	dma_addr_t max = 0xffffffff;
f16dab98	167
d93daf84	168	if (ppc_md.progress)
7f50382d	169	ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
d93daf84	170
f16dab98	171	#ifdef CONFIG_PCI
c9438aff KG	172	for_each_node_by_type(np, "pci") {
c9438aff KG	173	if (of_device_is_compatible(np, "fsl,mpc8540-pci") \|\|
01af9507 KG	174	of_device_is_compatible(np, "fsl,mpc8548-pcie") \|\|
01af9507 KG	175	of_device_is_compatible(np, "fsl,p2020-pcie")) {
c9438aff KG	176	struct resource rsrc;
	177	of_address_to_resource(np, 0, &rsrc);
	178	if ((rsrc.start & 0xfffff) == primary_phb_addr)
	179	fsl_add_bridge(np, 1);
	180	else
	181	fsl_add_bridge(np, 0);
152d0182 KG	182
	183	hose = pci_find_hose_for_OF_device(np);
	184	max = min(max, hose->dma_window_base_cur +
	185	hose->dma_window_size);
c9438aff	186	}
f16dab98	187	}
c9438aff	188
b66510cb	189	ppc_md.pci_exclude_device = mpc85xx_exclude_device;
f16dab98 RZ	190	#endif
f16dab98 RZ	191
8bd3947a KG	192	#ifdef CONFIG_SMP
	193	mpc85xx_smp_init();
	194	#endif
	195
152d0182	196	#ifdef CONFIG_SWIOTLB
95f72d1e	197	if (memblock_end_of_DRAM() > max) {
152d0182	198	ppc_swiotlb_enable = 1;
3702977f	199	set_pci_dma_ops(&swiotlb_dma_ops);
762afb73	200	ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
152d0182 KG	201	}
	202	#endif
	203
7f50382d	204	printk("MPC85xx DS board from Freescale Semiconductor\n");
d93daf84 JL	205	}
d93daf84 JL	206
d93daf84 JL	207	/*
	208	* Called very early, device-tree isn't unflattened
	209	*/
	210	static int __init mpc8544_ds_probe(void)
	211	{
	212	unsigned long root = of_get_flat_dt_root();
	213
7f50382d KG	214	if (of_flat_dt_is_compatible(root, "MPC8544DS")) {
	215	#ifdef CONFIG_PCI
	216	primary_phb_addr = 0xb000;
	217	#endif
	218	return 1;
7f50382d	219	}
01af9507 KG	220
01af9507 KG	221	return 0;
d93daf84 JL	222	}
d93daf84 JL	223
a712b65c	224	static struct of_device_id __initdata mpc85xxds_ids[] = {
1028d4f1 SS	225	{ .type = "soc", },
1028d4f1 SS	226	{ .compatible = "soc", },
cf0d19fb	227	{ .compatible = "simple-bus", },
84ba4a58	228	{ .compatible = "gianfar", },
1028d4f1 SS	229	{},
	230	};
	231
	232	static int __init mpc85xxds_publish_devices(void)
	233	{
	234	return of_platform_bus_probe(NULL, mpc85xxds_ids, NULL);
	235	}
	236	machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
741edc49	237	machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices);
01af9507	238	machine_device_initcall(p2020_ds, mpc85xxds_publish_devices);
1028d4f1	239
152d0182 KG	240	machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
	241	machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
	242	machine_arch_initcall(p2020_ds, swiotlb_setup_bus_notifier);
	243
5d54ddcb KG	244	/*
	245	* Called very early, device-tree isn't unflattened
	246	*/
	247	static int __init mpc8572_ds_probe(void)
	248	{
	249	unsigned long root = of_get_flat_dt_root();
	250
	251	if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS")) {
	252	#ifdef CONFIG_PCI
	253	primary_phb_addr = 0x8000;
	254	#endif
	255	return 1;
5d54ddcb	256	}
01af9507 KG	257
	258	return 0;
	259	}
	260
	261	/*
	262	* Called very early, device-tree isn't unflattened
	263	*/
	264	static int __init p2020_ds_probe(void)
	265	{
	266	unsigned long root = of_get_flat_dt_root();
	267
	268	if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) {
	269	#ifdef CONFIG_PCI
	270	primary_phb_addr = 0x9000;
	271	#endif
	272	return 1;
	273	}
	274
	275	return 0;
5d54ddcb KG	276	}
5d54ddcb KG	277
d93daf84 JL	278	define_machine(mpc8544_ds) {
	279	.name = "MPC8544 DS",
	280	.probe = mpc8544_ds_probe,
7f50382d KG	281	.setup_arch = mpc85xx_ds_setup_arch,
7f50382d KG	282	.init_IRQ = mpc85xx_ds_pic_init,
2af8569d	283	#ifdef CONFIG_PCI
f16dab98	284	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
2af8569d	285	#endif
d93daf84	286	.get_irq = mpic_get_irq,
e1c1575f	287	.restart = fsl_rstcr_restart,
d93daf84 JL	288	.calibrate_decr = generic_calibrate_decr,
	289	.progress = udbg_progress,
	290	};
5d54ddcb KG	291
	292	define_machine(mpc8572_ds) {
	293	.name = "MPC8572 DS",
	294	.probe = mpc8572_ds_probe,
	295	.setup_arch = mpc85xx_ds_setup_arch,
	296	.init_IRQ = mpc85xx_ds_pic_init,
	297	#ifdef CONFIG_PCI
	298	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	299	#endif
	300	.get_irq = mpic_get_irq,
e1c1575f	301	.restart = fsl_rstcr_restart,
5d54ddcb KG	302	.calibrate_decr = generic_calibrate_decr,
	303	.progress = udbg_progress,
	304	};
01af9507 KG	305
	306	define_machine(p2020_ds) {
	307	.name = "P2020 DS",
	308	.probe = p2020_ds_probe,
	309	.setup_arch = mpc85xx_ds_setup_arch,
	310	.init_IRQ = mpc85xx_ds_pic_init,
	311	#ifdef CONFIG_PCI
	312	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	313	#endif
	314	.get_irq = mpic_get_irq,
	315	.restart = fsl_rstcr_restart,
	316	.calibrate_decr = generic_calibrate_decr,
	317	.progress = udbg_progress,
	318	};