Commit | Line | Data |
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d93daf84 | 1 | /* |
7f50382d | 2 | * MPC85xx DS Board Setup |
d93daf84 JL |
3 | * |
4 | * Author Xianghua Xiao (x.xiao@freescale.com) | |
f16dab98 RZ |
5 | * Roy Zang <tie-fei.zang@freescale.com> |
6 | * - Add PCI/PCI Exprees support | |
d93daf84 JL |
7 | * Copyright 2007 Freescale Semiconductor Inc. |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/stddef.h> | |
16 | #include <linux/kernel.h> | |
f16dab98 | 17 | #include <linux/pci.h> |
d93daf84 JL |
18 | #include <linux/kdev_t.h> |
19 | #include <linux/delay.h> | |
20 | #include <linux/seq_file.h> | |
f16dab98 | 21 | #include <linux/interrupt.h> |
1028d4f1 | 22 | #include <linux/of_platform.h> |
95f72d1e | 23 | #include <linux/memblock.h> |
d93daf84 JL |
24 | |
25 | #include <asm/system.h> | |
26 | #include <asm/time.h> | |
27 | #include <asm/machdep.h> | |
f16dab98 | 28 | #include <asm/pci-bridge.h> |
d93daf84 JL |
29 | #include <mm/mmu_decl.h> |
30 | #include <asm/prom.h> | |
31 | #include <asm/udbg.h> | |
32 | #include <asm/mpic.h> | |
33 | #include <asm/i8259.h> | |
152d0182 | 34 | #include <asm/swiotlb.h> |
d93daf84 JL |
35 | |
36 | #include <sysdev/fsl_soc.h> | |
f16dab98 | 37 | #include <sysdev/fsl_pci.h> |
d93daf84 JL |
38 | |
39 | #undef DEBUG | |
40 | ||
41 | #ifdef DEBUG | |
e48b1b45 | 42 | #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) |
d93daf84 JL |
43 | #else |
44 | #define DBG(fmt, args...) | |
45 | #endif | |
46 | ||
f16dab98 | 47 | #ifdef CONFIG_PPC_I8259 |
7f50382d | 48 | static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) |
f16dab98 RZ |
49 | { |
50 | unsigned int cascade_irq = i8259_irq(); | |
51 | ||
52 | if (cascade_irq != NO_IRQ) { | |
53 | generic_handle_irq(cascade_irq); | |
54 | } | |
55 | desc->chip->eoi(irq); | |
56 | } | |
57 | #endif /* CONFIG_PPC_I8259 */ | |
d93daf84 | 58 | |
7f50382d | 59 | void __init mpc85xx_ds_pic_init(void) |
d93daf84 JL |
60 | { |
61 | struct mpic *mpic; | |
62 | struct resource r; | |
a712b65c | 63 | struct device_node *np; |
d93daf84 JL |
64 | #ifdef CONFIG_PPC_I8259 |
65 | struct device_node *cascade_node = NULL; | |
66 | int cascade_irq; | |
67 | #endif | |
06be64a3 | 68 | unsigned long root = of_get_flat_dt_root(); |
d93daf84 | 69 | |
b93eeba4 | 70 | np = of_find_node_by_type(NULL, "open-pic"); |
d93daf84 JL |
71 | if (np == NULL) { |
72 | printk(KERN_ERR "Could not find open-pic node\n"); | |
73 | return; | |
74 | } | |
75 | ||
76 | if (of_address_to_resource(np, 0, &r)) { | |
77 | printk(KERN_ERR "Failed to map mpic register space\n"); | |
78 | of_node_put(np); | |
79 | return; | |
80 | } | |
81 | ||
06be64a3 HW |
82 | if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) { |
83 | mpic = mpic_alloc(np, r.start, | |
84 | MPIC_PRIMARY | | |
85 | MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, | |
86 | 0, 256, " OpenPIC "); | |
87 | } else { | |
88 | mpic = mpic_alloc(np, r.start, | |
741edc49 | 89 | MPIC_PRIMARY | MPIC_WANTS_RESET | |
3c10c9c4 KG |
90 | MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | |
91 | MPIC_SINGLE_DEST_CPU, | |
b533f8ae | 92 | 0, 256, " OpenPIC "); |
06be64a3 HW |
93 | } |
94 | ||
d93daf84 | 95 | BUG_ON(mpic == NULL); |
a712b65c | 96 | of_node_put(np); |
d93daf84 | 97 | |
d93daf84 JL |
98 | mpic_init(mpic); |
99 | ||
100 | #ifdef CONFIG_PPC_I8259 | |
101 | /* Initialize the i8259 controller */ | |
102 | for_each_node_by_type(np, "interrupt-controller") | |
55b61fec | 103 | if (of_device_is_compatible(np, "chrp,iic")) { |
d93daf84 JL |
104 | cascade_node = np; |
105 | break; | |
106 | } | |
107 | ||
108 | if (cascade_node == NULL) { | |
109 | printk(KERN_DEBUG "Could not find i8259 PIC\n"); | |
110 | return; | |
111 | } | |
112 | ||
113 | cascade_irq = irq_of_parse_and_map(cascade_node, 0); | |
114 | if (cascade_irq == NO_IRQ) { | |
115 | printk(KERN_ERR "Failed to map cascade interrupt\n"); | |
116 | return; | |
117 | } | |
118 | ||
7f50382d | 119 | DBG("mpc85xxds: cascade mapped to irq %d\n", cascade_irq); |
d93daf84 JL |
120 | |
121 | i8259_init(cascade_node, 0); | |
122 | of_node_put(cascade_node); | |
123 | ||
7f50382d | 124 | set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade); |
d93daf84 JL |
125 | #endif /* CONFIG_PPC_I8259 */ |
126 | } | |
127 | ||
f16dab98 | 128 | #ifdef CONFIG_PCI |
7f50382d | 129 | static int primary_phb_addr; |
b66510cb KG |
130 | extern int uli_exclude_device(struct pci_controller *hose, |
131 | u_char bus, u_char devfn); | |
f16dab98 | 132 | |
b66510cb KG |
133 | static int mpc85xx_exclude_device(struct pci_controller *hose, |
134 | u_char bus, u_char devfn) | |
f16dab98 | 135 | { |
7f50382d | 136 | struct device_node* node; |
b66510cb | 137 | struct resource rsrc; |
f16dab98 | 138 | |
44ef3390 | 139 | node = hose->dn; |
b66510cb | 140 | of_address_to_resource(node, 0, &rsrc); |
f16dab98 | 141 | |
7f50382d | 142 | if ((rsrc.start & 0xfffff) == primary_phb_addr) { |
b66510cb KG |
143 | return uli_exclude_device(hose, bus, devfn); |
144 | } | |
f16dab98 | 145 | |
b66510cb | 146 | return PCIBIOS_SUCCESSFUL; |
f16dab98 | 147 | } |
f16dab98 | 148 | #endif /* CONFIG_PCI */ |
d93daf84 JL |
149 | |
150 | /* | |
151 | * Setup the architecture | |
152 | */ | |
8bd3947a KG |
153 | #ifdef CONFIG_SMP |
154 | extern void __init mpc85xx_smp_init(void); | |
155 | #endif | |
7f50382d | 156 | static void __init mpc85xx_ds_setup_arch(void) |
d93daf84 | 157 | { |
f16dab98 RZ |
158 | #ifdef CONFIG_PCI |
159 | struct device_node *np; | |
152d0182 | 160 | struct pci_controller *hose; |
f16dab98 | 161 | #endif |
152d0182 | 162 | dma_addr_t max = 0xffffffff; |
f16dab98 | 163 | |
d93daf84 | 164 | if (ppc_md.progress) |
7f50382d | 165 | ppc_md.progress("mpc85xx_ds_setup_arch()", 0); |
d93daf84 | 166 | |
f16dab98 | 167 | #ifdef CONFIG_PCI |
c9438aff KG |
168 | for_each_node_by_type(np, "pci") { |
169 | if (of_device_is_compatible(np, "fsl,mpc8540-pci") || | |
01af9507 KG |
170 | of_device_is_compatible(np, "fsl,mpc8548-pcie") || |
171 | of_device_is_compatible(np, "fsl,p2020-pcie")) { | |
c9438aff KG |
172 | struct resource rsrc; |
173 | of_address_to_resource(np, 0, &rsrc); | |
174 | if ((rsrc.start & 0xfffff) == primary_phb_addr) | |
175 | fsl_add_bridge(np, 1); | |
176 | else | |
177 | fsl_add_bridge(np, 0); | |
152d0182 KG |
178 | |
179 | hose = pci_find_hose_for_OF_device(np); | |
180 | max = min(max, hose->dma_window_base_cur + | |
181 | hose->dma_window_size); | |
c9438aff | 182 | } |
f16dab98 | 183 | } |
c9438aff | 184 | |
b66510cb | 185 | ppc_md.pci_exclude_device = mpc85xx_exclude_device; |
f16dab98 RZ |
186 | #endif |
187 | ||
8bd3947a KG |
188 | #ifdef CONFIG_SMP |
189 | mpc85xx_smp_init(); | |
190 | #endif | |
191 | ||
152d0182 | 192 | #ifdef CONFIG_SWIOTLB |
95f72d1e | 193 | if (memblock_end_of_DRAM() > max) { |
152d0182 | 194 | ppc_swiotlb_enable = 1; |
3702977f | 195 | set_pci_dma_ops(&swiotlb_dma_ops); |
762afb73 | 196 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb; |
152d0182 KG |
197 | } |
198 | #endif | |
199 | ||
7f50382d | 200 | printk("MPC85xx DS board from Freescale Semiconductor\n"); |
d93daf84 JL |
201 | } |
202 | ||
d93daf84 JL |
203 | /* |
204 | * Called very early, device-tree isn't unflattened | |
205 | */ | |
206 | static int __init mpc8544_ds_probe(void) | |
207 | { | |
208 | unsigned long root = of_get_flat_dt_root(); | |
209 | ||
7f50382d KG |
210 | if (of_flat_dt_is_compatible(root, "MPC8544DS")) { |
211 | #ifdef CONFIG_PCI | |
212 | primary_phb_addr = 0xb000; | |
213 | #endif | |
214 | return 1; | |
7f50382d | 215 | } |
01af9507 KG |
216 | |
217 | return 0; | |
d93daf84 JL |
218 | } |
219 | ||
a712b65c | 220 | static struct of_device_id __initdata mpc85xxds_ids[] = { |
1028d4f1 SS |
221 | { .type = "soc", }, |
222 | { .compatible = "soc", }, | |
cf0d19fb | 223 | { .compatible = "simple-bus", }, |
84ba4a58 | 224 | { .compatible = "gianfar", }, |
1028d4f1 SS |
225 | {}, |
226 | }; | |
227 | ||
228 | static int __init mpc85xxds_publish_devices(void) | |
229 | { | |
230 | return of_platform_bus_probe(NULL, mpc85xxds_ids, NULL); | |
231 | } | |
232 | machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices); | |
741edc49 | 233 | machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices); |
01af9507 | 234 | machine_device_initcall(p2020_ds, mpc85xxds_publish_devices); |
1028d4f1 | 235 | |
152d0182 KG |
236 | machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier); |
237 | machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier); | |
238 | machine_arch_initcall(p2020_ds, swiotlb_setup_bus_notifier); | |
239 | ||
5d54ddcb KG |
240 | /* |
241 | * Called very early, device-tree isn't unflattened | |
242 | */ | |
243 | static int __init mpc8572_ds_probe(void) | |
244 | { | |
245 | unsigned long root = of_get_flat_dt_root(); | |
246 | ||
247 | if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS")) { | |
248 | #ifdef CONFIG_PCI | |
249 | primary_phb_addr = 0x8000; | |
250 | #endif | |
251 | return 1; | |
5d54ddcb | 252 | } |
01af9507 KG |
253 | |
254 | return 0; | |
255 | } | |
256 | ||
257 | /* | |
258 | * Called very early, device-tree isn't unflattened | |
259 | */ | |
260 | static int __init p2020_ds_probe(void) | |
261 | { | |
262 | unsigned long root = of_get_flat_dt_root(); | |
263 | ||
264 | if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) { | |
265 | #ifdef CONFIG_PCI | |
266 | primary_phb_addr = 0x9000; | |
267 | #endif | |
268 | return 1; | |
269 | } | |
270 | ||
271 | return 0; | |
5d54ddcb KG |
272 | } |
273 | ||
d93daf84 JL |
274 | define_machine(mpc8544_ds) { |
275 | .name = "MPC8544 DS", | |
276 | .probe = mpc8544_ds_probe, | |
7f50382d KG |
277 | .setup_arch = mpc85xx_ds_setup_arch, |
278 | .init_IRQ = mpc85xx_ds_pic_init, | |
2af8569d | 279 | #ifdef CONFIG_PCI |
f16dab98 | 280 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
2af8569d | 281 | #endif |
d93daf84 | 282 | .get_irq = mpic_get_irq, |
e1c1575f | 283 | .restart = fsl_rstcr_restart, |
d93daf84 JL |
284 | .calibrate_decr = generic_calibrate_decr, |
285 | .progress = udbg_progress, | |
286 | }; | |
5d54ddcb KG |
287 | |
288 | define_machine(mpc8572_ds) { | |
289 | .name = "MPC8572 DS", | |
290 | .probe = mpc8572_ds_probe, | |
291 | .setup_arch = mpc85xx_ds_setup_arch, | |
292 | .init_IRQ = mpc85xx_ds_pic_init, | |
293 | #ifdef CONFIG_PCI | |
294 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | |
295 | #endif | |
296 | .get_irq = mpic_get_irq, | |
e1c1575f | 297 | .restart = fsl_rstcr_restart, |
5d54ddcb KG |
298 | .calibrate_decr = generic_calibrate_decr, |
299 | .progress = udbg_progress, | |
300 | }; | |
01af9507 KG |
301 | |
302 | define_machine(p2020_ds) { | |
303 | .name = "P2020 DS", | |
304 | .probe = p2020_ds_probe, | |
305 | .setup_arch = mpc85xx_ds_setup_arch, | |
306 | .init_IRQ = mpc85xx_ds_pic_init, | |
307 | #ifdef CONFIG_PCI | |
308 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | |
309 | #endif | |
310 | .get_irq = mpic_get_irq, | |
311 | .restart = fsl_rstcr_restart, | |
312 | .calibrate_decr = generic_calibrate_decr, | |
313 | .progress = udbg_progress, | |
314 | }; |