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c2882bb1 AF |
1 | /* |
2 | * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved. | |
3 | * | |
4 | * Author: Andy Fleming <afleming@freescale.com> | |
5 | * | |
6 | * Based on 83xx/mpc8360e_pb.c by: | |
7 | * Li Yang <LeoLi@freescale.com> | |
8 | * Yin Olivia <Hong-hua.Yin@freescale.com> | |
9 | * | |
10 | * Description: | |
23f510bc | 11 | * MPC85xx MDS board specific routines. |
c2882bb1 AF |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | ||
19 | #include <linux/stddef.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/reboot.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/kdev_t.h> | |
26 | #include <linux/major.h> | |
27 | #include <linux/console.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/seq_file.h> | |
c2882bb1 AF |
30 | #include <linux/initrd.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/fsl_devices.h> | |
882407b9 JL |
33 | #include <linux/of_platform.h> |
34 | #include <linux/of_device.h> | |
94833a42 | 35 | #include <linux/phy.h> |
c2882bb1 | 36 | |
c2882bb1 AF |
37 | #include <asm/system.h> |
38 | #include <asm/atomic.h> | |
39 | #include <asm/time.h> | |
40 | #include <asm/io.h> | |
41 | #include <asm/machdep.h> | |
c2882bb1 | 42 | #include <asm/pci-bridge.h> |
c2882bb1 AF |
43 | #include <asm/irq.h> |
44 | #include <mm/mmu_decl.h> | |
45 | #include <asm/prom.h> | |
46 | #include <asm/udbg.h> | |
47 | #include <sysdev/fsl_soc.h> | |
3f6c5dae | 48 | #include <sysdev/fsl_pci.h> |
c2882bb1 AF |
49 | #include <asm/qe.h> |
50 | #include <asm/qe_ic.h> | |
51 | #include <asm/mpic.h> | |
52 | ||
c2882bb1 AF |
53 | #undef DEBUG |
54 | #ifdef DEBUG | |
55 | #define DBG(fmt...) udbg_printf(fmt) | |
56 | #else | |
57 | #define DBG(fmt...) | |
58 | #endif | |
59 | ||
94833a42 AF |
60 | #define MV88E1111_SCR 0x10 |
61 | #define MV88E1111_SCR_125CLK 0x0010 | |
62 | static int mpc8568_fixup_125_clock(struct phy_device *phydev) | |
63 | { | |
64 | int scr; | |
65 | int err; | |
66 | ||
67 | /* Workaround for the 125 CLK Toggle */ | |
68 | scr = phy_read(phydev, MV88E1111_SCR); | |
69 | ||
70 | if (scr < 0) | |
71 | return scr; | |
72 | ||
73 | err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK)); | |
74 | ||
75 | if (err) | |
76 | return err; | |
77 | ||
78 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); | |
79 | ||
80 | if (err) | |
81 | return err; | |
82 | ||
83 | scr = phy_read(phydev, MV88E1111_SCR); | |
84 | ||
85 | if (scr < 0) | |
86 | return err; | |
87 | ||
88 | err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008); | |
89 | ||
90 | return err; | |
91 | } | |
92 | ||
93 | static int mpc8568_mds_phy_fixups(struct phy_device *phydev) | |
94 | { | |
95 | int temp; | |
96 | int err; | |
97 | ||
98 | /* Errata */ | |
99 | err = phy_write(phydev,29, 0x0006); | |
100 | ||
101 | if (err) | |
102 | return err; | |
103 | ||
104 | temp = phy_read(phydev, 30); | |
105 | ||
106 | if (temp < 0) | |
107 | return temp; | |
108 | ||
109 | temp = (temp & (~0x8000)) | 0x4000; | |
110 | err = phy_write(phydev,30, temp); | |
111 | ||
112 | if (err) | |
113 | return err; | |
114 | ||
115 | err = phy_write(phydev,29, 0x000a); | |
116 | ||
117 | if (err) | |
118 | return err; | |
119 | ||
120 | temp = phy_read(phydev, 30); | |
121 | ||
122 | if (temp < 0) | |
123 | return temp; | |
124 | ||
125 | temp = phy_read(phydev, 30); | |
126 | ||
127 | if (temp < 0) | |
128 | return temp; | |
129 | ||
130 | temp &= ~0x0020; | |
131 | ||
132 | err = phy_write(phydev,30,temp); | |
133 | ||
134 | if (err) | |
135 | return err; | |
136 | ||
137 | /* Disable automatic MDI/MDIX selection */ | |
138 | temp = phy_read(phydev, 16); | |
139 | ||
140 | if (temp < 0) | |
141 | return temp; | |
142 | ||
143 | temp &= ~0x0060; | |
144 | err = phy_write(phydev,16,temp); | |
145 | ||
146 | return err; | |
147 | } | |
148 | ||
c2882bb1 AF |
149 | /* ************************************************************************ |
150 | * | |
151 | * Setup the architecture | |
152 | * | |
153 | */ | |
23f510bc | 154 | static void __init mpc85xx_mds_setup_arch(void) |
c2882bb1 AF |
155 | { |
156 | struct device_node *np; | |
73f5b8f9 | 157 | static u8 __iomem *bcsr_regs = NULL; |
c2882bb1 | 158 | |
c2882bb1 | 159 | if (ppc_md.progress) |
23f510bc | 160 | ppc_md.progress("mpc85xx_mds_setup_arch()", 0); |
c2882bb1 | 161 | |
c2882bb1 AF |
162 | /* Map BCSR area */ |
163 | np = of_find_node_by_name(NULL, "bcsr"); | |
164 | if (np != NULL) { | |
165 | struct resource res; | |
166 | ||
167 | of_address_to_resource(np, 0, &res); | |
168 | bcsr_regs = ioremap(res.start, res.end - res.start +1); | |
169 | of_node_put(np); | |
170 | } | |
171 | ||
172 | #ifdef CONFIG_PCI | |
c9438aff KG |
173 | for_each_node_by_type(np, "pci") { |
174 | if (of_device_is_compatible(np, "fsl,mpc8540-pci") || | |
175 | of_device_is_compatible(np, "fsl,mpc8548-pcie")) { | |
176 | struct resource rsrc; | |
177 | of_address_to_resource(np, 0, &rsrc); | |
178 | if ((rsrc.start & 0xfffff) == 0x8000) | |
179 | fsl_add_bridge(np, 1); | |
180 | else | |
181 | fsl_add_bridge(np, 0); | |
182 | } | |
183 | } | |
c2882bb1 AF |
184 | #endif |
185 | ||
186 | #ifdef CONFIG_QUICC_ENGINE | |
a2dd70a1 AV |
187 | np = of_find_compatible_node(NULL, NULL, "fsl,qe"); |
188 | if (!np) { | |
189 | np = of_find_node_by_name(NULL, "qe"); | |
190 | if (!np) | |
191 | return; | |
c2882bb1 AF |
192 | } |
193 | ||
a2dd70a1 AV |
194 | qe_reset(); |
195 | of_node_put(np); | |
196 | ||
197 | np = of_find_node_by_name(NULL, "par_io"); | |
198 | if (np) { | |
199 | struct device_node *ucc; | |
c2882bb1 AF |
200 | |
201 | par_io_init(np); | |
202 | of_node_put(np); | |
203 | ||
a2dd70a1 | 204 | for_each_node_by_name(ucc, "ucc") |
c2882bb1 | 205 | par_io_of_config(ucc); |
c2882bb1 AF |
206 | } |
207 | ||
208 | if (bcsr_regs) { | |
803dedb6 AV |
209 | #define BCSR_UCC1_GETH_EN (0x1 << 7) |
210 | #define BCSR_UCC2_GETH_EN (0x1 << 7) | |
211 | #define BCSR_UCC1_MODE_MSK (0x3 << 4) | |
212 | #define BCSR_UCC2_MODE_MSK (0x3 << 0) | |
213 | ||
214 | /* Turn off UCC1 & UCC2 */ | |
215 | clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); | |
216 | clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); | |
217 | ||
218 | /* Mode is RGMII, all bits clear */ | |
219 | clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK | | |
220 | BCSR_UCC2_MODE_MSK); | |
221 | ||
222 | /* Turn UCC1 & UCC2 on */ | |
223 | setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); | |
224 | setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); | |
c2882bb1 AF |
225 | |
226 | iounmap(bcsr_regs); | |
227 | } | |
c2882bb1 AF |
228 | #endif /* CONFIG_QUICC_ENGINE */ |
229 | } | |
230 | ||
94833a42 AF |
231 | |
232 | static int __init board_fixups(void) | |
233 | { | |
aab0d375 | 234 | char phy_id[20]; |
94833a42 AF |
235 | char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"}; |
236 | struct device_node *mdio; | |
237 | struct resource res; | |
238 | int i; | |
239 | ||
240 | for (i = 0; i < ARRAY_SIZE(compstrs); i++) { | |
241 | mdio = of_find_compatible_node(NULL, NULL, compstrs[i]); | |
242 | ||
243 | of_address_to_resource(mdio, 0, &res); | |
aab0d375 | 244 | snprintf(phy_id, sizeof(phy_id), "%llx:%02x", |
24a99596 | 245 | (unsigned long long)res.start, 1); |
94833a42 AF |
246 | |
247 | phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock); | |
248 | phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups); | |
249 | ||
250 | /* Register a workaround for errata */ | |
aab0d375 | 251 | snprintf(phy_id, sizeof(phy_id), "%llx:%02x", |
24a99596 | 252 | (unsigned long long)res.start, 7); |
94833a42 AF |
253 | phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups); |
254 | ||
255 | of_node_put(mdio); | |
256 | } | |
257 | ||
258 | return 0; | |
259 | } | |
260 | machine_arch_initcall(mpc85xx_mds, board_fixups); | |
261 | ||
23f510bc | 262 | static struct of_device_id mpc85xx_ids[] = { |
c2882bb1 AF |
263 | { .type = "soc", }, |
264 | { .compatible = "soc", }, | |
cf0d19fb | 265 | { .compatible = "simple-bus", }, |
c2882bb1 | 266 | { .type = "qe", }, |
a2dd70a1 | 267 | { .compatible = "fsl,qe", }, |
c2882bb1 AF |
268 | {}, |
269 | }; | |
270 | ||
23f510bc | 271 | static int __init mpc85xx_publish_devices(void) |
c2882bb1 | 272 | { |
c2882bb1 | 273 | /* Publish the QE devices */ |
277982e2 | 274 | of_platform_bus_probe(NULL, mpc85xx_ids, NULL); |
c2882bb1 AF |
275 | |
276 | return 0; | |
277 | } | |
277982e2 | 278 | machine_device_initcall(mpc85xx_mds, mpc85xx_publish_devices); |
c2882bb1 | 279 | |
23f510bc | 280 | static void __init mpc85xx_mds_pic_init(void) |
c2882bb1 AF |
281 | { |
282 | struct mpic *mpic; | |
283 | struct resource r; | |
284 | struct device_node *np = NULL; | |
285 | ||
286 | np = of_find_node_by_type(NULL, "open-pic"); | |
287 | if (!np) | |
288 | return; | |
289 | ||
290 | if (of_address_to_resource(np, 0, &r)) { | |
291 | printk(KERN_ERR "Failed to map mpic register space\n"); | |
292 | of_node_put(np); | |
293 | return; | |
294 | } | |
295 | ||
296 | mpic = mpic_alloc(np, r.start, | |
297 | MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, | |
b533f8ae | 298 | 0, 256, " OpenPIC "); |
c2882bb1 AF |
299 | BUG_ON(mpic == NULL); |
300 | of_node_put(np); | |
301 | ||
c2882bb1 AF |
302 | mpic_init(mpic); |
303 | ||
c2882bb1 | 304 | #ifdef CONFIG_QUICC_ENGINE |
a2dd70a1 AV |
305 | np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); |
306 | if (!np) { | |
307 | np = of_find_node_by_type(NULL, "qeic"); | |
308 | if (!np) | |
309 | return; | |
310 | } | |
cccd2102 | 311 | qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); |
c2882bb1 AF |
312 | of_node_put(np); |
313 | #endif /* CONFIG_QUICC_ENGINE */ | |
314 | } | |
315 | ||
23f510bc | 316 | static int __init mpc85xx_mds_probe(void) |
c2882bb1 | 317 | { |
6936c625 | 318 | unsigned long root = of_get_flat_dt_root(); |
c2882bb1 | 319 | |
6936c625 | 320 | return of_flat_dt_is_compatible(root, "MPC85xxMDS"); |
c2882bb1 AF |
321 | } |
322 | ||
23f510bc | 323 | define_machine(mpc85xx_mds) { |
6936c625 | 324 | .name = "MPC85xx MDS", |
23f510bc KG |
325 | .probe = mpc85xx_mds_probe, |
326 | .setup_arch = mpc85xx_mds_setup_arch, | |
327 | .init_IRQ = mpc85xx_mds_pic_init, | |
c2882bb1 | 328 | .get_irq = mpic_get_irq, |
e1c1575f | 329 | .restart = fsl_rstcr_restart, |
c2882bb1 AF |
330 | .calibrate_decr = generic_calibrate_decr, |
331 | .progress = udbg_progress, | |
2af8569d | 332 | #ifdef CONFIG_PCI |
aa3c1121 | 333 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
2af8569d | 334 | #endif |
c2882bb1 | 335 | }; |