[deliverable/linux.git] / arch / powerpc / platforms / 85xx / mpc85xx_rdb.c

/*
 * MPC85xx RDB Board Setup
 *
 * Copyright 2009,2012 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/of_platform.h>

#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <asm/qe.h>
#include <asm/qe_ic.h>
#include <asm/fsl_guts.h>

#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include "smp.h"

#include "mpc85xx.h"

#undef DEBUG

#ifdef DEBUG
#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
#else
#define DBG(fmt, args...)
#endif


void __init mpc85xx_rdb_pic_init(void)
{
	struct mpic *mpic;
	unsigned long root = of_get_flat_dt_root();

#ifdef CONFIG_QUICC_ENGINE
	struct device_node *np;
#endif

	if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
		mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
			MPIC_BIG_ENDIAN |
			MPIC_SINGLE_DEST_CPU,
			0, 256, " OpenPIC  ");
	} else {
		mpic = mpic_alloc(NULL, 0,
		  MPIC_BIG_ENDIAN |
		  MPIC_SINGLE_DEST_CPU,
		  0, 256, " OpenPIC  ");
	}

	BUG_ON(mpic == NULL);
	mpic_init(mpic);

#ifdef CONFIG_QUICC_ENGINE
	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
	if (np) {
		qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
				qe_ic_cascade_high_mpic);
		of_node_put(np);

	} else
		pr_err("%s: Could not find qe-ic node\n", __func__);
#endif

}

/*
 * Setup the architecture
 */
static void __init mpc85xx_rdb_setup_arch(void)
{
#ifdef CONFIG_QUICC_ENGINE
	struct device_node *np;
#endif

	if (ppc_md.progress)
		ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);

	mpc85xx_smp_init();

	fsl_pci_assign_primary();

#ifdef CONFIG_QUICC_ENGINE
	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!np) {
		pr_err("%s: Could not find Quicc Engine node\n", __func__);
		goto qe_fail;
	}

	qe_reset();
	of_node_put(np);

	np = of_find_node_by_name(NULL, "par_io");
	if (np) {
		struct device_node *ucc;

		par_io_init(np);
		of_node_put(np);

		for_each_node_by_name(ucc, "ucc")
			par_io_of_config(ucc);

	}
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
	if (machine_is(p1025_rdb)) {

		struct ccsr_guts __iomem *guts;

		np = of_find_node_by_name(NULL, "global-utilities");
		if (np) {
			guts = of_iomap(np, 0);
			if (!guts) {

				pr_err("mpc85xx-rdb: could not map global utilities register\n");

			} else {
			/* P1025 has pins muxed for QE and other functions. To
			* enable QE UEC mode, we need to set bit QE0 for UCC1
			* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
			* and QE12 for QE MII management singals in PMUXCR
			* register.
			*/
				setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
						MPC85xx_PMUXCR_QE(3) |
						MPC85xx_PMUXCR_QE(9) |
						MPC85xx_PMUXCR_QE(12));
				iounmap(guts);
			}
			of_node_put(np);
		}

	}
#endif

qe_fail:
#endif	/* CONFIG_QUICC_ENGINE */

	printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
}

machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices);
machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices);
machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices);
machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices);

/*
 * Called very early, device-tree isn't unflattened
 */
static int __init p2020_rdb_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	if (of_flat_dt_is_compatible(root, "fsl,P2020RDB"))
		return 1;
	return 0;
}

static int __init p1020_rdb_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	if (of_flat_dt_is_compatible(root, "fsl,P1020RDB"))
		return 1;
	return 0;
}

static int __init p1020_rdb_pc_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PC");
}

static int __init p1021_rdb_pc_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	if (of_flat_dt_is_compatible(root, "fsl,P1021RDB-PC"))
		return 1;
	return 0;
}

static int __init p2020_rdb_pc_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	if (of_flat_dt_is_compatible(root, "fsl,P2020RDB-PC"))
		return 1;
	return 0;
}

static int __init p1025_rdb_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	return of_flat_dt_is_compatible(root, "fsl,P1025RDB");
}

static int __init p1020_mbg_pc_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	return of_flat_dt_is_compatible(root, "fsl,P1020MBG-PC");
}

static int __init p1020_utm_pc_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC");
}

static int __init p1024_rdb_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	return of_flat_dt_is_compatible(root, "fsl,P1024RDB");
}

define_machine(p2020_rdb) {
	.name			= "P2020 RDB",
	.probe			= p2020_rdb_probe,
	.setup_arch		= mpc85xx_rdb_setup_arch,
	.init_IRQ		= mpc85xx_rdb_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};

define_machine(p1020_rdb) {
	.name			= "P1020 RDB",
	.probe			= p1020_rdb_probe,
	.setup_arch		= mpc85xx_rdb_setup_arch,
	.init_IRQ		= mpc85xx_rdb_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};

define_machine(p1021_rdb_pc) {
	.name			= "P1021 RDB-PC",
	.probe			= p1021_rdb_pc_probe,
	.setup_arch		= mpc85xx_rdb_setup_arch,
	.init_IRQ		= mpc85xx_rdb_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};

define_machine(p2020_rdb_pc) {
	.name			= "P2020RDB-PC",
	.probe			= p2020_rdb_pc_probe,
	.setup_arch		= mpc85xx_rdb_setup_arch,
	.init_IRQ		= mpc85xx_rdb_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};

define_machine(p1025_rdb) {
	.name			= "P1025 RDB",
	.probe			= p1025_rdb_probe,
	.setup_arch		= mpc85xx_rdb_setup_arch,
	.init_IRQ		= mpc85xx_rdb_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};

define_machine(p1020_mbg_pc) {
	.name			= "P1020 MBG-PC",
	.probe			= p1020_mbg_pc_probe,
	.setup_arch		= mpc85xx_rdb_setup_arch,
	.init_IRQ		= mpc85xx_rdb_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};

define_machine(p1020_utm_pc) {
	.name			= "P1020 UTM-PC",
	.probe			= p1020_utm_pc_probe,
	.setup_arch		= mpc85xx_rdb_setup_arch,
	.init_IRQ		= mpc85xx_rdb_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};

define_machine(p1020_rdb_pc) {
	.name			= "P1020RDB-PC",
	.probe			= p1020_rdb_pc_probe,
	.setup_arch		= mpc85xx_rdb_setup_arch,
	.init_IRQ		= mpc85xx_rdb_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};

define_machine(p1024_rdb) {
	.name			= "P1024 RDB",
	.probe			= p1024_rdb_probe,
	.setup_arch		= mpc85xx_rdb_setup_arch,
	.init_IRQ		= mpc85xx_rdb_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};
Commit	Line	Data
fb8e3e1f PA	1	/*
	2	* MPC85xx RDB Board Setup
	3	*
7e6af144	4	* Copyright 2009,2012 Freescale Semiconductor Inc.
fb8e3e1f PA	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12	#include <linux/stddef.h>
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
	15	#include <linux/kdev_t.h>
	16	#include <linux/delay.h>
	17	#include <linux/seq_file.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/of_platform.h>
	20
fb8e3e1f PA	21	#include <asm/time.h>
	22	#include <asm/machdep.h>
	23	#include <asm/pci-bridge.h>
	24	#include <mm/mmu_decl.h>
	25	#include <asm/prom.h>
	26	#include <asm/udbg.h>
	27	#include <asm/mpic.h>
04e358d8 ZF	28	#include <asm/qe.h>
	29	#include <asm/qe_ic.h>
	30	#include <asm/fsl_guts.h>
fb8e3e1f PA	31
	32	#include <sysdev/fsl_soc.h>
	33	#include <sysdev/fsl_pci.h>
582d3e09	34	#include "smp.h"
fb8e3e1f	35
543a07b1 DES	36	#include "mpc85xx.h"
543a07b1 DES	37
fb8e3e1f PA	38	#undef DEBUG
	39
	40	#ifdef DEBUG
	41	#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
	42	#else
	43	#define DBG(fmt, args...)
	44	#endif
	45
	46
	47	void __init mpc85xx_rdb_pic_init(void)
	48	{
	49	struct mpic *mpic;
dc2e673d	50	unsigned long root = of_get_flat_dt_root();
fb8e3e1f	51
04e358d8 ZF	52	#ifdef CONFIG_QUICC_ENGINE
	53	struct device_node *np;
	54	#endif
	55
a63e23b9	56	if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
e55d7f73	57	mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET \|
5019609f	58	MPIC_BIG_ENDIAN \|
a63e23b9	59	MPIC_SINGLE_DEST_CPU,
dc2e673d PA	60	0, 256, " OpenPIC ");
dc2e673d PA	61	} else {
996983b7	62	mpic = mpic_alloc(NULL, 0,
5019609f	63	MPIC_BIG_ENDIAN \|
fb8e3e1f PA	64	MPIC_SINGLE_DEST_CPU,
fb8e3e1f PA	65	0, 256, " OpenPIC ");
dc2e673d	66	}
fb8e3e1f PA	67
fb8e3e1f PA	68	BUG_ON(mpic == NULL);
fb8e3e1f	69	mpic_init(mpic);
04e358d8 ZF	70
	71	#ifdef CONFIG_QUICC_ENGINE
	72	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
	73	if (np) {
	74	qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
	75	qe_ic_cascade_high_mpic);
	76	of_node_put(np);
	77
	78	} else
	79	pr_err("%s: Could not find qe-ic node\n", __func__);
	80	#endif
	81
fb8e3e1f PA	82	}
	83
	84	/*
	85	* Setup the architecture
	86	*/
fb8e3e1f PA	87	static void __init mpc85xx_rdb_setup_arch(void)
fb8e3e1f PA	88	{
905e75c4	89	#ifdef CONFIG_QUICC_ENGINE
fb8e3e1f PA	90	struct device_node *np;
	91	#endif
	92
	93	if (ppc_md.progress)
	94	ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
	95
fb8e3e1f	96	mpc85xx_smp_init();
04e358d8	97
905e75c4 JH	98	fsl_pci_assign_primary();
905e75c4 JH	99
04e358d8 ZF	100	#ifdef CONFIG_QUICC_ENGINE
	101	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	102	if (!np) {
	103	pr_err("%s: Could not find Quicc Engine node\n", __func__);
	104	goto qe_fail;
	105	}
	106
	107	qe_reset();
	108	of_node_put(np);
	109
	110	np = of_find_node_by_name(NULL, "par_io");
	111	if (np) {
	112	struct device_node *ucc;
	113
	114	par_io_init(np);
	115	of_node_put(np);
	116
	117	for_each_node_by_name(ucc, "ucc")
	118	par_io_of_config(ucc);
	119
	120	}
	121	#if defined(CONFIG_UCC_GETH) \|\| defined(CONFIG_SERIAL_QE)
	122	if (machine_is(p1025_rdb)) {
	123
9cb6abcb	124	struct ccsr_guts __iomem *guts;
04e358d8 ZF	125
	126	np = of_find_node_by_name(NULL, "global-utilities");
	127	if (np) {
	128	guts = of_iomap(np, 0);
	129	if (!guts) {
	130
	131	pr_err("mpc85xx-rdb: could not map global utilities register\n");
	132
	133	} else {
	134	/* P1025 has pins muxed for QE and other functions. To
	135	* enable QE UEC mode, we need to set bit QE0 for UCC1
	136	* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
	137	* and QE12 for QE MII management singals in PMUXCR
	138	* register.
	139	*/
	140	setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) \|
	141	MPC85xx_PMUXCR_QE(3) \|
	142	MPC85xx_PMUXCR_QE(9) \|
	143	MPC85xx_PMUXCR_QE(12));
	144	iounmap(guts);
	145	}
	146	of_node_put(np);
	147	}
	148
	149	}
	150	#endif
	151
	152	qe_fail:
	153	#endif /* CONFIG_QUICC_ENGINE */
	154
fb8e3e1f PA	155	printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
	156	}
	157
905e75c4 JH	158	machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices);
	159	machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
	160	machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
	161	machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices);
	162	machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
	163	machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
	164	machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
	165	machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices);
	166	machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices);
fb8e3e1f PA	167
	168	/*
	169	* Called very early, device-tree isn't unflattened
	170	*/
	171	static int __init p2020_rdb_probe(void)
	172	{
	173	unsigned long root = of_get_flat_dt_root();
	174
	175	if (of_flat_dt_is_compatible(root, "fsl,P2020RDB"))
	176	return 1;
	177	return 0;
	178	}
	179
52dffd7f PA	180	static int __init p1020_rdb_probe(void)
	181	{
	182	unsigned long root = of_get_flat_dt_root();
	183
	184	if (of_flat_dt_is_compatible(root, "fsl,P1020RDB"))
	185	return 1;
	186	return 0;
	187	}
	188
7e6af144 ZF	189	static int __init p1020_rdb_pc_probe(void)
	190	{
	191	unsigned long root = of_get_flat_dt_root();
	192
	193	return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PC");
	194	}
	195
b73bdf48 XJ	196	static int __init p1021_rdb_pc_probe(void)
	197	{
	198	unsigned long root = of_get_flat_dt_root();
	199
	200	if (of_flat_dt_is_compatible(root, "fsl,P1021RDB-PC"))
	201	return 1;
	202	return 0;
	203	}
	204
35ce1b5a TY	205	static int __init p2020_rdb_pc_probe(void)
	206	{
	207	unsigned long root = of_get_flat_dt_root();
	208
	209	if (of_flat_dt_is_compatible(root, "fsl,P2020RDB-PC"))
	210	return 1;
	211	return 0;
	212	}
	213
6886780a ZF	214	static int __init p1025_rdb_probe(void)
	215	{
	216	unsigned long root = of_get_flat_dt_root();
	217
	218	return of_flat_dt_is_compatible(root, "fsl,P1025RDB");
	219	}
	220
d1fb1060 JH	221	static int __init p1020_mbg_pc_probe(void)
	222	{
	223	unsigned long root = of_get_flat_dt_root();
	224
	225	return of_flat_dt_is_compatible(root, "fsl,P1020MBG-PC");
	226	}
	227
1a244b83 JH	228	static int __init p1020_utm_pc_probe(void)
	229	{
	230	unsigned long root = of_get_flat_dt_root();
	231
	232	return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC");
	233	}
	234
063e94bb TY	235	static int __init p1024_rdb_probe(void)
	236	{
	237	unsigned long root = of_get_flat_dt_root();
	238
	239	return of_flat_dt_is_compatible(root, "fsl,P1024RDB");
	240	}
	241
fb8e3e1f PA	242	define_machine(p2020_rdb) {
	243	.name = "P2020 RDB",
	244	.probe = p2020_rdb_probe,
	245	.setup_arch = mpc85xx_rdb_setup_arch,
	246	.init_IRQ = mpc85xx_rdb_pic_init,
	247	#ifdef CONFIG_PCI
	248	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	249	#endif
	250	.get_irq = mpic_get_irq,
	251	.restart = fsl_rstcr_restart,
	252	.calibrate_decr = generic_calibrate_decr,
	253	.progress = udbg_progress,
	254	};
52dffd7f PA	255
	256	define_machine(p1020_rdb) {
	257	.name = "P1020 RDB",
	258	.probe = p1020_rdb_probe,
	259	.setup_arch = mpc85xx_rdb_setup_arch,
	260	.init_IRQ = mpc85xx_rdb_pic_init,
	261	#ifdef CONFIG_PCI
	262	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	263	#endif
	264	.get_irq = mpic_get_irq,
	265	.restart = fsl_rstcr_restart,
	266	.calibrate_decr = generic_calibrate_decr,
	267	.progress = udbg_progress,
	268	};
b73bdf48 XJ	269
	270	define_machine(p1021_rdb_pc) {
	271	.name = "P1021 RDB-PC",
	272	.probe = p1021_rdb_pc_probe,
	273	.setup_arch = mpc85xx_rdb_setup_arch,
	274	.init_IRQ = mpc85xx_rdb_pic_init,
	275	#ifdef CONFIG_PCI
	276	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	277	#endif
	278	.get_irq = mpic_get_irq,
	279	.restart = fsl_rstcr_restart,
	280	.calibrate_decr = generic_calibrate_decr,
	281	.progress = udbg_progress,
	282	};
35ce1b5a TY	283
	284	define_machine(p2020_rdb_pc) {
	285	.name = "P2020RDB-PC",
	286	.probe = p2020_rdb_pc_probe,
	287	.setup_arch = mpc85xx_rdb_setup_arch,
	288	.init_IRQ = mpc85xx_rdb_pic_init,
	289	#ifdef CONFIG_PCI
	290	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	291	#endif
	292	.get_irq = mpic_get_irq,
	293	.restart = fsl_rstcr_restart,
	294	.calibrate_decr = generic_calibrate_decr,
	295	.progress = udbg_progress,
	296	};
6886780a ZF	297
	298	define_machine(p1025_rdb) {
	299	.name = "P1025 RDB",
	300	.probe = p1025_rdb_probe,
	301	.setup_arch = mpc85xx_rdb_setup_arch,
	302	.init_IRQ = mpc85xx_rdb_pic_init,
	303	#ifdef CONFIG_PCI
	304	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	305	#endif
	306	.get_irq = mpic_get_irq,
	307	.restart = fsl_rstcr_restart,
	308	.calibrate_decr = generic_calibrate_decr,
	309	.progress = udbg_progress,
	310	};
d1fb1060 JH	311
	312	define_machine(p1020_mbg_pc) {
	313	.name = "P1020 MBG-PC",
	314	.probe = p1020_mbg_pc_probe,
	315	.setup_arch = mpc85xx_rdb_setup_arch,
	316	.init_IRQ = mpc85xx_rdb_pic_init,
	317	#ifdef CONFIG_PCI
	318	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	319	#endif
	320	.get_irq = mpic_get_irq,
	321	.restart = fsl_rstcr_restart,
	322	.calibrate_decr = generic_calibrate_decr,
	323	.progress = udbg_progress,
	324	};
1a244b83 JH	325
	326	define_machine(p1020_utm_pc) {
	327	.name = "P1020 UTM-PC",
	328	.probe = p1020_utm_pc_probe,
	329	.setup_arch = mpc85xx_rdb_setup_arch,
	330	.init_IRQ = mpc85xx_rdb_pic_init,
	331	#ifdef CONFIG_PCI
	332	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	333	#endif
	334	.get_irq = mpic_get_irq,
	335	.restart = fsl_rstcr_restart,
	336	.calibrate_decr = generic_calibrate_decr,
	337	.progress = udbg_progress,
	338	};
7e6af144 ZF	339
	340	define_machine(p1020_rdb_pc) {
	341	.name = "P1020RDB-PC",
	342	.probe = p1020_rdb_pc_probe,
	343	.setup_arch = mpc85xx_rdb_setup_arch,
	344	.init_IRQ = mpc85xx_rdb_pic_init,
	345	#ifdef CONFIG_PCI
	346	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	347	#endif
	348	.get_irq = mpic_get_irq,
	349	.restart = fsl_rstcr_restart,
	350	.calibrate_decr = generic_calibrate_decr,
	351	.progress = udbg_progress,
	352	};
063e94bb TY	353
	354	define_machine(p1024_rdb) {
	355	.name = "P1024 RDB",
	356	.probe = p1024_rdb_probe,
	357	.setup_arch = mpc85xx_rdb_setup_arch,
	358	.init_IRQ = mpc85xx_rdb_pic_init,
	359	#ifdef CONFIG_PCI
	360	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	361	#endif
	362	.get_irq = mpic_get_irq,
	363	.restart = fsl_rstcr_restart,
	364	.calibrate_decr = generic_calibrate_decr,
	365	.progress = udbg_progress,
	366	};