[deliverable/linux.git] / arch / powerpc / platforms / 85xx / p1022_ds.c

/*
 * P1022DS board specific routines
 *
 * Authors: Travis Wheatley <travis.wheatley@freescale.com>
 *          Dave Liu <daveliu@freescale.com>
 *          Timur Tabi <timur@freescale.com>
 *
 * Copyright 2010 Freescale Semiconductor, Inc.
 *
 * This file is taken from the Freescale P1022DS BSP, with modifications:
 * 2) No AMP support
 * 3) No PCI endpoint support
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/pci.h>
#include <linux/of_platform.h>
#include <linux/memblock.h>
#include <asm/div64.h>
#include <asm/mpic.h>
#include <asm/swiotlb.h>

#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <asm/udbg.h>
#include <asm/fsl_guts.h>
#include <asm/fsl_lbc.h>
#include "smp.h"

#include "mpc85xx.h"

#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)

#define PMUXCR_ELBCDIU_MASK	0xc0000000
#define PMUXCR_ELBCDIU_NOR16	0x80000000
#define PMUXCR_ELBCDIU_DIU	0x40000000

/*
 * Board-specific initialization of the DIU.  This code should probably be
 * executed when the DIU is opened, rather than in arch code, but the DIU
 * driver does not have a mechanism for this (yet).
 *
 * This is especially problematic on the P1022DS because the local bus (eLBC)
 * and the DIU video signals share the same pins, which means that enabling the
 * DIU will disable access to NOR flash.
 */

/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
#define CLKDVDR_PXCKEN		0x80000000
#define CLKDVDR_PXCKINV		0x10000000
#define CLKDVDR_PXCKDLY		0x06000000
#define CLKDVDR_PXCLK_MASK	0x00FF0000

/* Some ngPIXIS register definitions */
#define PX_CTL		3
#define PX_BRDCFG0	8
#define PX_BRDCFG1	9

#define PX_BRDCFG0_ELBC_SPI_MASK	0xc0
#define PX_BRDCFG0_ELBC_SPI_ELBC	0x00
#define PX_BRDCFG0_ELBC_SPI_NULL	0xc0
#define PX_BRDCFG0_ELBC_DIU		0x02

#define PX_BRDCFG1_DVIEN	0x80
#define PX_BRDCFG1_DFPEN	0x40
#define PX_BRDCFG1_BACKLIGHT	0x20
#define PX_BRDCFG1_DDCEN	0x10

#define PX_CTL_ALTACC		0x80

/*
 * DIU Area Descriptor
 *
 * Note that we need to byte-swap the value before it's written to the AD
 * register.  So even though the registers don't look like they're in the same
 * bit positions as they are on the MPC8610, the same value is written to the
 * AD register on the MPC8610 and on the P1022.
 */
#define AD_BYTE_F		0x10000000
#define AD_ALPHA_C_MASK		0x0E000000
#define AD_ALPHA_C_SHIFT	25
#define AD_BLUE_C_MASK		0x01800000
#define AD_BLUE_C_SHIFT		23
#define AD_GREEN_C_MASK		0x00600000
#define AD_GREEN_C_SHIFT	21
#define AD_RED_C_MASK		0x00180000
#define AD_RED_C_SHIFT		19
#define AD_PALETTE		0x00040000
#define AD_PIXEL_S_MASK		0x00030000
#define AD_PIXEL_S_SHIFT	16
#define AD_COMP_3_MASK		0x0000F000
#define AD_COMP_3_SHIFT		12
#define AD_COMP_2_MASK		0x00000F00
#define AD_COMP_2_SHIFT		8
#define AD_COMP_1_MASK		0x000000F0
#define AD_COMP_1_SHIFT		4
#define AD_COMP_0_MASK		0x0000000F
#define AD_COMP_0_SHIFT		0

#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
	cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
	(blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
	(red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
	(c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
	(c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))

/**
 * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
 *
 * The Area Descriptor is a 32-bit value that determine which bits in each
 * pixel are to be used for each color.
 */
static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,
				    unsigned int bits_per_pixel)
{
	switch (bits_per_pixel) {
	case 32:
		/* 0x88883316 */
		return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
	case 24:
		/* 0x88082219 */
		return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
	case 16:
		/* 0x65053118 */
		return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
	default:
		pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
		return 0;
	}
}

/**
 * p1022ds_set_gamma_table: update the gamma table, if necessary
 *
 * On some boards, the gamma table for some ports may need to be modified.
 * This is not the case on the P1022DS, so we do nothing.
*/
static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
				    char *gamma_table_base)
{
}

struct fsl_law {
	u32	lawbar;
	u32	reserved1;
	u32	lawar;
	u32	reserved[5];
};

#define LAWBAR_MASK	0x00F00000
#define LAWBAR_SHIFT	12

#define LAWAR_EN	0x80000000
#define LAWAR_TGT_MASK	0x01F00000
#define LAW_TRGT_IF_LBC	(0x04 << 20)

#define LAWAR_MASK	(LAWAR_EN | LAWAR_TGT_MASK)
#define LAWAR_MATCH	(LAWAR_EN | LAW_TRGT_IF_LBC)

#define BR_BA		0xFFFF8000

/*
 * Map a BRx value to a physical address
 *
 * The localbus BRx registers only store the lower 32 bits of the address.  To
 * obtain the upper four bits, we need to scan the LAW table.  The entry which
 * maps to the localbus will contain the upper four bits.
 */
static phys_addr_t lbc_br_to_phys(const void *ecm, unsigned int count, u32 br)
{
#ifndef CONFIG_PHYS_64BIT
	/*
	 * If we only have 32-bit addressing, then the BRx address *is* the
	 * physical address.
	 */
	return br & BR_BA;
#else
	const struct fsl_law *law = ecm + 0xc08;
	unsigned int i;

	for (i = 0; i < count; i++) {
		u64 lawbar = in_be32(&law[i].lawbar);
		u32 lawar = in_be32(&law[i].lawar);

		if ((lawar & LAWAR_MASK) == LAWAR_MATCH)
			/* Extract the upper four bits */
			return (br & BR_BA) | ((lawbar & LAWBAR_MASK) << 12);
	}

	return 0;
#endif
}

/**
 * p1022ds_set_monitor_port: switch the output to a different monitor port
 */
static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
{
	struct device_node *guts_node;
	struct device_node *lbc_node = NULL;
	struct device_node *law_node = NULL;
	struct ccsr_guts __iomem *guts;
	struct fsl_lbc_regs *lbc = NULL;
	void *ecm = NULL;
	u8 __iomem *lbc_lcs0_ba = NULL;
	u8 __iomem *lbc_lcs1_ba = NULL;
	phys_addr_t cs0_addr, cs1_addr;
	const __be32 *iprop;
	unsigned int num_laws;
	u8 b;

	/* Map the global utilities registers. */
	guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
	if (!guts_node) {
		pr_err("p1022ds: missing global utilties device node\n");
		return;
	}

	guts = of_iomap(guts_node, 0);
	if (!guts) {
		pr_err("p1022ds: could not map global utilties device\n");
		goto exit;
	}

	lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
	if (!lbc_node) {
		pr_err("p1022ds: missing localbus node\n");
		goto exit;
	}

	lbc = of_iomap(lbc_node, 0);
	if (!lbc) {
		pr_err("p1022ds: could not map localbus node\n");
		goto exit;
	}

	law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law");
	if (!law_node) {
		pr_err("p1022ds: missing local access window node\n");
		goto exit;
	}

	ecm = of_iomap(law_node, 0);
	if (!ecm) {
		pr_err("p1022ds: could not map local access window node\n");
		goto exit;
	}

	iprop = of_get_property(law_node, "fsl,num-laws", 0);
	if (!iprop) {
		pr_err("p1022ds: LAW node is missing fsl,num-laws property\n");
		goto exit;
	}
	num_laws = be32_to_cpup(iprop);

	cs0_addr = lbc_br_to_phys(ecm, num_laws, in_be32(&lbc->bank[0].br));
	cs1_addr = lbc_br_to_phys(ecm, num_laws, in_be32(&lbc->bank[1].br));

	lbc_lcs0_ba = ioremap(cs0_addr, 1);
	lbc_lcs1_ba = ioremap(cs1_addr, 1);

	/* Make sure we're in indirect mode first. */
	if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
	    PMUXCR_ELBCDIU_DIU) {
		struct device_node *pixis_node;
		void __iomem *pixis;

		pixis_node =
			of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
		if (!pixis_node) {
			pr_err("p1022ds: missing pixis node\n");
			goto exit;
		}

		pixis = of_iomap(pixis_node, 0);
		of_node_put(pixis_node);
		if (!pixis) {
			pr_err("p1022ds: could not map pixis registers\n");
			goto exit;
		}

		/* Enable indirect PIXIS mode.  */
		setbits8(pixis + PX_CTL, PX_CTL_ALTACC);
		iounmap(pixis);

		/* Switch the board mux to the DIU */
		out_8(lbc_lcs0_ba, PX_BRDCFG0);	/* BRDCFG0 */
		b = in_8(lbc_lcs1_ba);
		b |= PX_BRDCFG0_ELBC_DIU;
		out_8(lbc_lcs1_ba, b);

		/* Set the chip mux to DIU mode. */
		clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK,
				PMUXCR_ELBCDIU_DIU);
		in_be32(&guts->pmuxcr);
	}


	switch (port) {
	case FSL_DIU_PORT_DVI:
		/* Enable the DVI port, disable the DFP and the backlight */
		out_8(lbc_lcs0_ba, PX_BRDCFG1);
		b = in_8(lbc_lcs1_ba);
		b &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
		b |= PX_BRDCFG1_DVIEN;
		out_8(lbc_lcs1_ba, b);
		break;
	case FSL_DIU_PORT_LVDS:
		/*
		 * LVDS also needs backlight enabled, otherwise the display
		 * will be blank.
		 */
		/* Enable the DFP port, disable the DVI and the backlight */
		out_8(lbc_lcs0_ba, PX_BRDCFG1);
		b = in_8(lbc_lcs1_ba);
		b &= ~PX_BRDCFG1_DVIEN;
		b |= PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT;
		out_8(lbc_lcs1_ba, b);
		break;
	default:
		pr_err("p1022ds: unsupported monitor port %i\n", port);
	}

exit:
	if (lbc_lcs1_ba)
		iounmap(lbc_lcs1_ba);
	if (lbc_lcs0_ba)
		iounmap(lbc_lcs0_ba);
	if (lbc)
		iounmap(lbc);
	if (ecm)
		iounmap(ecm);
	if (guts)
		iounmap(guts);

	of_node_put(law_node);
	of_node_put(lbc_node);
	of_node_put(guts_node);
}

/**
 * p1022ds_set_pixel_clock: program the DIU's clock
 *
 * @pixclock: the wavelength, in picoseconds, of the clock
 */
void p1022ds_set_pixel_clock(unsigned int pixclock)
{
	struct device_node *guts_np = NULL;
	struct ccsr_guts __iomem *guts;
	unsigned long freq;
	u64 temp;
	u32 pxclk;

	/* Map the global utilities registers. */
	guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
	if (!guts_np) {
		pr_err("p1022ds: missing global utilties device node\n");
		return;
	}

	guts = of_iomap(guts_np, 0);
	of_node_put(guts_np);
	if (!guts) {
		pr_err("p1022ds: could not map global utilties device\n");
		return;
	}

	/* Convert pixclock from a wavelength to a frequency */
	temp = 1000000000000ULL;
	do_div(temp, pixclock);
	freq = temp;

	/*
	 * 'pxclk' is the ratio of the platform clock to the pixel clock.
	 * This number is programmed into the CLKDVDR register, and the valid
	 * range of values is 2-255.
	 */
	pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
	pxclk = clamp_t(u32, pxclk, 2, 255);

	/* Disable the pixel clock, and set it to non-inverted and no delay */
	clrbits32(&guts->clkdvdr,
		  CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);

	/* Enable the clock and set the pxclk */
	setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));

	iounmap(guts);
}

/**
 * p1022ds_valid_monitor_port: set the monitor port for sysfs
 */
enum fsl_diu_monitor_port
p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
{
	switch (port) {
	case FSL_DIU_PORT_DVI:
	case FSL_DIU_PORT_LVDS:
		return port;
	default:
		return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
	}
}

#endif

void __init p1022_ds_pic_init(void)
{
	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
		MPIC_SINGLE_DEST_CPU,
		0, 256, " OpenPIC  ");
	BUG_ON(mpic == NULL);
	mpic_init(mpic);
}

#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)

/* TRUE if there is a "video=fslfb" command-line parameter. */
static bool fslfb;

/*
 * Search for a "video=fslfb" command-line parameter, and set 'fslfb' to
 * true if we find it.
 *
 * We need to use early_param() instead of __setup() because the normal
 * __setup() gets called to late.  However, early_param() gets called very
 * early, before the device tree is unflattened, so all we can do now is set a
 * global variable.  Later on, p1022_ds_setup_arch() will use that variable
 * to determine if we need to update the device tree.
 */
static int __init early_video_setup(char *options)
{
	fslfb = (strncmp(options, "fslfb:", 6) == 0);

	return 0;
}
early_param("video", early_video_setup);

#endif

/*
 * Setup the architecture
 */
static void __init p1022_ds_setup_arch(void)
{
#ifdef CONFIG_PCI
	struct device_node *np;
#endif
	dma_addr_t max = 0xffffffff;

	if (ppc_md.progress)
		ppc_md.progress("p1022_ds_setup_arch()", 0);

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
		struct resource rsrc;
		struct pci_controller *hose;

		of_address_to_resource(np, 0, &rsrc);

		if ((rsrc.start & 0xfffff) == 0x8000)
			fsl_add_bridge(np, 1);
		else
			fsl_add_bridge(np, 0);

		hose = pci_find_hose_for_OF_device(np);
		max = min(max, hose->dma_window_base_cur +
			  hose->dma_window_size);
	}
#endif

#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
	diu_ops.get_pixel_format	= p1022ds_get_pixel_format;
	diu_ops.set_gamma_table		= p1022ds_set_gamma_table;
	diu_ops.set_monitor_port	= p1022ds_set_monitor_port;
	diu_ops.set_pixel_clock		= p1022ds_set_pixel_clock;
	diu_ops.valid_monitor_port	= p1022ds_valid_monitor_port;

	/*
	 * Disable the NOR and NAND flash nodes if there is video=fslfb...
	 * command-line parameter.  When the DIU is active, the localbus is
	 * unavailable, so we have to disable these nodes before the MTD
	 * driver loads.
	 */
	if (fslfb) {
		struct device_node *np =
			of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");

		if (np) {
			struct device_node *np2;

			of_node_get(np);
			np2 = of_find_compatible_node(np, NULL, "cfi-flash");
			if (np2) {
				static struct property nor_status = {
					.name = "status",
					.value = "disabled",
					.length = sizeof("disabled"),
				};

				/*
				 * prom_update_property() is called before
				 * kmalloc() is available, so the 'new' object
				 * should be allocated in the global area.
				 * The easiest way is to do that is to
				 * allocate one static local variable for each
				 * call to this function.
				 */
				pr_info("p1022ds: disabling %s node",
					np2->full_name);
				prom_update_property(np2, &nor_status);
				of_node_put(np2);
			}

			of_node_get(np);
			np2 = of_find_compatible_node(np, NULL,
						      "fsl,elbc-fcm-nand");
			if (np2) {
				static struct property nand_status = {
					.name = "status",
					.value = "disabled",
					.length = sizeof("disabled"),
				};

				pr_info("p1022ds: disabling %s node",
					np2->full_name);
				prom_update_property(np2, &nand_status);
				of_node_put(np2);
			}

			of_node_put(np);
		}

	}

#endif

	mpc85xx_smp_init();

#ifdef CONFIG_SWIOTLB
	if ((memblock_end_of_DRAM() - 1) > max) {
		ppc_swiotlb_enable = 1;
		set_pci_dma_ops(&swiotlb_dma_ops);
		ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
	}
#endif

	pr_info("Freescale P1022 DS reference board\n");
}

machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);

machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);

/*
 * Called very early, device-tree isn't unflattened
 */
static int __init p1022_ds_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	return of_flat_dt_is_compatible(root, "fsl,p1022ds");
}

define_machine(p1022_ds) {
	.name			= "P1022 DS",
	.probe			= p1022_ds_probe,
	.setup_arch		= p1022_ds_setup_arch,
	.init_IRQ		= p1022_ds_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};
Commit	Line	Data
30be4c96 TT	1	/*
	2	* P1022DS board specific routines
	3	*
	4	* Authors: Travis Wheatley <travis.wheatley@freescale.com>
	5	* Dave Liu <daveliu@freescale.com>
	6	* Timur Tabi <timur@freescale.com>
	7	*
	8	* Copyright 2010 Freescale Semiconductor, Inc.
	9	*
	10	* This file is taken from the Freescale P1022DS BSP, with modifications:
30be4c96 TT	11	* 2) No AMP support
	12	* 3) No PCI endpoint support
	13	*
	14	* This file is licensed under the terms of the GNU General Public License
	15	* version 2. This program is licensed "as is" without any warranty of any
	16	* kind, whether express or implied.
	17	*/
	18
	19	#include <linux/pci.h>
	20	#include <linux/of_platform.h>
dc1c41f4	21	#include <linux/memblock.h>
2c184cd3	22	#include <asm/div64.h>
30be4c96 TT	23	#include <asm/mpic.h>
	24	#include <asm/swiotlb.h>
	25
	26	#include <sysdev/fsl_soc.h>
	27	#include <sysdev/fsl_pci.h>
ba8438fb	28	#include <asm/udbg.h>
2c184cd3	29	#include <asm/fsl_guts.h>
6bd825f0	30	#include <asm/fsl_lbc.h>
582d3e09	31	#include "smp.h"
2c184cd3	32
543a07b1 DES	33	#include "mpc85xx.h"
543a07b1 DES	34
2c184cd3 TT	35	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)
2c184cd3 TT	36
6597c713 TT	37	#define PMUXCR_ELBCDIU_MASK 0xc0000000
	38	#define PMUXCR_ELBCDIU_NOR16 0x80000000
	39	#define PMUXCR_ELBCDIU_DIU 0x40000000
	40
2c184cd3 TT	41	/*
	42	* Board-specific initialization of the DIU. This code should probably be
	43	* executed when the DIU is opened, rather than in arch code, but the DIU
	44	* driver does not have a mechanism for this (yet).
	45	*
	46	* This is especially problematic on the P1022DS because the local bus (eLBC)
	47	* and the DIU video signals share the same pins, which means that enabling the
	48	* DIU will disable access to NOR flash.
	49	*/
	50
	51	/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
	52	#define CLKDVDR_PXCKEN 0x80000000
	53	#define CLKDVDR_PXCKINV 0x10000000
	54	#define CLKDVDR_PXCKDLY 0x06000000
	55	#define CLKDVDR_PXCLK_MASK 0x00FF0000
	56
	57	/* Some ngPIXIS register definitions */
6597c713 TT	58	#define PX_CTL 3
	59	#define PX_BRDCFG0 8
	60	#define PX_BRDCFG1 9
	61
	62	#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
	63	#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
	64	#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
	65	#define PX_BRDCFG0_ELBC_DIU 0x02
	66
2c184cd3 TT	67	#define PX_BRDCFG1_DVIEN 0x80
	68	#define PX_BRDCFG1_DFPEN 0x40
	69	#define PX_BRDCFG1_BACKLIGHT 0x20
	70	#define PX_BRDCFG1_DDCEN 0x10
	71
6597c713 TT	72	#define PX_CTL_ALTACC 0x80
6597c713 TT	73
2c184cd3 TT	74	/*
	75	* DIU Area Descriptor
	76	*
	77	* Note that we need to byte-swap the value before it's written to the AD
	78	* register. So even though the registers don't look like they're in the same
	79	* bit positions as they are on the MPC8610, the same value is written to the
	80	* AD register on the MPC8610 and on the P1022.
	81	*/
	82	#define AD_BYTE_F 0x10000000
	83	#define AD_ALPHA_C_MASK 0x0E000000
	84	#define AD_ALPHA_C_SHIFT 25
	85	#define AD_BLUE_C_MASK 0x01800000
	86	#define AD_BLUE_C_SHIFT 23
	87	#define AD_GREEN_C_MASK 0x00600000
	88	#define AD_GREEN_C_SHIFT 21
	89	#define AD_RED_C_MASK 0x00180000
	90	#define AD_RED_C_SHIFT 19
	91	#define AD_PALETTE 0x00040000
	92	#define AD_PIXEL_S_MASK 0x00030000
	93	#define AD_PIXEL_S_SHIFT 16
	94	#define AD_COMP_3_MASK 0x0000F000
	95	#define AD_COMP_3_SHIFT 12
	96	#define AD_COMP_2_MASK 0x00000F00
	97	#define AD_COMP_2_SHIFT 8
	98	#define AD_COMP_1_MASK 0x000000F0
	99	#define AD_COMP_1_SHIFT 4
	100	#define AD_COMP_0_MASK 0x0000000F
	101	#define AD_COMP_0_SHIFT 0
	102
	103	#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
	104	cpu_to_le32(AD_BYTE_F \| (alpha << AD_ALPHA_C_SHIFT) \| \
	105	(blue << AD_BLUE_C_SHIFT) \| (green << AD_GREEN_C_SHIFT) \| \
	106	(red << AD_RED_C_SHIFT) \| (c3 << AD_COMP_3_SHIFT) \| \
	107	(c2 << AD_COMP_2_SHIFT) \| (c1 << AD_COMP_1_SHIFT) \| \
	108	(c0 << AD_COMP_0_SHIFT) \| (size << AD_PIXEL_S_SHIFT))
	109
	110	/**
	111	* p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
	112	*
	113	* The Area Descriptor is a 32-bit value that determine which bits in each
	114	* pixel are to be used for each color.
	115	*/
7653aaab TT	116	static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,
7653aaab TT	117	unsigned int bits_per_pixel)
2c184cd3 TT	118	{
	119	switch (bits_per_pixel) {
	120	case 32:
	121	/* 0x88883316 */
	122	return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
	123	case 24:
	124	/* 0x88082219 */
	125	return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
	126	case 16:
	127	/* 0x65053118 */
	128	return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
	129	default:
	130	pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
	131	return 0;
	132	}
	133	}
	134
	135	/**
	136	* p1022ds_set_gamma_table: update the gamma table, if necessary
	137	*
	138	* On some boards, the gamma table for some ports may need to be modified.
	139	* This is not the case on the P1022DS, so we do nothing.
	140	*/
7653aaab TT	141	static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
7653aaab TT	142	char *gamma_table_base)
2c184cd3 TT	143	{
	144	}
	145
6bd825f0 TT	146	struct fsl_law {
	147	u32 lawbar;
	148	u32 reserved1;
	149	u32 lawar;
	150	u32 reserved[5];
	151	};
	152
	153	#define LAWBAR_MASK 0x00F00000
	154	#define LAWBAR_SHIFT 12
	155
	156	#define LAWAR_EN 0x80000000
	157	#define LAWAR_TGT_MASK 0x01F00000
	158	#define LAW_TRGT_IF_LBC (0x04 << 20)
	159
	160	#define LAWAR_MASK (LAWAR_EN \| LAWAR_TGT_MASK)
	161	#define LAWAR_MATCH (LAWAR_EN \| LAW_TRGT_IF_LBC)
	162
	163	#define BR_BA 0xFFFF8000
	164
	165	/*
	166	* Map a BRx value to a physical address
	167	*
	168	* The localbus BRx registers only store the lower 32 bits of the address. To
	169	* obtain the upper four bits, we need to scan the LAW table. The entry which
	170	* maps to the localbus will contain the upper four bits.
	171	*/
	172	static phys_addr_t lbc_br_to_phys(const void *ecm, unsigned int count, u32 br)
	173	{
	174	#ifndef CONFIG_PHYS_64BIT
	175	/*
	176	* If we only have 32-bit addressing, then the BRx address is the
	177	* physical address.
	178	*/
	179	return br & BR_BA;
	180	#else
	181	const struct fsl_law *law = ecm + 0xc08;
	182	unsigned int i;
	183
	184	for (i = 0; i < count; i++) {
	185	u64 lawbar = in_be32(&law[i].lawbar);
	186	u32 lawar = in_be32(&law[i].lawar);
	187
	188	if ((lawar & LAWAR_MASK) == LAWAR_MATCH)
	189	/* Extract the upper four bits */
	190	return (br & BR_BA) \| ((lawbar & LAWBAR_MASK) << 12);
	191	}
	192
	193	return 0;
	194	#endif
	195	}
	196
2c184cd3 TT	197	/**
2c184cd3 TT	198	* p1022ds_set_monitor_port: switch the output to a different monitor port
2c184cd3	199	*/
7653aaab	200	static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
2c184cd3	201	{
6597c713	202	struct device_node *guts_node;
6bd825f0 TT	203	struct device_node *lbc_node = NULL;
6bd825f0 TT	204	struct device_node *law_node = NULL;
9cb6abcb	205	struct ccsr_guts __iomem *guts;
6bd825f0 TT	206	struct fsl_lbc_regs *lbc = NULL;
6bd825f0 TT	207	void *ecm = NULL;
6597c713 TT	208	u8 __iomem *lbc_lcs0_ba = NULL;
6597c713 TT	209	u8 __iomem *lbc_lcs1_ba = NULL;
6bd825f0 TT	210	phys_addr_t cs0_addr, cs1_addr;
	211	const __be32 *iprop;
	212	unsigned int num_laws;
6597c713 TT	213	u8 b;
	214
	215	/* Map the global utilities registers. */
	216	guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
	217	if (!guts_node) {
	218	pr_err("p1022ds: missing global utilties device node\n");
2c184cd3 TT	219	return;
	220	}
	221
6597c713 TT	222	guts = of_iomap(guts_node, 0);
	223	if (!guts) {
	224	pr_err("p1022ds: could not map global utilties device\n");
	225	goto exit;
	226	}
	227
6bd825f0 TT	228	lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
	229	if (!lbc_node) {
	230	pr_err("p1022ds: missing localbus node\n");
	231	goto exit;
	232	}
	233
	234	lbc = of_iomap(lbc_node, 0);
	235	if (!lbc) {
	236	pr_err("p1022ds: could not map localbus node\n");
6597c713	237	goto exit;
2c184cd3	238	}
6597c713	239
6bd825f0 TT	240	law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law");
	241	if (!law_node) {
	242	pr_err("p1022ds: missing local access window node\n");
6597c713 TT	243	goto exit;
	244	}
	245
6bd825f0 TT	246	ecm = of_iomap(law_node, 0);
	247	if (!ecm) {
	248	pr_err("p1022ds: could not map local access window node\n");
6597c713 TT	249	goto exit;
	250	}
	251
6bd825f0 TT	252	iprop = of_get_property(law_node, "fsl,num-laws", 0);
	253	if (!iprop) {
	254	pr_err("p1022ds: LAW node is missing fsl,num-laws property\n");
	255	goto exit;
	256	}
	257	num_laws = be32_to_cpup(iprop);
	258
	259	cs0_addr = lbc_br_to_phys(ecm, num_laws, in_be32(&lbc->bank[0].br));
	260	cs1_addr = lbc_br_to_phys(ecm, num_laws, in_be32(&lbc->bank[1].br));
	261
	262	lbc_lcs0_ba = ioremap(cs0_addr, 1);
	263	lbc_lcs1_ba = ioremap(cs1_addr, 1);
	264
6597c713 TT	265	/* Make sure we're in indirect mode first. */
	266	if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
	267	PMUXCR_ELBCDIU_DIU) {
	268	struct device_node *pixis_node;
	269	void __iomem *pixis;
	270
	271	pixis_node =
	272	of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
	273	if (!pixis_node) {
	274	pr_err("p1022ds: missing pixis node\n");
	275	goto exit;
	276	}
	277
	278	pixis = of_iomap(pixis_node, 0);
	279	of_node_put(pixis_node);
	280	if (!pixis) {
	281	pr_err("p1022ds: could not map pixis registers\n");
	282	goto exit;
	283	}
	284
	285	/* Enable indirect PIXIS mode. */
	286	setbits8(pixis + PX_CTL, PX_CTL_ALTACC);
	287	iounmap(pixis);
	288
	289	/* Switch the board mux to the DIU */
	290	out_8(lbc_lcs0_ba, PX_BRDCFG0); /* BRDCFG0 */
	291	b = in_8(lbc_lcs1_ba);
	292	b \|= PX_BRDCFG0_ELBC_DIU;
	293	out_8(lbc_lcs1_ba, b);
	294
	295	/* Set the chip mux to DIU mode. */
	296	clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK,
	297	PMUXCR_ELBCDIU_DIU);
	298	in_be32(&guts->pmuxcr);
	299	}
	300
2c184cd3	301
7653aaab TT	302	switch (port) {
7653aaab TT	303	case FSL_DIU_PORT_DVI:
2c184cd3	304	/* Enable the DVI port, disable the DFP and the backlight */
6597c713 TT	305	out_8(lbc_lcs0_ba, PX_BRDCFG1);
	306	b = in_8(lbc_lcs1_ba);
	307	b &= ~(PX_BRDCFG1_DFPEN \| PX_BRDCFG1_BACKLIGHT);
	308	b \|= PX_BRDCFG1_DVIEN;
	309	out_8(lbc_lcs1_ba, b);
2c184cd3	310	break;
7653aaab	311	case FSL_DIU_PORT_LVDS:
6597c713 TT	312	/*
	313	* LVDS also needs backlight enabled, otherwise the display
	314	* will be blank.
	315	*/
2c184cd3	316	/* Enable the DFP port, disable the DVI and the backlight */
6597c713 TT	317	out_8(lbc_lcs0_ba, PX_BRDCFG1);
	318	b = in_8(lbc_lcs1_ba);
	319	b &= ~PX_BRDCFG1_DVIEN;
	320	b \|= PX_BRDCFG1_DFPEN \| PX_BRDCFG1_BACKLIGHT;
	321	out_8(lbc_lcs1_ba, b);
2c184cd3 TT	322	break;
2c184cd3 TT	323	default:
7653aaab	324	pr_err("p1022ds: unsupported monitor port %i\n", port);
2c184cd3	325	}
31655958	326
6597c713 TT	327	exit:
	328	if (lbc_lcs1_ba)
	329	iounmap(lbc_lcs1_ba);
	330	if (lbc_lcs0_ba)
	331	iounmap(lbc_lcs0_ba);
6bd825f0 TT	332	if (lbc)
	333	iounmap(lbc);
	334	if (ecm)
	335	iounmap(ecm);
6597c713 TT	336	if (guts)
	337	iounmap(guts);
	338
6bd825f0 TT	339	of_node_put(law_node);
6bd825f0 TT	340	of_node_put(lbc_node);
6597c713	341	of_node_put(guts_node);
2c184cd3 TT	342	}
	343
	344	/**
	345	* p1022ds_set_pixel_clock: program the DIU's clock
	346	*
	347	* @pixclock: the wavelength, in picoseconds, of the clock
	348	*/
	349	void p1022ds_set_pixel_clock(unsigned int pixclock)
	350	{
	351	struct device_node *guts_np = NULL;
9cb6abcb	352	struct ccsr_guts __iomem *guts;
2c184cd3 TT	353	unsigned long freq;
	354	u64 temp;
	355	u32 pxclk;
	356
	357	/* Map the global utilities registers. */
	358	guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
	359	if (!guts_np) {
	360	pr_err("p1022ds: missing global utilties device node\n");
	361	return;
	362	}
	363
	364	guts = of_iomap(guts_np, 0);
	365	of_node_put(guts_np);
	366	if (!guts) {
	367	pr_err("p1022ds: could not map global utilties device\n");
	368	return;
	369	}
	370
	371	/* Convert pixclock from a wavelength to a frequency */
	372	temp = 1000000000000ULL;
	373	do_div(temp, pixclock);
	374	freq = temp;
	375
7b93eccf TT	376	/*
	377	* 'pxclk' is the ratio of the platform clock to the pixel clock.
	378	* This number is programmed into the CLKDVDR register, and the valid
	379	* range of values is 2-255.
	380	*/
2c184cd3	381	pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
7b93eccf	382	pxclk = clamp_t(u32, pxclk, 2, 255);
2c184cd3 TT	383
	384	/* Disable the pixel clock, and set it to non-inverted and no delay */
	385	clrbits32(&guts->clkdvdr,
	386	CLKDVDR_PXCKEN \| CLKDVDR_PXCKDLY \| CLKDVDR_PXCLK_MASK);
	387
	388	/* Enable the clock and set the pxclk */
	389	setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN \| (pxclk << 16));
31655958 TT	390
31655958 TT	391	iounmap(guts);
2c184cd3 TT	392	}
	393
	394	/**
7653aaab	395	* p1022ds_valid_monitor_port: set the monitor port for sysfs
2c184cd3	396	*/
7653aaab TT	397	enum fsl_diu_monitor_port
7653aaab TT	398	p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
2c184cd3	399	{
7653aaab TT	400	switch (port) {
	401	case FSL_DIU_PORT_DVI:
	402	case FSL_DIU_PORT_LVDS:
	403	return port;
	404	default:
	405	return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
	406	}
2c184cd3 TT	407	}
	408
	409	#endif
30be4c96 TT	410
	411	void __init p1022_ds_pic_init(void)
	412	{
e55d7f73	413	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN \|
30be4c96 TT	414	MPIC_SINGLE_DEST_CPU,
30be4c96 TT	415	0, 256, " OpenPIC ");
30be4c96	416	BUG_ON(mpic == NULL);
30be4c96 TT	417	mpic_init(mpic);
	418	}
	419
4951896a TT	420	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)
4951896a TT	421
4951896a TT	422	/* TRUE if there is a "video=fslfb" command-line parameter. */
	423	static bool fslfb;
	424
	425	/*
	426	* Search for a "video=fslfb" command-line parameter, and set 'fslfb' to
	427	* true if we find it.
	428	*
	429	* We need to use early_param() instead of __setup() because the normal
	430	* __setup() gets called to late. However, early_param() gets called very
	431	* early, before the device tree is unflattened, so all we can do now is set a
	432	* global variable. Later on, p1022_ds_setup_arch() will use that variable
	433	* to determine if we need to update the device tree.
	434	*/
	435	static int __init early_video_setup(char *options)
	436	{
	437	fslfb = (strncmp(options, "fslfb:", 6) == 0);
	438
	439	return 0;
	440	}
	441	early_param("video", early_video_setup);
	442
	443	#endif
	444
30be4c96 TT	445	/*
	446	* Setup the architecture
	447	*/
	448	static void __init p1022_ds_setup_arch(void)
	449	{
	450	#ifdef CONFIG_PCI
	451	struct device_node *np;
	452	#endif
	453	dma_addr_t max = 0xffffffff;
	454
	455	if (ppc_md.progress)
	456	ppc_md.progress("p1022_ds_setup_arch()", 0);
	457
	458	#ifdef CONFIG_PCI
	459	for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
	460	struct resource rsrc;
	461	struct pci_controller *hose;
	462
	463	of_address_to_resource(np, 0, &rsrc);
	464
	465	if ((rsrc.start & 0xfffff) == 0x8000)
	466	fsl_add_bridge(np, 1);
	467	else
	468	fsl_add_bridge(np, 0);
	469
	470	hose = pci_find_hose_for_OF_device(np);
	471	max = min(max, hose->dma_window_base_cur +
	472	hose->dma_window_size);
	473	}
	474	#endif
	475
2c184cd3 TT	476	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)
	477	diu_ops.get_pixel_format = p1022ds_get_pixel_format;
	478	diu_ops.set_gamma_table = p1022ds_set_gamma_table;
	479	diu_ops.set_monitor_port = p1022ds_set_monitor_port;
	480	diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
7653aaab	481	diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
4951896a TT	482
4951896a TT	483	/*
6269f258 TT	484	* Disable the NOR and NAND flash nodes if there is video=fslfb...
	485	* command-line parameter. When the DIU is active, the localbus is
	486	* unavailable, so we have to disable these nodes before the MTD
	487	* driver loads.
4951896a TT	488	*/
	489	if (fslfb) {
	490	struct device_node *np =
	491	of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
	492
	493	if (np) {
6269f258 TT	494	struct device_node *np2;
	495
	496	of_node_get(np);
	497	np2 = of_find_compatible_node(np, NULL, "cfi-flash");
	498	if (np2) {
4951896a TT	499	static struct property nor_status = {
	500	.name = "status",
	501	.value = "disabled",
	502	.length = sizeof("disabled"),
	503	};
	504
6269f258 TT	505	/*
	506	* prom_update_property() is called before
	507	* kmalloc() is available, so the 'new' object
	508	* should be allocated in the global area.
	509	* The easiest way is to do that is to
	510	* allocate one static local variable for each
	511	* call to this function.
	512	*/
	513	pr_info("p1022ds: disabling %s node",
	514	np2->full_name);
	515	prom_update_property(np2, &nor_status);
	516	of_node_put(np2);
	517	}
	518
	519	of_node_get(np);
	520	np2 = of_find_compatible_node(np, NULL,
	521	"fsl,elbc-fcm-nand");
	522	if (np2) {
	523	static struct property nand_status = {
	524	.name = "status",
	525	.value = "disabled",
	526	.length = sizeof("disabled"),
	527	};
	528
4951896a	529	pr_info("p1022ds: disabling %s node",
6269f258 TT	530	np2->full_name);
	531	prom_update_property(np2, &nand_status);
	532	of_node_put(np2);
4951896a	533	}
6269f258 TT	534
6269f258 TT	535	of_node_put(np);
4951896a TT	536	}
	537
	538	}
	539
2c184cd3 TT	540	#endif
2c184cd3 TT	541
30be4c96	542	mpc85xx_smp_init();
30be4c96 TT	543
30be4c96 TT	544	#ifdef CONFIG_SWIOTLB
a5cb82da	545	if ((memblock_end_of_DRAM() - 1) > max) {
30be4c96 TT	546	ppc_swiotlb_enable = 1;
	547	set_pci_dma_ops(&swiotlb_dma_ops);
	548	ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
	549	}
	550	#endif
	551
	552	pr_info("Freescale P1022 DS reference board\n");
	553	}
	554
8a95bc8d	555	machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);
30be4c96 TT	556
	557	machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
	558
	559	/*
	560	* Called very early, device-tree isn't unflattened
	561	*/
	562	static int __init p1022_ds_probe(void)
	563	{
	564	unsigned long root = of_get_flat_dt_root();
	565
	566	return of_flat_dt_is_compatible(root, "fsl,p1022ds");
	567	}
	568
	569	define_machine(p1022_ds) {
	570	.name = "P1022 DS",
	571	.probe = p1022_ds_probe,
	572	.setup_arch = p1022_ds_setup_arch,
	573	.init_IRQ = p1022_ds_pic_init,
	574	#ifdef CONFIG_PCI
	575	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	576	#endif
	577	.get_irq = mpic_get_irq,
	578	.restart = fsl_rstcr_restart,
	579	.calibrate_decr = generic_calibrate_decr,
	580	.progress = udbg_progress,
	581	};