[deliverable/linux.git] / arch / powerpc / platforms / 85xx / xes_mpc85xx.c

/*
 * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
 *
 * X-ES board-specific functionality
 *
 * Based on mpc85xx_ds code from Freescale Semiconductor, Inc.
 *
 * Author: Nate Case <ncase@xes-inc.com>
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/of_platform.h>

#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
#include <asm/udbg.h>
#include <asm/mpic.h>

#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include "smp.h"

#include "mpc85xx.h"

/* A few bit definitions needed for fixups on some boards */
#define MPC85xx_L2CTL_L2E		0x80000000 /* L2 enable */
#define MPC85xx_L2CTL_L2I		0x40000000 /* L2 flash invalidate */
#define MPC85xx_L2CTL_L2SIZ_MASK	0x30000000 /* L2 SRAM size (R/O) */

void __init xes_mpc85xx_pic_init(void)
{
	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
			0, 256, " OpenPIC  ");
	BUG_ON(mpic == NULL);
	mpic_init(mpic);
}

static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
{
	volatile uint32_t ctl, tmp;

	asm volatile("msync; isync");
	tmp = in_be32(l2_base);

	/*
	 * xMon may have enabled part of L2 as SRAM, so we need to set it
	 * up for all cache mode just to be safe.
	 */
	printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");

	ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
	if (of_machine_is_compatible("MPC8540") ||
	    of_machine_is_compatible("MPC8560"))
		/*
		 * Assume L2 SRAM is used fully for cache, so set
		 * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
		 */
		ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2;

	asm volatile("msync; isync");
	out_be32(l2_base, ctl);
	asm volatile("msync; isync");
}

static void xes_mpc85xx_fixups(void)
{
	struct device_node *np;
	int err;

	/*
	 * Legacy xMon firmware on some X-ES boards does not enable L2
	 * as cache.  We must ensure that they get enabled here.
	 */
	for_each_node_by_name(np, "l2-cache-controller") {
		struct resource r[2];
		void __iomem *l2_base;

		/* Only MPC8548, MPC8540, and MPC8560 boards are affected */
		if (!of_device_is_compatible(np,
				    "fsl,mpc8548-l2-cache-controller") &&
		    !of_device_is_compatible(np,
				    "fsl,mpc8540-l2-cache-controller") &&
		    !of_device_is_compatible(np,
				    "fsl,mpc8560-l2-cache-controller"))
			continue;

		err = of_address_to_resource(np, 0, &r[0]);
		if (err) {
			printk(KERN_WARNING "xes_mpc85xx: Could not get "
			       "resource for device tree node '%s'",
			       np->full_name);
			continue;
		}

		l2_base = ioremap(r[0].start, resource_size(&r[0]));

		xes_mpc85xx_configure_l2(l2_base);
	}
}

/*
 * Setup the architecture
 */
static void __init xes_mpc85xx_setup_arch(void)
{
	struct device_node *root;
	const char *model = "Unknown";

	root = of_find_node_by_path("/");
	if (root == NULL)
		return;

	model = of_get_property(root, "model", NULL);

	printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n",
	       model + strlen("xes,"));

	xes_mpc85xx_fixups();

	mpc85xx_smp_init();

	fsl_pci_assign_primary();
}

machine_arch_initcall(xes_mpc8572, mpc85xx_common_publish_devices);
machine_arch_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
machine_arch_initcall(xes_mpc8540, mpc85xx_common_publish_devices);

/*
 * Called very early, device-tree isn't unflattened
 */
static int __init xes_mpc8572_probe(void)
{
	return of_machine_is_compatible("xes,MPC8572");
}

static int __init xes_mpc8548_probe(void)
{
	return of_machine_is_compatible("xes,MPC8548");
}

static int __init xes_mpc8540_probe(void)
{
	return of_machine_is_compatible("xes,MPC8540");
}

define_machine(xes_mpc8572) {
	.name			= "X-ES MPC8572",
	.probe			= xes_mpc8572_probe,
	.setup_arch		= xes_mpc85xx_setup_arch,
	.init_IRQ		= xes_mpc85xx_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};

define_machine(xes_mpc8548) {
	.name			= "X-ES MPC8548",
	.probe			= xes_mpc8548_probe,
	.setup_arch		= xes_mpc85xx_setup_arch,
	.init_IRQ		= xes_mpc85xx_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};

define_machine(xes_mpc8540) {
	.name			= "X-ES MPC8540",
	.probe			= xes_mpc8540_probe,
	.setup_arch		= xes_mpc85xx_setup_arch,
	.init_IRQ		= xes_mpc85xx_pic_init,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
#endif
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};
Commit	Line	Data
3038acf9 NC	1	/*
	2	* Copyright (C) 2009 Extreme Engineering Solutions, Inc.
	3	*
	4	* X-ES board-specific functionality
	5	*
	6	* Based on mpc85xx_ds code from Freescale Semiconductor, Inc.
	7	*
	8	* Author: Nate Case <ncase@xes-inc.com>
	9	*
	10	* This is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/stddef.h>
	16	#include <linux/kernel.h>
	17	#include <linux/pci.h>
	18	#include <linux/kdev_t.h>
	19	#include <linux/delay.h>
	20	#include <linux/seq_file.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/of_platform.h>
	23
3038acf9 NC	24	#include <asm/time.h>
	25	#include <asm/machdep.h>
	26	#include <asm/pci-bridge.h>
	27	#include <mm/mmu_decl.h>
	28	#include <asm/prom.h>
	29	#include <asm/udbg.h>
	30	#include <asm/mpic.h>
	31
	32	#include <sysdev/fsl_soc.h>
	33	#include <sysdev/fsl_pci.h>
582d3e09	34	#include "smp.h"
3038acf9	35
543a07b1 DES	36	#include "mpc85xx.h"
543a07b1 DES	37
3038acf9 NC	38	/* A few bit definitions needed for fixups on some boards */
	39	#define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */
	40	#define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */
	41	#define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */
	42
	43	void __init xes_mpc85xx_pic_init(void)
	44	{
e55d7f73	45	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
3038acf9 NC	46	0, 256, " OpenPIC ");
3038acf9 NC	47	BUG_ON(mpic == NULL);
3038acf9 NC	48	mpic_init(mpic);
	49	}
	50
	51	static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
	52	{
	53	volatile uint32_t ctl, tmp;
	54
	55	asm volatile("msync; isync");
	56	tmp = in_be32(l2_base);
	57
	58	/*
	59	* xMon may have enabled part of L2 as SRAM, so we need to set it
	60	* up for all cache mode just to be safe.
	61	*/
	62	printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
	63
	64	ctl = MPC85xx_L2CTL_L2E \| MPC85xx_L2CTL_L2I;
71a157e8 GL	65	if (of_machine_is_compatible("MPC8540") \|\|
71a157e8 GL	66	of_machine_is_compatible("MPC8560"))
3038acf9 NC	67	/*
	68	* Assume L2 SRAM is used fully for cache, so set
	69	* L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
	70	*/
	71	ctl \|= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2;
	72
	73	asm volatile("msync; isync");
	74	out_be32(l2_base, ctl);
	75	asm volatile("msync; isync");
	76	}
	77
	78	static void xes_mpc85xx_fixups(void)
	79	{
	80	struct device_node *np;
	81	int err;
	82
	83	/*
	84	* Legacy xMon firmware on some X-ES boards does not enable L2
	85	* as cache. We must ensure that they get enabled here.
	86	*/
	87	for_each_node_by_name(np, "l2-cache-controller") {
	88	struct resource r[2];
	89	void __iomem *l2_base;
	90
	91	/* Only MPC8548, MPC8540, and MPC8560 boards are affected */
	92	if (!of_device_is_compatible(np,
	93	"fsl,mpc8548-l2-cache-controller") &&
	94	!of_device_is_compatible(np,
	95	"fsl,mpc8540-l2-cache-controller") &&
	96	!of_device_is_compatible(np,
	97	"fsl,mpc8560-l2-cache-controller"))
	98	continue;
	99
	100	err = of_address_to_resource(np, 0, &r[0]);
	101	if (err) {
	102	printk(KERN_WARNING "xes_mpc85xx: Could not get "
	103	"resource for device tree node '%s'",
	104	np->full_name);
	105	continue;
	106	}
	107
28f65c11	108	l2_base = ioremap(r[0].start, resource_size(&r[0]));
3038acf9 NC	109
	110	xes_mpc85xx_configure_l2(l2_base);
	111	}
	112	}
	113
3038acf9 NC	114	/*
	115	* Setup the architecture
	116	*/
3038acf9 NC	117	static void __init xes_mpc85xx_setup_arch(void)
3038acf9 NC	118	{
3038acf9 NC	119	struct device_node *root;
	120	const char *model = "Unknown";
	121
	122	root = of_find_node_by_path("/");
	123	if (root == NULL)
	124	return;
	125
	126	model = of_get_property(root, "model", NULL);
	127
	128	printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n",
	129	model + strlen("xes,"));
	130
	131	xes_mpc85xx_fixups();
	132
3038acf9	133	mpc85xx_smp_init();
905e75c4 JH	134
905e75c4 JH	135	fsl_pci_assign_primary();
3038acf9 NC	136	}
3038acf9 NC	137
905e75c4 JH	138	machine_arch_initcall(xes_mpc8572, mpc85xx_common_publish_devices);
	139	machine_arch_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
	140	machine_arch_initcall(xes_mpc8540, mpc85xx_common_publish_devices);
3038acf9 NC	141
	142	/*
	143	* Called very early, device-tree isn't unflattened
	144	*/
	145	static int __init xes_mpc8572_probe(void)
	146	{
56571384	147	return of_machine_is_compatible("xes,MPC8572");
3038acf9 NC	148	}
	149
	150	static int __init xes_mpc8548_probe(void)
	151	{
56571384	152	return of_machine_is_compatible("xes,MPC8548");
3038acf9 NC	153	}
	154
	155	static int __init xes_mpc8540_probe(void)
	156	{
56571384	157	return of_machine_is_compatible("xes,MPC8540");
3038acf9 NC	158	}
	159
	160	define_machine(xes_mpc8572) {
	161	.name = "X-ES MPC8572",
	162	.probe = xes_mpc8572_probe,
	163	.setup_arch = xes_mpc85xx_setup_arch,
	164	.init_IRQ = xes_mpc85xx_pic_init,
	165	#ifdef CONFIG_PCI
	166	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
48b16180	167	.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
3038acf9 NC	168	#endif
	169	.get_irq = mpic_get_irq,
	170	.restart = fsl_rstcr_restart,
	171	.calibrate_decr = generic_calibrate_decr,
	172	.progress = udbg_progress,
	173	};
	174
	175	define_machine(xes_mpc8548) {
	176	.name = "X-ES MPC8548",
	177	.probe = xes_mpc8548_probe,
	178	.setup_arch = xes_mpc85xx_setup_arch,
	179	.init_IRQ = xes_mpc85xx_pic_init,
	180	#ifdef CONFIG_PCI
	181	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
48b16180	182	.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
3038acf9 NC	183	#endif
	184	.get_irq = mpic_get_irq,
	185	.restart = fsl_rstcr_restart,
	186	.calibrate_decr = generic_calibrate_decr,
	187	.progress = udbg_progress,
	188	};
	189
	190	define_machine(xes_mpc8540) {
	191	.name = "X-ES MPC8540",
	192	.probe = xes_mpc8540_probe,
	193	.setup_arch = xes_mpc85xx_setup_arch,
	194	.init_IRQ = xes_mpc85xx_pic_init,
	195	#ifdef CONFIG_PCI
	196	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
48b16180	197	.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
3038acf9 NC	198	#endif
	199	.get_irq = mpic_get_irq,
	200	.restart = fsl_rstcr_restart,
	201	.calibrate_decr = generic_calibrate_decr,
	202	.progress = udbg_progress,
	203	};