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1 | /* |
2 | * GE Fanuc SBC310 board support | |
3 | * | |
4 | * Author: Martyn Welch <martyn.welch@gefanuc.com> | |
5 | * | |
6 | * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines) | |
14 | * Copyright 2006 Freescale Semiconductor Inc. | |
15 | * | |
16 | * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c | |
17 | */ | |
18 | ||
19 | #include <linux/stddef.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/kdev_t.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/seq_file.h> | |
25 | #include <linux/of_platform.h> | |
26 | ||
27 | #include <asm/system.h> | |
28 | #include <asm/time.h> | |
29 | #include <asm/machdep.h> | |
30 | #include <asm/pci-bridge.h> | |
31 | #include <asm/mpc86xx.h> | |
32 | #include <asm/prom.h> | |
33 | #include <mm/mmu_decl.h> | |
34 | #include <asm/udbg.h> | |
35 | ||
36 | #include <asm/mpic.h> | |
37 | ||
38 | #include <sysdev/fsl_pci.h> | |
39 | #include <sysdev/fsl_soc.h> | |
40 | ||
41 | #include "mpc86xx.h" | |
42 | #include "gef_pic.h" | |
43 | ||
44 | #undef DEBUG | |
45 | ||
46 | #ifdef DEBUG | |
47 | #define DBG (fmt...) do { printk(KERN_ERR "SBC310: " fmt); } while (0) | |
48 | #else | |
49 | #define DBG (fmt...) do { } while (0) | |
50 | #endif | |
51 | ||
52 | void __iomem *sbc310_regs; | |
53 | ||
54 | static void __init gef_sbc310_init_irq(void) | |
55 | { | |
56 | struct device_node *cascade_node = NULL; | |
57 | ||
58 | mpc86xx_init_irq(); | |
59 | ||
60 | /* | |
61 | * There is a simple interrupt handler in the main FPGA, this needs | |
62 | * to be cascaded into the MPIC | |
63 | */ | |
64 | cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic"); | |
65 | if (!cascade_node) { | |
66 | printk(KERN_WARNING "SBC310: No FPGA PIC\n"); | |
67 | return; | |
68 | } | |
69 | ||
70 | gef_pic_init(cascade_node); | |
71 | of_node_put(cascade_node); | |
72 | } | |
73 | ||
74 | static void __init gef_sbc310_setup_arch(void) | |
75 | { | |
76 | struct device_node *regs; | |
77 | #ifdef CONFIG_PCI | |
78 | struct device_node *np; | |
79 | ||
80 | for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") { | |
81 | fsl_add_bridge(np, 1); | |
82 | } | |
83 | #endif | |
84 | ||
85 | printk(KERN_INFO "GE Fanuc Intelligent Platforms SBC310 6U VPX SBC\n"); | |
86 | ||
87 | #ifdef CONFIG_SMP | |
88 | mpc86xx_smp_init(); | |
89 | #endif | |
90 | ||
91 | /* Remap basic board registers */ | |
92 | regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs"); | |
93 | if (regs) { | |
94 | sbc310_regs = of_iomap(regs, 0); | |
95 | if (sbc310_regs == NULL) | |
96 | printk(KERN_WARNING "Unable to map board registers\n"); | |
97 | of_node_put(regs); | |
98 | } | |
99 | } | |
100 | ||
101 | /* Return the PCB revision */ | |
102 | static unsigned int gef_sbc310_get_board_id(void) | |
103 | { | |
104 | unsigned int reg; | |
105 | ||
106 | reg = ioread32(sbc310_regs); | |
107 | return reg & 0xff; | |
108 | } | |
109 | ||
110 | /* Return the PCB revision */ | |
111 | static unsigned int gef_sbc310_get_pcb_rev(void) | |
112 | { | |
113 | unsigned int reg; | |
114 | ||
115 | reg = ioread32(sbc310_regs); | |
116 | return (reg >> 8) & 0xff; | |
117 | } | |
118 | ||
119 | /* Return the board (software) revision */ | |
120 | static unsigned int gef_sbc310_get_board_rev(void) | |
121 | { | |
122 | unsigned int reg; | |
123 | ||
124 | reg = ioread32(sbc310_regs); | |
125 | return (reg >> 16) & 0xff; | |
126 | } | |
127 | ||
128 | /* Return the FPGA revision */ | |
129 | static unsigned int gef_sbc310_get_fpga_rev(void) | |
130 | { | |
131 | unsigned int reg; | |
132 | ||
133 | reg = ioread32(sbc310_regs); | |
134 | return (reg >> 24) & 0xf; | |
135 | } | |
136 | ||
137 | static void gef_sbc310_show_cpuinfo(struct seq_file *m) | |
138 | { | |
139 | uint svid = mfspr(SPRN_SVR); | |
140 | ||
141 | seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n"); | |
142 | ||
143 | seq_printf(m, "Board ID\t: 0x%2.2x\n", gef_sbc310_get_board_id()); | |
144 | seq_printf(m, "Revision\t: %u%c\n", gef_sbc310_get_pcb_rev(), | |
145 | ('A' + gef_sbc310_get_board_rev() - 1)); | |
146 | seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc310_get_fpga_rev()); | |
147 | ||
148 | seq_printf(m, "SVR\t\t: 0x%x\n", svid); | |
149 | ||
150 | } | |
151 | ||
152 | static void __init gef_sbc310_nec_fixup(struct pci_dev *pdev) | |
153 | { | |
154 | unsigned int val; | |
155 | ||
01ce8ef5 MW |
156 | /* Do not do the fixup on other platforms! */ |
157 | if (!machine_is(gef_sbc310)) | |
158 | return; | |
159 | ||
bb2b66dc MW |
160 | printk(KERN_INFO "Running NEC uPD720101 Fixup\n"); |
161 | ||
162 | /* Ensure only ports 1 & 2 are enabled */ | |
163 | pci_read_config_dword(pdev, 0xe0, &val); | |
164 | pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x2); | |
165 | ||
166 | /* System clock is 48-MHz Oscillator and EHCI Enabled. */ | |
167 | pci_write_config_dword(pdev, 0xe4, 1 << 5); | |
168 | } | |
169 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, | |
170 | gef_sbc310_nec_fixup); | |
171 | ||
172 | /* | |
173 | * Called very early, device-tree isn't unflattened | |
174 | * | |
175 | * This function is called to determine whether the BSP is compatible with the | |
176 | * supplied device-tree, which is assumed to be the correct one for the actual | |
177 | * board. It is expected thati, in the future, a kernel may support multiple | |
178 | * boards. | |
179 | */ | |
180 | static int __init gef_sbc310_probe(void) | |
181 | { | |
182 | unsigned long root = of_get_flat_dt_root(); | |
183 | ||
184 | if (of_flat_dt_is_compatible(root, "gef,sbc310")) | |
185 | return 1; | |
186 | ||
187 | return 0; | |
188 | } | |
189 | ||
190 | static long __init mpc86xx_time_init(void) | |
191 | { | |
192 | unsigned int temp; | |
193 | ||
194 | /* Set the time base to zero */ | |
195 | mtspr(SPRN_TBWL, 0); | |
196 | mtspr(SPRN_TBWU, 0); | |
197 | ||
198 | temp = mfspr(SPRN_HID0); | |
199 | temp |= HID0_TBEN; | |
200 | mtspr(SPRN_HID0, temp); | |
201 | asm volatile("isync"); | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
206 | static __initdata struct of_device_id of_bus_ids[] = { | |
207 | { .compatible = "simple-bus", }, | |
d8bc55fb | 208 | { .compatible = "gianfar", }, |
bb2b66dc MW |
209 | {}, |
210 | }; | |
211 | ||
212 | static int __init declare_of_platform_devices(void) | |
213 | { | |
214 | printk(KERN_DEBUG "Probe platform devices\n"); | |
215 | of_platform_bus_probe(NULL, of_bus_ids, NULL); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | machine_device_initcall(gef_sbc310, declare_of_platform_devices); | |
220 | ||
221 | define_machine(gef_sbc310) { | |
222 | .name = "GE Fanuc SBC310", | |
223 | .probe = gef_sbc310_probe, | |
224 | .setup_arch = gef_sbc310_setup_arch, | |
225 | .init_IRQ = gef_sbc310_init_irq, | |
226 | .show_cpuinfo = gef_sbc310_show_cpuinfo, | |
227 | .get_irq = mpic_get_irq, | |
228 | .restart = fsl_rstcr_restart, | |
229 | .time_init = mpc86xx_time_init, | |
230 | .calibrate_decr = generic_calibrate_decr, | |
231 | .progress = udbg_progress, | |
232 | #ifdef CONFIG_PCI | |
233 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | |
234 | #endif | |
235 | }; |