[deliverable/linux.git] / arch / powerpc / platforms / 86xx / mpc8610_hpcd.c

/*
 * MPC8610 HPCD board specific routines
 *
 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
 * Recode: Jason Jin <jason.jin@freescale.com>
 *         York Sun <yorksun@freescale.com>
 *
 * Rewrite the interrupt routing. remove the 8259PIC support,
 * All the integrated device in ULI use sideband interrupt.
 *
 * Copyright 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/of.h>

#include <asm/system.h>
#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/mpc86xx.h>
#include <asm/prom.h>
#include <mm/mmu_decl.h>
#include <asm/udbg.h>

#include <asm/mpic.h>

#include <linux/of_platform.h>
#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>

#include "mpc86xx.h"

static unsigned char *pixis_bdcfg0, *pixis_arch;

static struct of_device_id __initdata mpc8610_ids[] = {
	{ .compatible = "fsl,mpc8610-immr", },
	{ .compatible = "simple-bus", },
	{}
};

static int __init mpc8610_declare_of_platform_devices(void)
{
	/* Without this call, the SSI device driver won't get probed. */
	of_platform_bus_probe(NULL, mpc8610_ids, NULL);

	return 0;
}
machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);

#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)

static u32 get_busfreq(void)
{
	struct device_node *node;

	u32 fs_busfreq = 0;
	node = of_find_node_by_type(NULL, "cpu");
	if (node) {
		unsigned int size;
		const unsigned int *prop =
			of_get_property(node, "bus-frequency", &size);
		if (prop)
			fs_busfreq = *prop;
		of_node_put(node);
	};
	return fs_busfreq;
}

unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
						int monitor_port)
{
	static const unsigned long pixelformat[][3] = {
		{0x88882317, 0x88083218, 0x65052119},
		{0x88883316, 0x88082219, 0x65053118},
	};
	unsigned int pix_fmt, arch_monitor;

	arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
		/* DVI port for board version 0x01 */

	if (bits_per_pixel == 32)
		pix_fmt = pixelformat[arch_monitor][0];
	else if (bits_per_pixel == 24)
		pix_fmt = pixelformat[arch_monitor][1];
	else if (bits_per_pixel == 16)
		pix_fmt = pixelformat[arch_monitor][2];
	else
		pix_fmt = pixelformat[1][0];

	return pix_fmt;
}

void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
{
	int i;
	if (monitor_port == 2) {		/* dual link LVDS */
		for (i = 0; i < 256*3; i++)
			gamma_table_base[i] = (gamma_table_base[i] << 2) |
					 ((gamma_table_base[i] >> 6) & 0x03);
	}
}

#define PX_BRDCFG0_DVISEL	(1 << 3)
#define PX_BRDCFG0_DLINK	(1 << 4)
#define PX_BRDCFG0_DIU_MASK	(PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)

void mpc8610hpcd_set_monitor_port(int monitor_port)
{
	static const u8 bdcfg[] = {
		PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK,
		PX_BRDCFG0_DLINK,
		0,
	};

	if (monitor_port < 3)
		clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
			     bdcfg[monitor_port]);
}

void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
{
	u32 __iomem *clkdvdr;
	u32 temp;
	/* variables for pixel clock calcs */
	ulong  bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
	ulong pixval;
	long err;
	int i;

	clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
	if (!clkdvdr) {
		printk(KERN_ERR "Err: can't map clock divider register!\n");
		return;
	}

	/* Pixel Clock configuration */
	pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
	speed_ccb = get_busfreq();

	/* Calculate the pixel clock with the smallest error */
	/* calculate the following in steps to avoid overflow */
	pr_debug("DIU pixclock in ps - %d\n", pixclock);
	temp = 1000000000/pixclock;
	temp *= 1000;
	pixclock = temp;
	pr_debug("DIU pixclock freq - %u\n", pixclock);

	temp = pixclock * 5 / 100;
	pr_debug("deviation = %d\n", temp);
	minpixclock = pixclock - temp;
	maxpixclock = pixclock + temp;
	pr_debug("DIU minpixclock - %lu\n", minpixclock);
	pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
	pixval = speed_ccb/pixclock;
	pr_debug("DIU pixval = %lu\n", pixval);

	err = 100000000;
	bestval = pixval;
	pr_debug("DIU bestval = %lu\n", bestval);

	bestfreq = 0;
	for (i = -1; i <= 1; i++) {
		temp = speed_ccb / ((pixval+i) + 1);
		pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
							i, pixval, temp);
		if ((temp < minpixclock) || (temp > maxpixclock))
			pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
				minpixclock, maxpixclock);
		else if (abs(temp - pixclock) < err) {
		  pr_debug("Entered the else if block %d\n", i);
			err = abs(temp - pixclock);
			bestval = pixval+i;
			bestfreq = temp;
		}
	}

	pr_debug("DIU chose = %lx\n", bestval);
	pr_debug("DIU error = %ld\n NomPixClk ", err);
	pr_debug("DIU: Best Freq = %lx\n", bestfreq);
	/* Modify PXCLK in GUTS CLKDVDR */
	pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
	temp = (*clkdvdr) & 0x2000FFFF;
	*clkdvdr = temp;		/* turn off clock */
	*clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
	pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
	iounmap(clkdvdr);
}

ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
{
	return snprintf(buf, PAGE_SIZE,
			"%c0 - DVI\n"
			"%c1 - Single link LVDS\n"
			"%c2 - Dual link LVDS\n",
			monitor_port == 0 ? '*' : ' ',
			monitor_port == 1 ? '*' : ' ',
			monitor_port == 2 ? '*' : ' ');
}

int mpc8610hpcd_set_sysfs_monitor_port(int val)
{
	return val < 3 ? val : 0;
}

#endif

static void __init mpc86xx_hpcd_setup_arch(void)
{
	struct resource r;
	struct device_node *np;
	unsigned char *pixis;

	if (ppc_md.progress)
		ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);

#ifdef CONFIG_PCI
	for_each_node_by_type(np, "pci") {
		if (of_device_is_compatible(np, "fsl,mpc8610-pci")
		    || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
			struct resource rsrc;
			of_address_to_resource(np, 0, &rsrc);
			if ((rsrc.start & 0xfffff) == 0xa000)
				fsl_add_bridge(np, 1);
			else
				fsl_add_bridge(np, 0);
		}
        }
#endif
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
	preallocate_diu_videomemory();
	diu_ops.get_pixel_format	= mpc8610hpcd_get_pixel_format;
	diu_ops.set_gamma_table		= mpc8610hpcd_set_gamma_table;
	diu_ops.set_monitor_port	= mpc8610hpcd_set_monitor_port;
	diu_ops.set_pixel_clock		= mpc8610hpcd_set_pixel_clock;
	diu_ops.show_monitor_port	= mpc8610hpcd_show_monitor_port;
	diu_ops.set_sysfs_monitor_port	= mpc8610hpcd_set_sysfs_monitor_port;
#endif

	np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
	if (np) {
		of_address_to_resource(np, 0, &r);
		of_node_put(np);
		pixis = ioremap(r.start, 32);
		if (!pixis) {
			printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
			return;
		}
		pixis_bdcfg0 = pixis + 8;
		pixis_arch = pixis + 1;
	} else
		printk(KERN_ERR "Err: "
				"can't find device node 'fsl,fpga-pixis'\n");

	printk("MPC86xx HPCD board from Freescale Semiconductor\n");
}

/*
 * Called very early, device-tree isn't unflattened
 */
static int __init mpc86xx_hpcd_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
		return 1;	/* Looks good */

	return 0;
}

static long __init mpc86xx_time_init(void)
{
	unsigned int temp;

	/* Set the time base to zero */
	mtspr(SPRN_TBWL, 0);
	mtspr(SPRN_TBWU, 0);

	temp = mfspr(SPRN_HID0);
	temp |= HID0_TBEN;
	mtspr(SPRN_HID0, temp);
	asm volatile("isync");

	return 0;
}

define_machine(mpc86xx_hpcd) {
	.name			= "MPC86xx HPCD",
	.probe			= mpc86xx_hpcd_probe,
	.setup_arch		= mpc86xx_hpcd_setup_arch,
	.init_IRQ		= mpc86xx_init_irq,
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.time_init		= mpc86xx_time_init,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
};
Commit	Line	Data
0e65bfe3 XX	1	/*
	2	* MPC8610 HPCD board specific routines
	3	*
	4	* Initial author: Xianghua Xiao <x.xiao@freescale.com>
	5	* Recode: Jason Jin <jason.jin@freescale.com>
6f90a8bd	6	* York Sun <yorksun@freescale.com>
0e65bfe3 XX	7	*
	8	* Rewrite the interrupt routing. remove the 8259PIC support,
	9	* All the integrated device in ULI use sideband interrupt.
	10	*
6f90a8bd	11	* Copyright 2008 Freescale Semiconductor Inc.
0e65bfe3 XX	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License as published by the
	15	* Free Software Foundation; either version 2 of the License, or (at your
	16	* option) any later version.
	17	*/
	18
	19	#include <linux/stddef.h>
	20	#include <linux/kernel.h>
	21	#include <linux/pci.h>
	22	#include <linux/kdev_t.h>
	23	#include <linux/delay.h>
	24	#include <linux/seq_file.h>
	25	#include <linux/of.h>
	26
	27	#include <asm/system.h>
	28	#include <asm/time.h>
	29	#include <asm/machdep.h>
	30	#include <asm/pci-bridge.h>
	31	#include <asm/mpc86xx.h>
	32	#include <asm/prom.h>
	33	#include <mm/mmu_decl.h>
	34	#include <asm/udbg.h>
	35
	36	#include <asm/mpic.h>
	37
c7d24a2d	38	#include <linux/of_platform.h>
0e65bfe3 XX	39	#include <sysdev/fsl_pci.h>
	40	#include <sysdev/fsl_soc.h>
	41
98384c6c KG	42	#include "mpc86xx.h"
98384c6c KG	43
6f90a8bd YS	44	static unsigned char pixis_bdcfg0, pixis_arch;
6f90a8bd YS	45
c7d24a2d TT	46	static struct of_device_id __initdata mpc8610_ids[] = {
c7d24a2d TT	47	{ .compatible = "fsl,mpc8610-immr", },
34b4a873	48	{ .compatible = "simple-bus", },
c7d24a2d TT	49	{}
	50	};
	51
	52	static int __init mpc8610_declare_of_platform_devices(void)
	53	{
	54	/* Without this call, the SSI device driver won't get probed. */
	55	of_platform_bus_probe(NULL, mpc8610_ids, NULL);
	56
	57	return 0;
	58	}
	59	machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
	60
6f90a8bd YS	61	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)
	62
	63	static u32 get_busfreq(void)
0e65bfe3	64	{
6f90a8bd YS	65	struct device_node *node;
	66
	67	u32 fs_busfreq = 0;
	68	node = of_find_node_by_type(NULL, "cpu");
	69	if (node) {
	70	unsigned int size;
	71	const unsigned int *prop =
	72	of_get_property(node, "bus-frequency", &size);
	73	if (prop)
	74	fs_busfreq = *prop;
	75	of_node_put(node);
	76	};
	77	return fs_busfreq;
	78	}
	79
	80	unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
	81	int monitor_port)
	82	{
	83	static const unsigned long pixelformat[][3] = {
	84	{0x88882317, 0x88083218, 0x65052119},
	85	{0x88883316, 0x88082219, 0x65053118},
	86	};
	87	unsigned int pix_fmt, arch_monitor;
	88
	89	arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
	90	/* DVI port for board version 0x01 */
	91
	92	if (bits_per_pixel == 32)
	93	pix_fmt = pixelformat[arch_monitor][0];
	94	else if (bits_per_pixel == 24)
	95	pix_fmt = pixelformat[arch_monitor][1];
	96	else if (bits_per_pixel == 16)
	97	pix_fmt = pixelformat[arch_monitor][2];
	98	else
	99	pix_fmt = pixelformat[1][0];
	100
	101	return pix_fmt;
	102	}
	103
	104	void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
	105	{
	106	int i;
	107	if (monitor_port == 2) { /* dual link LVDS */
	108	for (i = 0; i < 256*3; i++)
	109	gamma_table_base[i] = (gamma_table_base[i] << 2) \|
	110	((gamma_table_base[i] >> 6) & 0x03);
	111	}
	112	}
	113
f637ef8e AV	114	#define PX_BRDCFG0_DVISEL (1 << 3)
	115	#define PX_BRDCFG0_DLINK (1 << 4)
	116	#define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL \| PX_BRDCFG0_DLINK)
	117
6f90a8bd YS	118	void mpc8610hpcd_set_monitor_port(int monitor_port)
6f90a8bd YS	119	{
f637ef8e AV	120	static const u8 bdcfg[] = {
	121	PX_BRDCFG0_DVISEL \| PX_BRDCFG0_DLINK,
	122	PX_BRDCFG0_DLINK,
	123	0,
	124	};
	125
6f90a8bd	126	if (monitor_port < 3)
f637ef8e AV	127	clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
f637ef8e AV	128	bdcfg[monitor_port]);
6f90a8bd YS	129	}
	130
	131	void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
	132	{
	133	u32 __iomem *clkdvdr;
	134	u32 temp;
	135	/* variables for pixel clock calcs */
	136	ulong bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
	137	ulong pixval;
	138	long err;
	139	int i;
	140
	141	clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
	142	if (!clkdvdr) {
	143	printk(KERN_ERR "Err: can't map clock divider register!\n");
	144	return;
	145	}
	146
	147	/* Pixel Clock configuration */
	148	pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
	149	speed_ccb = get_busfreq();
	150
	151	/* Calculate the pixel clock with the smallest error */
	152	/* calculate the following in steps to avoid overflow */
	153	pr_debug("DIU pixclock in ps - %d\n", pixclock);
	154	temp = 1000000000/pixclock;
	155	temp *= 1000;
	156	pixclock = temp;
	157	pr_debug("DIU pixclock freq - %u\n", pixclock);
	158
	159	temp = pixclock * 5 / 100;
	160	pr_debug("deviation = %d\n", temp);
	161	minpixclock = pixclock - temp;
	162	maxpixclock = pixclock + temp;
	163	pr_debug("DIU minpixclock - %lu\n", minpixclock);
	164	pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
	165	pixval = speed_ccb/pixclock;
	166	pr_debug("DIU pixval = %lu\n", pixval);
	167
	168	err = 100000000;
	169	bestval = pixval;
	170	pr_debug("DIU bestval = %lu\n", bestval);
	171
	172	bestfreq = 0;
	173	for (i = -1; i <= 1; i++) {
	174	temp = speed_ccb / ((pixval+i) + 1);
	175	pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
	176	i, pixval, temp);
	177	if ((temp < minpixclock) \|\| (temp > maxpixclock))
	178	pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
	179	minpixclock, maxpixclock);
	180	else if (abs(temp - pixclock) < err) {
	181	pr_debug("Entered the else if block %d\n", i);
	182	err = abs(temp - pixclock);
	183	bestval = pixval+i;
	184	bestfreq = temp;
	185	}
	186	}
	187
	188	pr_debug("DIU chose = %lx\n", bestval);
	189	pr_debug("DIU error = %ld\n NomPixClk ", err);
	190	pr_debug("DIU: Best Freq = %lx\n", bestfreq);
	191	/* Modify PXCLK in GUTS CLKDVDR */
	192	pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
193	temp = (*clkdvdr) & 0x2000FFFF;
194	clkdvdr = temp; / turn off clock */
195	*clkdvdr = temp \| 0x80000000 \| (((bestval) & 0x1F) << 16);
196	pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
197	iounmap(clkdvdr);
198	}
199
200	ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
201	{
202	return snprintf(buf, PAGE_SIZE,
203	"%c0 - DVI\n"
204	"%c1 - Single link LVDS\n"
205	"%c2 - Dual link LVDS\n",
206	monitor_port == 0 ? '*' : ' ',
207	monitor_port == 1 ? '*' : ' ',
208	monitor_port == 2 ? '*' : ' ');
209	}
210
211	int mpc8610hpcd_set_sysfs_monitor_port(int val)
212	{
213	return val < 3 ? val : 0;
214	}
215
0e65bfe3	216	#endif
6f90a8bd YS	217
	218	static void __init mpc86xx_hpcd_setup_arch(void)
	219	{
	220	struct resource r;
	221	struct device_node *np;
	222	unsigned char *pixis;
	223
0e65bfe3 XX	224	if (ppc_md.progress)
	225	ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
	226
	227	#ifdef CONFIG_PCI
	228	for_each_node_by_type(np, "pci") {
	229	if (of_device_is_compatible(np, "fsl,mpc8610-pci")
	230	\|\| of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
	231	struct resource rsrc;
	232	of_address_to_resource(np, 0, &rsrc);
	233	if ((rsrc.start & 0xfffff) == 0xa000)
	234	fsl_add_bridge(np, 1);
	235	else
	236	fsl_add_bridge(np, 0);
	237	}
	238	}
	239	#endif
6f90a8bd YS	240	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)
	241	preallocate_diu_videomemory();
	242	diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
	243	diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
	244	diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
	245	diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
	246	diu_ops.show_monitor_port = mpc8610hpcd_show_monitor_port;
	247	diu_ops.set_sysfs_monitor_port = mpc8610hpcd_set_sysfs_monitor_port;
	248	#endif
	249
	250	np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
	251	if (np) {
	252	of_address_to_resource(np, 0, &r);
	253	of_node_put(np);
	254	pixis = ioremap(r.start, 32);
	255	if (!pixis) {
	256	printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
	257	return;
	258	}
	259	pixis_bdcfg0 = pixis + 8;
	260	pixis_arch = pixis + 1;
	261	} else
	262	printk(KERN_ERR "Err: "
	263	"can't find device node 'fsl,fpga-pixis'\n");
0e65bfe3 XX	264
	265	printk("MPC86xx HPCD board from Freescale Semiconductor\n");
	266	}
	267
	268	/*
	269	* Called very early, device-tree isn't unflattened
	270	*/
	271	static int __init mpc86xx_hpcd_probe(void)
	272	{
	273	unsigned long root = of_get_flat_dt_root();
	274
	275	if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
	276	return 1; /* Looks good */
	277
	278	return 0;
	279	}
	280
6f90a8bd	281	static long __init mpc86xx_time_init(void)
0e65bfe3 XX	282	{
	283	unsigned int temp;
	284
	285	/* Set the time base to zero */
	286	mtspr(SPRN_TBWL, 0);
	287	mtspr(SPRN_TBWU, 0);
	288
	289	temp = mfspr(SPRN_HID0);
	290	temp \|= HID0_TBEN;
	291	mtspr(SPRN_HID0, temp);
	292	asm volatile("isync");
	293
	294	return 0;
	295	}
	296
	297	define_machine(mpc86xx_hpcd) {
	298	.name = "MPC86xx HPCD",
	299	.probe = mpc86xx_hpcd_probe,
	300	.setup_arch = mpc86xx_hpcd_setup_arch,
98384c6c	301	.init_IRQ = mpc86xx_init_irq,
0e65bfe3	302	.get_irq = mpic_get_irq,
e1c1575f	303	.restart = fsl_rstcr_restart,
0e65bfe3 XX	304	.time_init = mpc86xx_time_init,
	305	.calibrate_decr = generic_calibrate_decr,
	306	.progress = udbg_progress,
	307	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	308	};