[deliverable/linux.git] / arch / powerpc / platforms / 86xx / mpc8610_hpcd.c

/*
 * MPC8610 HPCD board specific routines
 *
 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
 * Recode: Jason Jin <jason.jin@freescale.com>
 *         York Sun <yorksun@freescale.com>
 *
 * Rewrite the interrupt routing. remove the 8259PIC support,
 * All the integrated device in ULI use sideband interrupt.
 *
 * Copyright 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/of.h>

#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/prom.h>
#include <mm/mmu_decl.h>
#include <asm/udbg.h>

#include <asm/mpic.h>

#include <linux/of_platform.h>
#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/simple_gpio.h>
#include <asm/fsl_guts.h>

#include "mpc86xx.h"

static struct device_node *pixis_node;
static unsigned char *pixis_bdcfg0, *pixis_arch;

/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
#define CLKDVDR_PXCKEN		0x80000000
#define CLKDVDR_PXCKINV		0x10000000
#define CLKDVDR_PXCKDLY		0x06000000
#define CLKDVDR_PXCLK_MASK	0x001F0000

#ifdef CONFIG_SUSPEND
static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
{
	pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
	return IRQ_HANDLED;
}

static void __init mpc8610_suspend_init(void)
{
	int irq;
	int ret;

	if (!pixis_node)
		return;

	irq = irq_of_parse_and_map(pixis_node, 0);
	if (!irq) {
		pr_err("%s: can't map pixis event IRQ.\n", __func__);
		return;
	}

	ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL);
	if (ret) {
		pr_err("%s: can't request pixis event IRQ: %d\n",
		       __func__, ret);
		irq_dispose_mapping(irq);
	}

	enable_irq_wake(irq);
}
#else
static inline void mpc8610_suspend_init(void) { }
#endif /* CONFIG_SUSPEND */

static const struct of_device_id mpc8610_ids[] __initconst = {
	{ .compatible = "fsl,mpc8610-immr", },
	{ .compatible = "fsl,mpc8610-guts", },
	{ .compatible = "simple-bus", },
	/* So that the DMA channel nodes can be probed individually: */
	{ .compatible = "fsl,eloplus-dma", },
	/* PCI controllers */
	{ .compatible = "fsl,mpc8610-pci", },
	{ .compatible = "fsl,mpc8641-pcie", },
	{}
};

static int __init mpc8610_declare_of_platform_devices(void)
{
	/* Firstly, register PIXIS GPIOs. */
	simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");

	/* Enable wakeup on PIXIS' event IRQ. */
	mpc8610_suspend_init();

	/* Without this call, the SSI device driver won't get probed. */
	of_platform_bus_probe(NULL, mpc8610_ids, NULL);

	return 0;
}
machine_arch_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);

#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)

/*
 * DIU Area Descriptor
 *
 * The MPC8610 reference manual shows the bits of the AD register in
 * little-endian order, which causes the BLUE_C field to be split into two
 * parts. To simplify the definition of the MAKE_AD() macro, we define the
 * fields in big-endian order and byte-swap the result.
 *
 * So even though the registers don't look like they're in the
 * same bit positions as they are on the P1022, the same value is written to
 * the AD register on the MPC8610 and on the P1022.
 */
#define AD_BYTE_F		0x10000000
#define AD_ALPHA_C_MASK		0x0E000000
#define AD_ALPHA_C_SHIFT	25
#define AD_BLUE_C_MASK		0x01800000
#define AD_BLUE_C_SHIFT		23
#define AD_GREEN_C_MASK		0x00600000
#define AD_GREEN_C_SHIFT	21
#define AD_RED_C_MASK		0x00180000
#define AD_RED_C_SHIFT		19
#define AD_PALETTE		0x00040000
#define AD_PIXEL_S_MASK		0x00030000
#define AD_PIXEL_S_SHIFT	16
#define AD_COMP_3_MASK		0x0000F000
#define AD_COMP_3_SHIFT		12
#define AD_COMP_2_MASK		0x00000F00
#define AD_COMP_2_SHIFT		8
#define AD_COMP_1_MASK		0x000000F0
#define AD_COMP_1_SHIFT		4
#define AD_COMP_0_MASK		0x0000000F
#define AD_COMP_0_SHIFT		0

#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
	cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
	(blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
	(red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
	(c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
	(c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))

u32 mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port,
				 unsigned int bits_per_pixel)
{
	static const u32 pixelformat[][3] = {
		{
			MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
			MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
			MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0)
		},
		{
			MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8),
			MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0),
			MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0)
		},
	};
	unsigned int arch_monitor;

	/* The DVI port is mis-wired on revision 1 of this board. */
	arch_monitor =
		((*pixis_arch == 0x01) && (port == FSL_DIU_PORT_DVI)) ? 0 : 1;

	switch (bits_per_pixel) {
	case 32:
		return pixelformat[arch_monitor][0];
	case 24:
		return pixelformat[arch_monitor][1];
	case 16:
		return pixelformat[arch_monitor][2];
	default:
		pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
		return 0;
	}
}

void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port,
				 char *gamma_table_base)
{
	int i;
	if (port == FSL_DIU_PORT_DLVDS) {
		for (i = 0; i < 256*3; i++)
			gamma_table_base[i] = (gamma_table_base[i] << 2) |
					 ((gamma_table_base[i] >> 6) & 0x03);
	}
}

#define PX_BRDCFG0_DVISEL	(1 << 3)
#define PX_BRDCFG0_DLINK	(1 << 4)
#define PX_BRDCFG0_DIU_MASK	(PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)

void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)
{
	switch (port) {
	case FSL_DIU_PORT_DVI:
		clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
			     PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK);
		break;
	case FSL_DIU_PORT_LVDS:
		clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
			     PX_BRDCFG0_DLINK);
		break;
	case FSL_DIU_PORT_DLVDS:
		clrbits8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK);
		break;
	}
}

/**
 * mpc8610hpcd_set_pixel_clock: program the DIU's clock
 *
 * @pixclock: the wavelength, in picoseconds, of the clock
 */
void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
{
	struct device_node *guts_np = NULL;
	struct ccsr_guts __iomem *guts;
	unsigned long freq;
	u64 temp;
	u32 pxclk;

	/* Map the global utilities registers. */
	guts_np = of_find_compatible_node(NULL, NULL, "fsl,mpc8610-guts");
	if (!guts_np) {
		pr_err("mpc8610hpcd: missing global utilities device node\n");
		return;
	}

	guts = of_iomap(guts_np, 0);
	of_node_put(guts_np);
	if (!guts) {
		pr_err("mpc8610hpcd: could not map global utilities device\n");
		return;
	}

	/* Convert pixclock from a wavelength to a frequency */
	temp = 1000000000000ULL;
	do_div(temp, pixclock);
	freq = temp;

	/*
	 * 'pxclk' is the ratio of the platform clock to the pixel clock.
	 * On the MPC8610, the value programmed into CLKDVDR is the ratio
	 * minus one.  The valid range of values is 2-31.
	 */
	pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq) - 1;
	pxclk = clamp_t(u32, pxclk, 2, 31);

	/* Disable the pixel clock, and set it to non-inverted and no delay */
	clrbits32(&guts->clkdvdr,
		  CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);

	/* Enable the clock and set the pxclk */
	setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));

	iounmap(guts);
}

enum fsl_diu_monitor_port
mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
{
	return port;
}

#endif

static void __init mpc86xx_hpcd_setup_arch(void)
{
	struct resource r;
	unsigned char *pixis;

	if (ppc_md.progress)
		ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);

	fsl_pci_assign_primary();

#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
	diu_ops.get_pixel_format	= mpc8610hpcd_get_pixel_format;
	diu_ops.set_gamma_table		= mpc8610hpcd_set_gamma_table;
	diu_ops.set_monitor_port	= mpc8610hpcd_set_monitor_port;
	diu_ops.set_pixel_clock		= mpc8610hpcd_set_pixel_clock;
	diu_ops.valid_monitor_port	= mpc8610hpcd_valid_monitor_port;
#endif

	pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
	if (pixis_node) {
		of_address_to_resource(pixis_node, 0, &r);
		of_node_put(pixis_node);
		pixis = ioremap(r.start, 32);
		if (!pixis) {
			printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
			return;
		}
		pixis_bdcfg0 = pixis + 8;
		pixis_arch = pixis + 1;
	} else
		printk(KERN_ERR "Err: "
				"can't find device node 'fsl,fpga-pixis'\n");

	printk("MPC86xx HPCD board from Freescale Semiconductor\n");
}

/*
 * Called very early, device-tree isn't unflattened
 */
static int __init mpc86xx_hpcd_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
		return 1;	/* Looks good */

	return 0;
}

static long __init mpc86xx_time_init(void)
{
	unsigned int temp;

	/* Set the time base to zero */
	mtspr(SPRN_TBWL, 0);
	mtspr(SPRN_TBWU, 0);

	temp = mfspr(SPRN_HID0);
	temp |= HID0_TBEN;
	mtspr(SPRN_HID0, temp);
	asm volatile("isync");

	return 0;
}

define_machine(mpc86xx_hpcd) {
	.name			= "MPC86xx HPCD",
	.probe			= mpc86xx_hpcd_probe,
	.setup_arch		= mpc86xx_hpcd_setup_arch,
	.init_IRQ		= mpc86xx_init_irq,
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.time_init		= mpc86xx_time_init,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
};
Commit	Line	Data
0e65bfe3 XX	1	/*
	2	* MPC8610 HPCD board specific routines
	3	*
	4	* Initial author: Xianghua Xiao <x.xiao@freescale.com>
	5	* Recode: Jason Jin <jason.jin@freescale.com>
6f90a8bd	6	* York Sun <yorksun@freescale.com>
0e65bfe3 XX	7	*
	8	* Rewrite the interrupt routing. remove the 8259PIC support,
	9	* All the integrated device in ULI use sideband interrupt.
	10	*
6f90a8bd	11	* Copyright 2008 Freescale Semiconductor Inc.
0e65bfe3 XX	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License as published by the
	15	* Free Software Foundation; either version 2 of the License, or (at your
	16	* option) any later version.
	17	*/
	18
	19	#include <linux/stddef.h>
	20	#include <linux/kernel.h>
	21	#include <linux/pci.h>
8c68e2f7	22	#include <linux/interrupt.h>
0e65bfe3 XX	23	#include <linux/kdev_t.h>
	24	#include <linux/delay.h>
	25	#include <linux/seq_file.h>
	26	#include <linux/of.h>
	27
0e65bfe3 XX	28	#include <asm/time.h>
	29	#include <asm/machdep.h>
	30	#include <asm/pci-bridge.h>
0e65bfe3 XX	31	#include <asm/prom.h>
	32	#include <mm/mmu_decl.h>
	33	#include <asm/udbg.h>
	34
	35	#include <asm/mpic.h>
	36
c7d24a2d	37	#include <linux/of_platform.h>
0e65bfe3 XX	38	#include <sysdev/fsl_pci.h>
0e65bfe3 XX	39	#include <sysdev/fsl_soc.h>
d2998c2c	40	#include <sysdev/simple_gpio.h>
c8bfa77b	41	#include <asm/fsl_guts.h>
0e65bfe3	42
98384c6c KG	43	#include "mpc86xx.h"
98384c6c KG	44
8c68e2f7	45	static struct device_node *pixis_node;
6f90a8bd YS	46	static unsigned char pixis_bdcfg0, pixis_arch;
6f90a8bd YS	47
c8bfa77b TT	48	/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
	49	#define CLKDVDR_PXCKEN 0x80000000
	50	#define CLKDVDR_PXCKINV 0x10000000
	51	#define CLKDVDR_PXCKDLY 0x06000000
	52	#define CLKDVDR_PXCLK_MASK 0x001F0000
	53
8c68e2f7 AV	54	#ifdef CONFIG_SUSPEND
	55	static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
	56	{
	57	pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
	58	return IRQ_HANDLED;
	59	}
	60
	61	static void __init mpc8610_suspend_init(void)
	62	{
	63	int irq;
	64	int ret;
	65
	66	if (!pixis_node)
	67	return;
	68
	69	irq = irq_of_parse_and_map(pixis_node, 0);
	70	if (!irq) {
	71	pr_err("%s: can't map pixis event IRQ.\n", __func__);
	72	return;
	73	}
	74
e0be2c21	75	ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL);
8c68e2f7 AV	76	if (ret) {
	77	pr_err("%s: can't request pixis event IRQ: %d\n",
	78	__func__, ret);
	79	irq_dispose_mapping(irq);
	80	}
	81
	82	enable_irq_wake(irq);
	83	}
	84	#else
	85	static inline void mpc8610_suspend_init(void) { }
	86	#endif /* CONFIG_SUSPEND */
	87
ce6d73c9	88	static const struct of_device_id mpc8610_ids[] __initconst = {
c7d24a2d	89	{ .compatible = "fsl,mpc8610-immr", },
8c68e2f7	90	{ .compatible = "fsl,mpc8610-guts", },
34b4a873	91	{ .compatible = "simple-bus", },
4c5ddd52 TT	92	/* So that the DMA channel nodes can be probed individually: */
4c5ddd52 TT	93	{ .compatible = "fsl,eloplus-dma", },
905e75c4 JH	94	/* PCI controllers */
	95	{ .compatible = "fsl,mpc8610-pci", },
	96	{ .compatible = "fsl,mpc8641-pcie", },
c7d24a2d TT	97	{}
	98	};
	99
	100	static int __init mpc8610_declare_of_platform_devices(void)
	101	{
d2998c2c AV	102	/* Firstly, register PIXIS GPIOs. */
	103	simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");
	104
8c68e2f7 AV	105	/* Enable wakeup on PIXIS' event IRQ. */
	106	mpc8610_suspend_init();
	107
c7d24a2d TT	108	/* Without this call, the SSI device driver won't get probed. */
	109	of_platform_bus_probe(NULL, mpc8610_ids, NULL);
	110
	111	return 0;
	112	}
905e75c4	113	machine_arch_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
c7d24a2d	114
6f90a8bd YS	115	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)
6f90a8bd YS	116
f46dad27 TT	117	/*
	118	* DIU Area Descriptor
	119	*
	120	* The MPC8610 reference manual shows the bits of the AD register in
	121	* little-endian order, which causes the BLUE_C field to be split into two
	122	* parts. To simplify the definition of the MAKE_AD() macro, we define the
	123	* fields in big-endian order and byte-swap the result.
	124	*
	125	* So even though the registers don't look like they're in the
	126	* same bit positions as they are on the P1022, the same value is written to
	127	* the AD register on the MPC8610 and on the P1022.
	128	*/
	129	#define AD_BYTE_F 0x10000000
	130	#define AD_ALPHA_C_MASK 0x0E000000
	131	#define AD_ALPHA_C_SHIFT 25
	132	#define AD_BLUE_C_MASK 0x01800000
	133	#define AD_BLUE_C_SHIFT 23
	134	#define AD_GREEN_C_MASK 0x00600000
	135	#define AD_GREEN_C_SHIFT 21
	136	#define AD_RED_C_MASK 0x00180000
	137	#define AD_RED_C_SHIFT 19
	138	#define AD_PALETTE 0x00040000
	139	#define AD_PIXEL_S_MASK 0x00030000
	140	#define AD_PIXEL_S_SHIFT 16
	141	#define AD_COMP_3_MASK 0x0000F000
	142	#define AD_COMP_3_SHIFT 12
	143	#define AD_COMP_2_MASK 0x00000F00
	144	#define AD_COMP_2_SHIFT 8
	145	#define AD_COMP_1_MASK 0x000000F0
	146	#define AD_COMP_1_SHIFT 4
	147	#define AD_COMP_0_MASK 0x0000000F
	148	#define AD_COMP_0_SHIFT 0
	149
	150	#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
	151	cpu_to_le32(AD_BYTE_F \| (alpha << AD_ALPHA_C_SHIFT) \| \
	152	(blue << AD_BLUE_C_SHIFT) \| (green << AD_GREEN_C_SHIFT) \| \
	153	(red << AD_RED_C_SHIFT) \| (c3 << AD_COMP_3_SHIFT) \| \
	154	(c2 << AD_COMP_2_SHIFT) \| (c1 << AD_COMP_1_SHIFT) \| \
	155	(c0 << AD_COMP_0_SHIFT) \| (size << AD_PIXEL_S_SHIFT))
6f90a8bd	156
7653aaab TT	157	u32 mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port,
7653aaab TT	158	unsigned int bits_per_pixel)
6f90a8bd	159	{
7653aaab	160	static const u32 pixelformat[][3] = {
f46dad27 TT	161	{
	162	MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
	163	MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
	164	MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0)
	165	},
	166	{
	167	MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8),
	168	MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0),
	169	MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0)
	170	},
6f90a8bd	171	};
f46dad27	172	unsigned int arch_monitor;
6f90a8bd	173
f46dad27	174	/* The DVI port is mis-wired on revision 1 of this board. */
7653aaab TT	175	arch_monitor =
7653aaab TT	176	((*pixis_arch == 0x01) && (port == FSL_DIU_PORT_DVI)) ? 0 : 1;
f46dad27 TT	177
	178	switch (bits_per_pixel) {
	179	case 32:
	180	return pixelformat[arch_monitor][0];
	181	case 24:
	182	return pixelformat[arch_monitor][1];
	183	case 16:
	184	return pixelformat[arch_monitor][2];
	185	default:
	186	pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
	187	return 0;
	188	}
6f90a8bd YS	189	}
6f90a8bd YS	190
7653aaab TT	191	void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port,
7653aaab TT	192	char *gamma_table_base)
6f90a8bd YS	193	{
6f90a8bd YS	194	int i;
7653aaab	195	if (port == FSL_DIU_PORT_DLVDS) {
6f90a8bd YS	196	for (i = 0; i < 256*3; i++)
	197	gamma_table_base[i] = (gamma_table_base[i] << 2) \|
	198	((gamma_table_base[i] >> 6) & 0x03);
	199	}
	200	}
	201
f637ef8e AV	202	#define PX_BRDCFG0_DVISEL (1 << 3)
	203	#define PX_BRDCFG0_DLINK (1 << 4)
	204	#define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL \| PX_BRDCFG0_DLINK)
	205
7653aaab	206	void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)
6f90a8bd	207	{
7653aaab TT	208	switch (port) {
7653aaab TT	209	case FSL_DIU_PORT_DVI:
f637ef8e	210	clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
7653aaab TT	211	PX_BRDCFG0_DVISEL \| PX_BRDCFG0_DLINK);
	212	break;
	213	case FSL_DIU_PORT_LVDS:
	214	clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
	215	PX_BRDCFG0_DLINK);
	216	break;
	217	case FSL_DIU_PORT_DLVDS:
	218	clrbits8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK);
	219	break;
	220	}
6f90a8bd YS	221	}
6f90a8bd YS	222
c8bfa77b TT	223	/**
	224	* mpc8610hpcd_set_pixel_clock: program the DIU's clock
	225	*
	226	* @pixclock: the wavelength, in picoseconds, of the clock
	227	*/
6f90a8bd YS	228	void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
6f90a8bd YS	229	{
c8bfa77b	230	struct device_node *guts_np = NULL;
9cb6abcb	231	struct ccsr_guts __iomem *guts;
c8bfa77b TT	232	unsigned long freq;
	233	u64 temp;
	234	u32 pxclk;
	235
	236	/* Map the global utilities registers. */
	237	guts_np = of_find_compatible_node(NULL, NULL, "fsl,mpc8610-guts");
	238	if (!guts_np) {
b6741bc7	239	pr_err("mpc8610hpcd: missing global utilities device node\n");
6f90a8bd YS	240	return;
	241	}
	242
c8bfa77b TT	243	guts = of_iomap(guts_np, 0);
	244	of_node_put(guts_np);
	245	if (!guts) {
b6741bc7	246	pr_err("mpc8610hpcd: could not map global utilities device\n");
c8bfa77b	247	return;
6f90a8bd YS	248	}
6f90a8bd YS	249
c8bfa77b TT	250	/* Convert pixclock from a wavelength to a frequency */
	251	temp = 1000000000000ULL;
	252	do_div(temp, pixclock);
	253	freq = temp;
	254
	255	/*
	256	* 'pxclk' is the ratio of the platform clock to the pixel clock.
	257	* On the MPC8610, the value programmed into CLKDVDR is the ratio
	258	* minus one. The valid range of values is 2-31.
	259	*/
	260	pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq) - 1;
	261	pxclk = clamp_t(u32, pxclk, 2, 31);
	262
	263	/* Disable the pixel clock, and set it to non-inverted and no delay */
	264	clrbits32(&guts->clkdvdr,
	265	CLKDVDR_PXCKEN \| CLKDVDR_PXCKDLY \| CLKDVDR_PXCLK_MASK);
	266
	267	/* Enable the clock and set the pxclk */
	268	setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN \| (pxclk << 16));
	269
	270	iounmap(guts);
6f90a8bd YS	271	}
6f90a8bd YS	272
7653aaab TT	273	enum fsl_diu_monitor_port
7653aaab TT	274	mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
6f90a8bd	275	{
7653aaab	276	return port;
6f90a8bd YS	277	}
6f90a8bd YS	278
0e65bfe3	279	#endif
6f90a8bd YS	280
	281	static void __init mpc86xx_hpcd_setup_arch(void)
	282	{
	283	struct resource r;
6f90a8bd YS	284	unsigned char *pixis;
6f90a8bd YS	285
0e65bfe3 XX	286	if (ppc_md.progress)
	287	ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
	288
905e75c4 JH	289	fsl_pci_assign_primary();
905e75c4 JH	290
6f90a8bd	291	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)
6f90a8bd YS	292	diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
	293	diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
	294	diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
	295	diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
7653aaab	296	diu_ops.valid_monitor_port = mpc8610hpcd_valid_monitor_port;
6f90a8bd YS	297	#endif
6f90a8bd YS	298
8c68e2f7 AV	299	pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
	300	if (pixis_node) {
	301	of_address_to_resource(pixis_node, 0, &r);
	302	of_node_put(pixis_node);
6f90a8bd YS	303	pixis = ioremap(r.start, 32);
	304	if (!pixis) {
	305	printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
	306	return;
	307	}
	308	pixis_bdcfg0 = pixis + 8;
	309	pixis_arch = pixis + 1;
	310	} else
	311	printk(KERN_ERR "Err: "
	312	"can't find device node 'fsl,fpga-pixis'\n");
0e65bfe3 XX	313
	314	printk("MPC86xx HPCD board from Freescale Semiconductor\n");
	315	}
	316
	317	/*
	318	* Called very early, device-tree isn't unflattened
	319	*/
	320	static int __init mpc86xx_hpcd_probe(void)
	321	{
	322	unsigned long root = of_get_flat_dt_root();
	323
	324	if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
	325	return 1; /* Looks good */
	326
	327	return 0;
	328	}
	329
6f90a8bd	330	static long __init mpc86xx_time_init(void)
0e65bfe3 XX	331	{
	332	unsigned int temp;
	333
	334	/* Set the time base to zero */
	335	mtspr(SPRN_TBWL, 0);
	336	mtspr(SPRN_TBWU, 0);
	337
	338	temp = mfspr(SPRN_HID0);
	339	temp \|= HID0_TBEN;
	340	mtspr(SPRN_HID0, temp);
	341	asm volatile("isync");
	342
	343	return 0;
	344	}
	345
	346	define_machine(mpc86xx_hpcd) {
	347	.name = "MPC86xx HPCD",
	348	.probe = mpc86xx_hpcd_probe,
	349	.setup_arch = mpc86xx_hpcd_setup_arch,
98384c6c	350	.init_IRQ = mpc86xx_init_irq,
0e65bfe3	351	.get_irq = mpic_get_irq,
e1c1575f	352	.restart = fsl_rstcr_restart,
0e65bfe3 XX	353	.time_init = mpc86xx_time_init,
	354	.calibrate_decr = generic_calibrate_decr,
	355	.progress = udbg_progress,
b567d1c7	356	#ifdef CONFIG_PCI
0e65bfe3	357	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
b567d1c7	358	#endif
0e65bfe3	359	};