Commit | Line | Data |
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4ca4b627 JL |
1 | /* |
2 | * MPC86xx HPCN board specific routines | |
3 | * | |
4 | * Recode: ZHANG WEI <wei.zhang@freescale.com> | |
5 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> | |
6 | * | |
7 | * Copyright 2006 Freescale Semiconductor Inc. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | */ | |
14 | ||
4ca4b627 JL |
15 | #include <linux/stddef.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/kdev_t.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/seq_file.h> | |
4ca4b627 JL |
21 | |
22 | #include <asm/system.h> | |
23 | #include <asm/time.h> | |
24 | #include <asm/machdep.h> | |
25 | #include <asm/pci-bridge.h> | |
26 | #include <asm/mpc86xx.h> | |
27 | #include <asm/prom.h> | |
28 | #include <mm/mmu_decl.h> | |
29 | #include <asm/udbg.h> | |
30 | #include <asm/i8259.h> | |
31 | ||
32 | #include <asm/mpic.h> | |
33 | ||
9ac4dd30 | 34 | #include <sysdev/fsl_pci.h> |
4ca4b627 JL |
35 | #include <sysdev/fsl_soc.h> |
36 | ||
37 | #include "mpc86xx.h" | |
38 | ||
919fede6 JL |
39 | #undef DEBUG |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(fmt...) do { printk(KERN_ERR fmt); } while(0) | |
43 | #else | |
44 | #define DBG(fmt...) do { } while(0) | |
45 | #endif | |
46 | ||
869d7f38 | 47 | #ifdef CONFIG_PCI |
35a84c2f | 48 | static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc) |
919fede6 | 49 | { |
35a84c2f | 50 | unsigned int cascade_irq = i8259_irq(); |
919fede6 | 51 | if (cascade_irq != NO_IRQ) |
49f19ce4 | 52 | generic_handle_irq(cascade_irq); |
919fede6 JL |
53 | desc->chip->eoi(irq); |
54 | } | |
869d7f38 | 55 | #endif /* CONFIG_PCI */ |
4ca4b627 JL |
56 | |
57 | void __init | |
58 | mpc86xx_hpcn_init_irq(void) | |
59 | { | |
60 | struct mpic *mpic1; | |
869d7f38 | 61 | struct device_node *np; |
c85c41ad | 62 | struct resource res; |
869d7f38 JL |
63 | #ifdef CONFIG_PCI |
64 | struct device_node *cascade_node = NULL; | |
65 | int cascade_irq; | |
66 | #endif | |
4ca4b627 | 67 | |
c85c41ad | 68 | /* Determine PIC address. */ |
919fede6 JL |
69 | np = of_find_node_by_type(NULL, "open-pic"); |
70 | if (np == NULL) | |
71 | return; | |
c85c41ad | 72 | of_address_to_resource(np, 0, &res); |
4ca4b627 JL |
73 | |
74 | /* Alloc mpic structure and per isu has 16 INT entries. */ | |
c85c41ad | 75 | mpic1 = mpic_alloc(np, res.start, |
4ca4b627 | 76 | MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, |
b533f8ae | 77 | 0, 256, " MPIC "); |
4ca4b627 JL |
78 | BUG_ON(mpic1 == NULL); |
79 | ||
4ca4b627 JL |
80 | mpic_init(mpic1); |
81 | ||
82 | #ifdef CONFIG_PCI | |
919fede6 JL |
83 | /* Initialize i8259 controller */ |
84 | for_each_node_by_type(np, "interrupt-controller") | |
55b61fec | 85 | if (of_device_is_compatible(np, "chrp,iic")) { |
919fede6 JL |
86 | cascade_node = np; |
87 | break; | |
88 | } | |
89 | if (cascade_node == NULL) { | |
90 | printk(KERN_DEBUG "mpc86xxhpcn: no ISA interrupt controller\n"); | |
91 | return; | |
92 | } | |
4ca4b627 | 93 | |
919fede6 JL |
94 | cascade_irq = irq_of_parse_and_map(cascade_node, 0); |
95 | if (cascade_irq == NO_IRQ) { | |
96 | printk(KERN_ERR "mpc86xxhpcn: failed to map cascade interrupt"); | |
97 | return; | |
98 | } | |
99 | DBG("mpc86xxhpcn: cascade mapped to irq %d\n", cascade_irq); | |
4ca4b627 | 100 | |
919fede6 | 101 | i8259_init(cascade_node, 0); |
00e402d0 JL |
102 | of_node_put(cascade_node); |
103 | ||
919fede6 JL |
104 | set_irq_chained_handler(cascade_irq, mpc86xx_8259_cascade); |
105 | #endif | |
106 | } | |
4ca4b627 JL |
107 | |
108 | #ifdef CONFIG_PCI | |
b66510cb KG |
109 | extern int uses_fsl_uli_m1575; |
110 | extern int uli_exclude_device(struct pci_controller *hose, | |
111 | u_char bus, u_char devfn); | |
4ca4b627 | 112 | |
b66510cb KG |
113 | static int mpc86xx_exclude_device(struct pci_controller *hose, |
114 | u_char bus, u_char devfn) | |
4ca4b627 | 115 | { |
b66510cb KG |
116 | struct device_node* node; |
117 | struct resource rsrc; | |
9ad494f6 | 118 | |
44ef3390 | 119 | node = hose->dn; |
b66510cb | 120 | of_address_to_resource(node, 0, &rsrc); |
9ad494f6 | 121 | |
b66510cb KG |
122 | if ((rsrc.start & 0xfffff) == 0x8000) { |
123 | return uli_exclude_device(hose, bus, devfn); | |
124 | } | |
9ad494f6 | 125 | |
b66510cb | 126 | return PCIBIOS_SUCCESSFUL; |
9ad494f6 | 127 | } |
4ca4b627 JL |
128 | #endif /* CONFIG_PCI */ |
129 | ||
130 | ||
131 | static void __init | |
132 | mpc86xx_hpcn_setup_arch(void) | |
133 | { | |
d347b329 | 134 | #ifdef CONFIG_PCI |
4ca4b627 | 135 | struct device_node *np; |
d347b329 | 136 | #endif |
4ca4b627 JL |
137 | |
138 | if (ppc_md.progress) | |
139 | ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0); | |
140 | ||
4ca4b627 | 141 | #ifdef CONFIG_PCI |
c9438aff | 142 | for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") { |
9ac4dd30 ZR |
143 | struct resource rsrc; |
144 | of_address_to_resource(np, 0, &rsrc); | |
145 | if ((rsrc.start & 0xfffff) == 0x8000) | |
146 | fsl_add_bridge(np, 1); | |
147 | else | |
148 | fsl_add_bridge(np, 0); | |
149 | } | |
c9438aff | 150 | |
b66510cb KG |
151 | uses_fsl_uli_m1575 = 1; |
152 | ppc_md.pci_exclude_device = mpc86xx_exclude_device; | |
153 | ||
4ca4b627 JL |
154 | #endif |
155 | ||
156 | printk("MPC86xx HPCN board from Freescale Semiconductor\n"); | |
157 | ||
4ca4b627 JL |
158 | #ifdef CONFIG_SMP |
159 | mpc86xx_smp_init(); | |
160 | #endif | |
161 | } | |
162 | ||
163 | ||
164 | void | |
165 | mpc86xx_hpcn_show_cpuinfo(struct seq_file *m) | |
166 | { | |
167 | struct device_node *root; | |
168 | uint memsize = total_memory; | |
169 | const char *model = ""; | |
170 | uint svid = mfspr(SPRN_SVR); | |
171 | ||
172 | seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n"); | |
173 | ||
174 | root = of_find_node_by_path("/"); | |
175 | if (root) | |
e2eb6392 | 176 | model = of_get_property(root, "model", NULL); |
4ca4b627 JL |
177 | seq_printf(m, "Machine\t\t: %s\n", model); |
178 | of_node_put(root); | |
179 | ||
180 | seq_printf(m, "SVR\t\t: 0x%x\n", svid); | |
181 | seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024)); | |
182 | } | |
183 | ||
184 | ||
185 | /* | |
186 | * Called very early, device-tree isn't unflattened | |
187 | */ | |
188 | static int __init mpc86xx_hpcn_probe(void) | |
189 | { | |
190 | unsigned long root = of_get_flat_dt_root(); | |
191 | ||
192 | if (of_flat_dt_is_compatible(root, "mpc86xx")) | |
193 | return 1; /* Looks good */ | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
4ca4b627 JL |
198 | long __init |
199 | mpc86xx_time_init(void) | |
200 | { | |
201 | unsigned int temp; | |
202 | ||
203 | /* Set the time base to zero */ | |
204 | mtspr(SPRN_TBWL, 0); | |
205 | mtspr(SPRN_TBWU, 0); | |
206 | ||
207 | temp = mfspr(SPRN_HID0); | |
208 | temp |= HID0_TBEN; | |
209 | mtspr(SPRN_HID0, temp); | |
210 | asm volatile("isync"); | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
4ca4b627 JL |
215 | define_machine(mpc86xx_hpcn) { |
216 | .name = "MPC86xx HPCN", | |
217 | .probe = mpc86xx_hpcn_probe, | |
218 | .setup_arch = mpc86xx_hpcn_setup_arch, | |
219 | .init_IRQ = mpc86xx_hpcn_init_irq, | |
220 | .show_cpuinfo = mpc86xx_hpcn_show_cpuinfo, | |
221 | .get_irq = mpic_get_irq, | |
e1c1575f | 222 | .restart = fsl_rstcr_restart, |
4ca4b627 JL |
223 | .time_init = mpc86xx_time_init, |
224 | .calibrate_decr = generic_calibrate_decr, | |
225 | .progress = udbg_progress, | |
2af8569d | 226 | #ifdef CONFIG_PCI |
6c0a11c1 | 227 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
2af8569d | 228 | #endif |
4ca4b627 | 229 | }; |