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4ca4b627 JL |
1 | /* |
2 | * Author: Xianghua Xiao <x.xiao@freescale.com> | |
3 | * Zhang Wei <wei.zhang@freescale.com> | |
4 | * | |
5 | * Copyright 2006 Freescale Semiconductor Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
4ca4b627 JL |
13 | #include <linux/stddef.h> |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
17 | ||
aaddd3ea | 18 | #include <asm/code-patching.h> |
4ca4b627 | 19 | #include <asm/page.h> |
f1a1eb29 | 20 | #include <asm/pgtable.h> |
4ca4b627 | 21 | #include <asm/pci-bridge.h> |
b8b572e1 | 22 | #include <asm/mpic.h> |
4ca4b627 JL |
23 | #include <asm/cacheflush.h> |
24 | ||
25 | #include <sysdev/fsl_soc.h> | |
26 | ||
27 | #include "mpc86xx.h" | |
28 | ||
29 | extern void __secondary_start_mpc86xx(void); | |
30 | extern unsigned long __secondary_hold_acknowledge; | |
31 | ||
1e76dff2 KG |
32 | #define MCM_PORT_CONFIG_OFFSET 0x10 |
33 | ||
34 | /* Offset from CCSRBAR */ | |
35 | #define MPC86xx_MCM_OFFSET (0x1000) | |
36 | #define MPC86xx_MCM_SIZE (0x1000) | |
4ca4b627 JL |
37 | |
38 | static void __init | |
39 | smp_86xx_release_core(int nr) | |
40 | { | |
9ad494f6 KG |
41 | __be32 __iomem *mcm_vaddr; |
42 | unsigned long pcr; | |
4ca4b627 JL |
43 | |
44 | if (nr < 0 || nr >= NR_CPUS) | |
45 | return; | |
46 | ||
47 | /* | |
48 | * Startup Core #nr. | |
49 | */ | |
50 | mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET, | |
51 | MPC86xx_MCM_SIZE); | |
9ad494f6 | 52 | pcr = in_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2)); |
4ca4b627 | 53 | pcr |= 1 << (nr + 24); |
9ad494f6 | 54 | out_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2), pcr); |
1e76dff2 KG |
55 | |
56 | iounmap(mcm_vaddr); | |
4ca4b627 JL |
57 | } |
58 | ||
59 | ||
60 | static void __init | |
61 | smp_86xx_kick_cpu(int nr) | |
62 | { | |
63 | unsigned int save_vector; | |
64 | unsigned long target, flags; | |
65 | int n = 0; | |
e7a57273 | 66 | unsigned int *vector = (unsigned int *)(KERNELBASE + 0x100); |
4ca4b627 JL |
67 | |
68 | if (nr < 0 || nr >= NR_CPUS) | |
69 | return; | |
70 | ||
71 | pr_debug("smp_86xx_kick_cpu: kick CPU #%d\n", nr); | |
72 | ||
73 | local_irq_save(flags); | |
4ca4b627 JL |
74 | |
75 | /* Save reset vector */ | |
76 | save_vector = *vector; | |
77 | ||
78 | /* Setup fake reset vector to call __secondary_start_mpc86xx. */ | |
79 | target = (unsigned long) __secondary_start_mpc86xx; | |
e7a57273 | 80 | patch_branch(vector, target, BRANCH_SET_LINK); |
4ca4b627 JL |
81 | |
82 | /* Kick that CPU */ | |
83 | smp_86xx_release_core(nr); | |
84 | ||
85 | /* Wait a bit for the CPU to take the exception. */ | |
86 | while ((__secondary_hold_acknowledge != nr) && (n++, n < 1000)) | |
87 | mdelay(1); | |
88 | ||
89 | /* Restore the exception vector */ | |
90 | *vector = save_vector; | |
91 | flush_icache_range((unsigned long) vector, (unsigned long) vector + 4); | |
92 | ||
93 | local_irq_restore(flags); | |
94 | ||
95 | pr_debug("wait CPU #%d for %d msecs.\n", nr, n); | |
96 | } | |
97 | ||
98 | ||
99 | static void __init | |
100 | smp_86xx_setup_cpu(int cpu_nr) | |
101 | { | |
102 | mpic_setup_this_cpu(); | |
103 | } | |
104 | ||
105 | ||
106 | struct smp_ops_t smp_86xx_ops = { | |
107 | .message_pass = smp_mpic_message_pass, | |
108 | .probe = smp_mpic_probe, | |
109 | .kick_cpu = smp_86xx_kick_cpu, | |
110 | .setup_cpu = smp_86xx_setup_cpu, | |
111 | .take_timebase = smp_generic_take_timebase, | |
112 | .give_timebase = smp_generic_give_timebase, | |
113 | }; | |
114 | ||
115 | ||
116 | void __init | |
117 | mpc86xx_smp_init(void) | |
118 | { | |
119 | smp_ops = &smp_86xx_ops; | |
120 | } |