Merge branch 'for-linville' of git://github.com/kvalo/ath
[deliverable/linux.git] / arch / powerpc / platforms / Kconfig
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4330f5da 1menu "Platform support"
4330f5da 2
55190f88 3source "arch/powerpc/platforms/powernv/Kconfig"
4330f5da 4source "arch/powerpc/platforms/pseries/Kconfig"
4330f5da 5source "arch/powerpc/platforms/chrp/Kconfig"
e177edcd 6source "arch/powerpc/platforms/512x/Kconfig"
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7source "arch/powerpc/platforms/52xx/Kconfig"
8source "arch/powerpc/platforms/powermac/Kconfig"
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9source "arch/powerpc/platforms/maple/Kconfig"
10source "arch/powerpc/platforms/pasemi/Kconfig"
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11source "arch/powerpc/platforms/ps3/Kconfig"
12source "arch/powerpc/platforms/cell/Kconfig"
c8a55f3d 13source "arch/powerpc/platforms/8xx/Kconfig"
d6071f88 14source "arch/powerpc/platforms/82xx/Kconfig"
b5a48346 15source "arch/powerpc/platforms/83xx/Kconfig"
db947808 16source "arch/powerpc/platforms/85xx/Kconfig"
4a89f7fa 17source "arch/powerpc/platforms/86xx/Kconfig"
98750261 18source "arch/powerpc/platforms/embedded6xx/Kconfig"
f6dfc805 19source "arch/powerpc/platforms/44x/Kconfig"
545c069c 20source "arch/powerpc/platforms/40x/Kconfig"
54b318aa 21source "arch/powerpc/platforms/amigaone/Kconfig"
4330f5da 22
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23config KVM_GUEST
24 bool "KVM Guest support"
643ba4e3 25 default n
2e1ae9c0 26 select EPAPR_PARAVIRT
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27 ---help---
28 This option enables various optimizations for running under the KVM
29 hypervisor. Overhead for the kernel when not running inside KVM should
30 be minimal.
31
32 In case of doubt, say Y
33
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34config EPAPR_PARAVIRT
35 bool "ePAPR para-virtualization support"
36 default n
37 help
38 Enables ePAPR para-virtualization support for guests.
39
40 In case of doubt, say Y
41
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42config PPC_NATIVE
43 bool
28794d34 44 depends on 6xx || PPC64
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45 help
46 Support for running natively on the hardware, i.e. without
47 a hypervisor. This option is not user-selectable but should
48 be selected by all platforms that need it.
49
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50config PPC_OF_BOOT_TRAMPOLINE
51 bool "Support booting from Open Firmware or yaboot"
52 depends on 6xx || PPC64
53 default y
54 help
55 Support from booting from Open Firmware or yaboot using an
56 Open Firmware client interface. This enables the kernel to
f65e51d7 57 communicate with open firmware to retrieve system information
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58 such as the device tree.
59
60 In case of doubt, say Y
61
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62config UDBG_RTAS_CONSOLE
63 bool "RTAS based debug console"
64 depends on PPC_RTAS
65 default n
66
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67config PPC_SMP_MUXED_IPI
68 bool
69 help
70 Select this opton if your platform supports SMP and your
71 interrupt controller provides less than 4 interrupts to each
72 cpu. This will enable the generic code to multiplex the 4
73 messages on to one ipi.
74
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75config PPC_UDBG_BEAT
76 bool "BEAT based debug console"
77 depends on PPC_CELLEB
78 default n
79
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80config IPIC
81 bool
82 default n
83
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84config MPIC
85 bool
86 default n
87
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88config MPIC_TIMER
89 bool "MPIC Global Timer"
90 depends on MPIC && FSL_SOC
91 default n
92 help
93 The MPIC global timer is a hardware timer inside the
94 Freescale PIC complying with OpenPIC standard. When the
95 specified interval times out, the hardware timer generates
96 an interrupt. The driver currently is only tested on fsl
97 chip, but it can potentially support other global timers
98 complying with the OpenPIC standard.
99
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100config FSL_MPIC_TIMER_WAKEUP
101 tristate "Freescale MPIC global timer wakeup driver"
102 depends on FSL_SOC && MPIC_TIMER && PM
103 default n
104 help
105 The driver provides a way to wake up the system by MPIC
106 timer.
107 e.g. "echo 5 > /sys/devices/system/mpic/timer_wakeup"
108
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109config PPC_EPAPR_HV_PIC
110 bool
111 default n
40656397 112 select EPAPR_PARAVIRT
3a93261f 113
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114config MPIC_WEIRD
115 bool
116 default n
117
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118config MPIC_MSGR
119 bool "MPIC message register support"
120 depends on MPIC
121 default n
122 help
123 Enables support for the MPIC message registers. These
124 registers are used for inter-processor communication.
125
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126config PPC_I8259
127 bool
128 default n
129
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130config U3_DART
131 bool
28794d34 132 depends on PPC64
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133 default n
134
135config PPC_RTAS
136 bool
137 default n
138
139config RTAS_ERROR_LOGGING
140 bool
141 depends on PPC_RTAS
142 default n
143
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144config PPC_RTAS_DAEMON
145 bool
146 depends on PPC_RTAS
147 default n
148
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149config RTAS_PROC
150 bool "Proc interface to RTAS"
b80ec3dc 151 depends on PPC_RTAS && PROC_FS
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152 default y
153
154config RTAS_FLASH
155 tristate "Firmware flash interface"
156 depends on PPC64 && RTAS_PROC
157
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158config MMIO_NVRAM
159 bool
160 default n
161
6cfef5b2 162config MPIC_U3_HT_IRQS
4330f5da 163 bool
314b389b 164 default n
4330f5da 165
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166config MPIC_BROKEN_REGREAD
167 bool
168 depends on MPIC
169 help
170 This option enables a MPIC driver workaround for some chips
171 that have a bug that causes some interrupt source information
172 to not read back properly. It is safe to use on other chips as
173 well, but enabling it uses about 8KB of memory to keep copies
174 of the register contents in software.
175
4330f5da 176config IBMVIO
3d066d77 177 depends on PPC_PSERIES
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178 bool
179 default y
180
181config IBMEBUS
182 depends on PPC_PSERIES
183 bool "Support for GX bus based adapters"
184 help
185 Bus device driver for GX bus based adapters.
186
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187config EEH
188 bool
189 depends on (PPC_POWERNV || PPC_PSERIES) && PCI
190 default y
191
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192config PPC_MPC106
193 bool
194 default n
195
196config PPC_970_NAP
197 bool
198 default n
199
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200config PPC_P7_NAP
201 bool
202 default n
203
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204config PPC_INDIRECT_PIO
205 bool
ecd73cc5 206 select GENERIC_IOMAP
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207
208config PPC_INDIRECT_MMIO
209 bool
4330f5da 210
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211config PPC_IO_WORKAROUNDS
212 bool
213
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214source "drivers/cpufreq/Kconfig"
215
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216menu "CPUIdle driver"
217
218source "drivers/cpuidle/Kconfig"
219
220endmenu
221
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222config PPC601_SYNC_FIX
223 bool "Workarounds for PPC601 bugs"
933ee711 224 depends on 6xx && PPC_PMAC
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225 help
226 Some versions of the PPC601 (the first PowerPC chip) have bugs which
227 mean that extra synchronization instructions are required near
228 certain instructions, typically those that make major changes to the
229 CPU state. These extra instructions reduce performance slightly.
230 If you say N here, these extra instructions will not be included,
231 resulting in a kernel which will run faster but may not run at all
232 on some systems with the PPC601 chip.
233
234 If in doubt, say Y here.
235
236config TAU
237 bool "On-chip CPU temperature sensor support"
28794d34 238 depends on 6xx
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239 help
240 G3 and G4 processors have an on-chip temperature sensor called the
241 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
242 temperature within 2-4 degrees Celsius. This option shows the current
243 on-die temperature in /proc/cpuinfo if the cpu supports it.
244
245 Unfortunately, on some chip revisions, this sensor is very inaccurate
246 and in many cases, does not work at all, so don't assume the cpu
247 temp is actually what /proc/cpuinfo says it is.
248
249config TAU_INT
250 bool "Interrupt driven TAU driver (DANGEROUS)"
251 depends on TAU
252 ---help---
253 The TAU supports an interrupt driven mode which causes an interrupt
254 whenever the temperature goes out of range. This is the fastest way
255 to get notified the temp has exceeded a range. With this option off,
256 a timer is used to re-check the temperature periodically.
257
258 However, on some cpus it appears that the TAU interrupt hardware
259 is buggy and can cause a situation which would lead unexplained hard
260 lockups.
261
262 Unless you are extending the TAU driver, or enjoy kernel/hardware
263 debugging, leave this option off.
264
265config TAU_AVERAGE
266 bool "Average high and low temp"
267 depends on TAU
268 ---help---
269 The TAU hardware can compare the temperature to an upper and lower
270 bound. The default behavior is to show both the upper and lower
271 bound in /proc/cpuinfo. If the range is large, the temperature is
272 either changing a lot, or the TAU hardware is broken (likely on some
273 G4's). If the range is small (around 4 degrees), the temperature is
274 relatively stable. If you say Y here, a single temperature value,
275 halfway between the upper and lower bounds, will be reported in
276 /proc/cpuinfo.
277
278 If in doubt, say N here.
279
98750261 280config QUICC_ENGINE
4e330bcf 281 bool "Freescale QUICC Engine (QE) Support"
47fe819e 282 depends on FSL_SOC && PPC32
1088a209 283 select PPC_LIB_RHEAP
bc556ba9 284 select CRC32
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285 help
286 The QUICC Engine (QE) is a new generation of communications
287 coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
288 Selecting this option means that you wish to build a kernel
289 for a machine with a QE coprocessor.
290
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291config QE_GPIO
292 bool "QE GPIO support"
293 depends on QUICC_ENGINE
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294 select ARCH_REQUIRE_GPIOLIB
295 help
296 Say Y here if you're going to use hardware that connects to the
297 QE GPIOs.
298
d6071f88 299config CPM2
b8b3caf3 300 bool "Enable support for the CPM2 (Communications Processor Module)"
5753c082 301 depends on (FSL_SOC_BOOKE && PPC32) || 8260
c374e00e 302 select CPM
1088a209 303 select PPC_LIB_RHEAP
b500563b 304 select PPC_PCI_CHOICE
e193325e 305 select ARCH_REQUIRE_GPIOLIB
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306 help
307 The CPM2 (Communications Processor Module) is a coprocessor on
308 embedded CPUs made by Freescale. Selecting this option means that
309 you wish to build a kernel for a machine with a CPM2 coprocessor
310 on it (826x, 827x, 8560).
311
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312config AXON_RAM
313 tristate "Axon DDR2 memory device driver"
ebf0f334 314 depends on PPC_IBM_CELL_BLADE && BLOCK
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315 default m
316 help
317 It registers one block device per Axon's DDR2 memory bank found
318 on a system. Block devices are called axonram?, their major and
319 minor numbers are available in /proc/devices, /proc/partitions or
320 in /sys/block/axonram?/dev.
321
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322config FSL_ULI1575
323 bool
324 default n
fb4f0e88 325 select GENERIC_ISA_DMA
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326 help
327 Supports for the ULI1575 PCIe south bridge that exists on some
328 Freescale reference boards. The boards all use the ULI in pretty
329 much the same way.
330
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331config CPM
332 bool
333
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334config OF_RTC
335 bool
336 help
692105b8 337 Uses information from the OF or flattened device tree to instantiate
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338 platform devices for direct mapped RTC chips like the DS1742 or DS1743.
339
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340config SIMPLE_GPIO
341 bool "Support for simple, memory-mapped GPIO controllers"
342 depends on PPC
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343 select ARCH_REQUIRE_GPIOLIB
344 help
345 Say Y here to support simple, memory-mapped GPIO controllers.
346 These are usually BCSRs used to control board's switches, LEDs,
347 chip-selects, Ethernet/USB PHY's power and various other small
348 on-board peripherals.
349
ea0105ea 350config MCU_MPC8349EMITX
6ca6ca5d 351 bool "MPC8349E-mITX MCU driver"
82640a6b 352 depends on I2C=y && PPC_83xx
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353 select ARCH_REQUIRE_GPIOLIB
354 help
355 Say Y here to enable soft power-off functionality on the Freescale
356 boards with the MPC8349E-mITX-compatible MCU chips. This driver will
357 also register MCU GPIOs with the generic GPIO API, so you'll able
358 to use MCU pins as GPIOs.
359
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360config XILINX_PCI
361 bool "Xilinx PCI host bridge support"
362 depends on PCI && XILINX_VIRTEX
363
4330f5da 364endmenu
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