Commit | Line | Data |
---|---|---|
a0ae9c7c AB |
1 | config PPC64 |
2 | bool "64-bit kernel" | |
3 | default n | |
b952741c | 4 | select HAVE_VIRT_CPU_ACCOUNTING |
a0ae9c7c AB |
5 | help |
6 | This option selects whether a 32-bit or a 64-bit kernel | |
7 | will be built. | |
8 | ||
9 | menu "Processor support" | |
10 | choice | |
11 | prompt "Processor Type" | |
12 | depends on PPC32 | |
a0ae9c7c | 13 | help |
b9fd305d AB |
14 | There are five families of 32 bit PowerPC chips supported. |
15 | The most common ones are the desktop and server CPUs (601, 603, | |
16 | 604, 740, 750, 74xx) CPUs from Freescale and IBM, with their | |
e177edcd | 17 | embedded 512x/52xx/82xx/83xx/86xx counterparts. |
b9fd305d AB |
18 | The other embeeded parts, namely 4xx, 8xx, e200 (55xx) and e500 |
19 | (85xx) each form a family of their own that is not compatible | |
20 | with the others. | |
21 | ||
22 | If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx. | |
23 | ||
48c93112 | 24 | config PPC_BOOK3S_32 |
e177edcd | 25 | bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx" |
a0ae9c7c AB |
26 | select PPC_FPU |
27 | ||
a0ae9c7c AB |
28 | config PPC_85xx |
29 | bool "Freescale 85xx" | |
30 | select E500 | |
a0ae9c7c | 31 | |
a0ae9c7c AB |
32 | config PPC_8xx |
33 | bool "Freescale 8xx" | |
34 | select FSL_SOC | |
35 | select 8xx | |
1088a209 | 36 | select PPC_LIB_RHEAP |
a0ae9c7c AB |
37 | |
38 | config 40x | |
39 | bool "AMCC 40x" | |
40 | select PPC_DCR_NATIVE | |
9dae8afd | 41 | select PPC_UDBG_16550 |
93173ce2 | 42 | select 4xx_SOC |
b500563b | 43 | select PPC_PCI_CHOICE |
a0ae9c7c AB |
44 | |
45 | config 44x | |
e7f75ad0 | 46 | bool "AMCC 44x, 46x or 47x" |
a0ae9c7c | 47 | select PPC_DCR_NATIVE |
1d5499b5 | 48 | select PPC_UDBG_16550 |
93173ce2 | 49 | select 4xx_SOC |
b500563b | 50 | select PPC_PCI_CHOICE |
4ee7084e | 51 | select PHYS_64BIT |
a0ae9c7c AB |
52 | |
53 | config E200 | |
54 | bool "Freescale e200" | |
55 | ||
56 | endchoice | |
57 | ||
2d27cfd3 BH |
58 | choice |
59 | prompt "Processor Type" | |
5b7c3c91 | 60 | depends on PPC64 |
2d27cfd3 BH |
61 | help |
62 | There are two families of 64 bit PowerPC chips supported. | |
63 | The most common ones are the desktop and server CPUs | |
64 | (POWER3, RS64, POWER4, POWER5, POWER5+, POWER6, ...) | |
65 | ||
66 | The other are the "embedded" processors compliant with the | |
67 | "Book 3E" variant of the architecture | |
68 | ||
69 | config PPC_BOOK3S_64 | |
70 | bool "Server processors" | |
5b7c3c91 | 71 | select PPC_FPU |
5adfd346 | 72 | select PPC_HAVE_PMU_SUPPORT |
41151e77 | 73 | select SYS_SUPPORTS_HUGETLBFS |
5b7c3c91 | 74 | |
2d27cfd3 BH |
75 | config PPC_BOOK3E_64 |
76 | bool "Embedded processors" | |
77 | select PPC_FPU # Make it a choice ? | |
1ece355b | 78 | select PPC_SMP_MUXED_IPI |
2d27cfd3 BH |
79 | |
80 | endchoice | |
81 | ||
d23c6fb4 AB |
82 | choice |
83 | prompt "CPU selection" | |
84 | depends on PPC64 | |
85 | default GENERIC_CPU | |
86 | help | |
87 | This will create a kernel which is optimised for a particular CPU. | |
88 | The resulting kernel may not run on other CPUs, so use this with care. | |
89 | ||
90 | If unsure, select Generic. | |
91 | ||
92 | config GENERIC_CPU | |
93 | bool "Generic" | |
94 | ||
95 | config CELL_CPU | |
96 | bool "Cell Broadband Engine" | |
97 | ||
98 | config POWER4_CPU | |
99 | bool "POWER4" | |
100 | ||
101 | config POWER5_CPU | |
102 | bool "POWER5" | |
103 | ||
104 | config POWER6_CPU | |
105 | bool "POWER6" | |
106 | ||
107 | config POWER7_CPU | |
108 | bool "POWER7" | |
109 | ||
110 | endchoice | |
111 | ||
48c93112 BH |
112 | config PPC_BOOK3S |
113 | def_bool y | |
114 | depends on PPC_BOOK3S_32 || PPC_BOOK3S_64 | |
28794d34 | 115 | |
2d27cfd3 BH |
116 | config PPC_BOOK3E |
117 | def_bool y | |
118 | depends on PPC_BOOK3E_64 | |
119 | ||
5b7c3c91 BH |
120 | config 6xx |
121 | def_bool y | |
122 | depends on PPC32 && PPC_BOOK3S | |
7325927e | 123 | select PPC_HAVE_PMU_SUPPORT |
5b7c3c91 | 124 | |
a0ae9c7c AB |
125 | config POWER3 |
126 | bool | |
28794d34 | 127 | depends on PPC64 && PPC_BOOK3S |
a0ae9c7c AB |
128 | default y if !POWER4_ONLY |
129 | ||
130 | config POWER4 | |
28794d34 | 131 | depends on PPC64 && PPC_BOOK3S |
a0ae9c7c AB |
132 | def_bool y |
133 | ||
76b4eda8 BH |
134 | config PPC_A2 |
135 | bool | |
136 | depends on PPC_BOOK3E_64 | |
137 | ||
3164cccd AB |
138 | config TUNE_CELL |
139 | bool "Optimize for Cell Broadband Engine" | |
28794d34 | 140 | depends on PPC64 && PPC_BOOK3S |
3164cccd AB |
141 | help |
142 | Cause the compiler to optimize for the PPE of the Cell Broadband | |
143 | Engine. This will make the code run considerably faster on Cell | |
144 | but somewhat slower on other machines. This option only changes | |
145 | the scheduling of instructions, not the selection of instructions | |
146 | itself, so the resulting kernel will keep running on all other | |
147 | machines. When building a kernel that is supposed to run only | |
148 | on Cell, you should also select the POWER4_ONLY option. | |
149 | ||
a0ae9c7c AB |
150 | # this is temp to handle compat with arch=ppc |
151 | config 8xx | |
152 | bool | |
153 | ||
a0ae9c7c | 154 | config E500 |
39aef685 | 155 | select FSL_EMB_PERFMON |
4490c06b | 156 | select PPC_FSL_BOOK3E |
a0ae9c7c AB |
157 | bool |
158 | ||
3dfa8773 KG |
159 | config PPC_E500MC |
160 | bool "e500mc Support" | |
161 | select PPC_FPU | |
162 | depends on E500 | |
9653018b SW |
163 | help |
164 | This must be enabled for running on e500mc (and derivatives | |
165 | such as e5500/e6500), and must be disabled for running on | |
166 | e500v1 or e500v2. | |
3dfa8773 | 167 | |
a0ae9c7c AB |
168 | config PPC_FPU |
169 | bool | |
170 | default y if PPC64 | |
171 | ||
5753c082 KG |
172 | config FSL_EMB_PERFMON |
173 | bool "Freescale Embedded Perfmon" | |
174 | depends on E500 || PPC_83xx | |
175 | help | |
176 | This is the Performance Monitor support found on the e500 core | |
177 | and some e300 cores (c3 and c4). Select this only if your | |
178 | core supports the Embedded Performance Monitor APU | |
179 | ||
a1110654 SW |
180 | config FSL_EMB_PERF_EVENT |
181 | bool | |
182 | depends on FSL_EMB_PERFMON && PERF_EVENTS && !PPC_PERF_CTRS | |
183 | default y | |
184 | ||
185 | config FSL_EMB_PERF_EVENT_E500 | |
186 | bool | |
187 | depends on FSL_EMB_PERF_EVENT && E500 | |
188 | default y | |
189 | ||
a0ae9c7c AB |
190 | config 4xx |
191 | bool | |
192 | depends on 40x || 44x | |
193 | default y | |
194 | ||
195 | config BOOKE | |
196 | bool | |
2d27cfd3 | 197 | depends on E200 || E500 || 44x || PPC_BOOK3E |
a0ae9c7c AB |
198 | default y |
199 | ||
200 | config FSL_BOOKE | |
201 | bool | |
4490c06b | 202 | depends on (E200 || E500) && PPC32 |
a0ae9c7c AB |
203 | default y |
204 | ||
4490c06b KG |
205 | # this is for common code between PPC32 & PPC64 FSL BOOKE |
206 | config PPC_FSL_BOOK3E | |
207 | bool | |
208 | select FSL_EMB_PERFMON | |
1ece355b | 209 | select PPC_SMP_MUXED_IPI |
a475c8ec | 210 | select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64 |
4490c06b | 211 | default y if FSL_BOOKE |
39aef685 | 212 | |
a0ae9c7c AB |
213 | config PTE_64BIT |
214 | bool | |
4ee7084e BB |
215 | depends on 44x || E500 || PPC_86xx |
216 | default y if PHYS_64BIT | |
a0ae9c7c AB |
217 | |
218 | config PHYS_64BIT | |
4ee7084e BB |
219 | bool 'Large physical address support' if E500 || PPC_86xx |
220 | depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx | |
a0ae9c7c AB |
221 | ---help--- |
222 | This option enables kernel support for larger than 32-bit physical | |
4ee7084e BB |
223 | addresses. This feature may not be available on all cores. |
224 | ||
225 | If you have more than 3.5GB of RAM or so, you also need to enable | |
226 | SWIOTLB under Kernel Options for this to work. The actual number | |
227 | is platform-dependent. | |
a0ae9c7c AB |
228 | |
229 | If in doubt, say N here. | |
230 | ||
231 | config ALTIVEC | |
232 | bool "AltiVec Support" | |
28794d34 | 233 | depends on 6xx || POWER4 |
a0ae9c7c AB |
234 | ---help--- |
235 | This option enables kernel support for the Altivec extensions to the | |
236 | PowerPC processor. The kernel currently supports saving and restoring | |
237 | altivec registers, and turning on the 'altivec enable' bit so user | |
238 | processes can execute altivec instructions. | |
239 | ||
240 | This option is only usefully if you have a processor that supports | |
241 | altivec (G4, otherwise known as 74xx series), but does not have | |
242 | any affect on a non-altivec cpu (it does, however add code to the | |
243 | kernel). | |
244 | ||
245 | If in doubt, say Y here. | |
246 | ||
96d5b52c MN |
247 | config VSX |
248 | bool "VSX Support" | |
249 | depends on POWER4 && ALTIVEC && PPC_FPU | |
250 | ---help--- | |
251 | ||
252 | This option enables kernel support for the Vector Scaler extensions | |
253 | to the PowerPC processor. The kernel currently supports saving and | |
254 | restoring VSX registers, and turning on the 'VSX enable' bit so user | |
255 | processes can execute VSX instructions. | |
256 | ||
257 | This option is only useful if you have a processor that supports | |
258 | VSX (P7 and above), but does not have any affect on a non-VSX | |
259 | CPUs (it does, however add code to the kernel). | |
260 | ||
261 | If in doubt, say Y here. | |
262 | ||
851d2e2f THFL |
263 | config PPC_ICSWX |
264 | bool "Support for PowerPC icswx coprocessor instruction" | |
fac26ad4 | 265 | depends on POWER4 || PPC_A2 |
851d2e2f THFL |
266 | default n |
267 | ---help--- | |
268 | ||
269 | This option enables kernel support for the PowerPC Initiate | |
270 | Coprocessor Store Word (icswx) coprocessor instruction on POWER7 | |
271 | or newer processors. | |
272 | ||
273 | This option is only useful if you have a processor that supports | |
274 | the icswx coprocessor instruction. It does not have any effect | |
275 | on processors without the icswx coprocessor instruction. | |
276 | ||
277 | This option slightly increases kernel memory usage. | |
278 | ||
279 | If in doubt, say N here. | |
280 | ||
9d670280 JX |
281 | config PPC_ICSWX_PID |
282 | bool "icswx requires direct PID management" | |
283 | depends on PPC_ICSWX && POWER4 | |
284 | default y | |
285 | ---help--- | |
c3dcf53a | 286 | The PID register in server is used explicitly for ICSWX. In |
6b2aac42 | 287 | embedded systems PID management is done by the system. |
9d670280 | 288 | |
c3dcf53a JX |
289 | config PPC_ICSWX_USE_SIGILL |
290 | bool "Should a bad CT cause a SIGILL?" | |
291 | depends on PPC_ICSWX | |
292 | default n | |
293 | ---help--- | |
294 | Should a bad CT used for "non-record form ICSWX" cause an | |
6b2aac42 | 295 | illegal instruction signal or should it be silent as |
c3dcf53a JX |
296 | architected. |
297 | ||
298 | If in doubt, say N here. | |
299 | ||
a0ae9c7c AB |
300 | config SPE |
301 | bool "SPE Support" | |
3dfa8773 | 302 | depends on E200 || (E500 && !PPC_E500MC) |
a0ae9c7c AB |
303 | default y |
304 | ---help--- | |
305 | This option enables kernel support for the Signal Processing | |
306 | Extensions (SPE) to the PowerPC processor. The kernel currently | |
307 | supports saving and restoring SPE registers, and turning on the | |
308 | 'spe enable' bit so user processes can execute SPE instructions. | |
309 | ||
310 | This option is only useful if you have a processor that supports | |
311 | SPE (e500, otherwise known as 85xx series), but does not have any | |
312 | effect on a non-spe cpu (it does, however add code to the kernel). | |
313 | ||
314 | If in doubt, say Y here. | |
315 | ||
316 | config PPC_STD_MMU | |
5b7c3c91 BH |
317 | def_bool y |
318 | depends on PPC_BOOK3S | |
a0ae9c7c AB |
319 | |
320 | config PPC_STD_MMU_32 | |
321 | def_bool y | |
322 | depends on PPC_STD_MMU && PPC32 | |
323 | ||
5e696617 BH |
324 | config PPC_STD_MMU_64 |
325 | def_bool y | |
326 | depends on PPC_STD_MMU && PPC64 | |
327 | ||
328 | config PPC_MMU_NOHASH | |
329 | def_bool y | |
330 | depends on !PPC_STD_MMU | |
331 | ||
70fe3af8 KG |
332 | config PPC_BOOK3E_MMU |
333 | def_bool y | |
2d27cfd3 | 334 | depends on FSL_BOOKE || PPC_BOOK3E |
70fe3af8 | 335 | |
a0ae9c7c AB |
336 | config PPC_MM_SLICES |
337 | bool | |
a475c8ec | 338 | default y if (!PPC_FSL_BOOK3E && PPC64 && HUGETLB_PAGE) || (PPC_STD_MMU_64 && PPC_64K_PAGES) |
a0ae9c7c AB |
339 | default n |
340 | ||
105988c0 PM |
341 | config PPC_HAVE_PMU_SUPPORT |
342 | bool | |
343 | ||
344 | config PPC_PERF_CTRS | |
345 | def_bool y | |
cdd6c482 | 346 | depends on PERF_EVENTS && PPC_HAVE_PMU_SUPPORT |
105988c0 | 347 | help |
cdd6c482 | 348 | This enables the powerpc-specific perf_event back-end. |
105988c0 | 349 | |
a0ae9c7c | 350 | config SMP |
e7f75ad0 | 351 | depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE || PPC_47x |
a0ae9c7c AB |
352 | bool "Symmetric multi-processing support" |
353 | ---help--- | |
354 | This enables support for systems with more than one CPU. If you have | |
355 | a system with only one CPU, say N. If you have a system with more | |
356 | than one CPU, say Y. Note that the kernel does not currently | |
357 | support SMP machines with 603/603e/603ev or PPC750 ("G3") processors | |
358 | since they have inadequate hardware support for multiprocessor | |
359 | operation. | |
360 | ||
361 | If you say N here, the kernel will run on single and multiprocessor | |
362 | machines, but will use only one CPU of a multiprocessor machine. If | |
363 | you say Y here, the kernel will run on single-processor machines. | |
364 | On a single-processor machine, the kernel will run faster if you say | |
365 | N here. | |
366 | ||
367 | If you don't know what to do here, say N. | |
368 | ||
369 | config NR_CPUS | |
2d8ae638 MN |
370 | int "Maximum number of CPUs (2-8192)" |
371 | range 2 8192 | |
a0ae9c7c AB |
372 | depends on SMP |
373 | default "32" if PPC64 | |
374 | default "4" | |
375 | ||
376 | config NOT_COHERENT_CACHE | |
377 | bool | |
b91a143b | 378 | depends on 4xx || 8xx || E200 || PPC_MPC512x || GAMECUBE_COMMON |
e7f75ad0 | 379 | default n if PPC_47x |
a0ae9c7c AB |
380 | default y |
381 | ||
f8eb77d6 | 382 | config CHECK_CACHE_COHERENCY |
a0ae9c7c AB |
383 | bool |
384 | ||
385 | endmenu |