Commit | Line | Data |
---|---|---|
a0ae9c7c AB |
1 | config PPC64 |
2 | bool "64-bit kernel" | |
3 | default n | |
b952741c | 4 | select HAVE_VIRT_CPU_ACCOUNTING |
a0ae9c7c AB |
5 | help |
6 | This option selects whether a 32-bit or a 64-bit kernel | |
7 | will be built. | |
8 | ||
9 | menu "Processor support" | |
10 | choice | |
11 | prompt "Processor Type" | |
12 | depends on PPC32 | |
a0ae9c7c | 13 | help |
b9fd305d AB |
14 | There are five families of 32 bit PowerPC chips supported. |
15 | The most common ones are the desktop and server CPUs (601, 603, | |
16 | 604, 740, 750, 74xx) CPUs from Freescale and IBM, with their | |
e177edcd | 17 | embedded 512x/52xx/82xx/83xx/86xx counterparts. |
b9fd305d AB |
18 | The other embeeded parts, namely 4xx, 8xx, e200 (55xx) and e500 |
19 | (85xx) each form a family of their own that is not compatible | |
20 | with the others. | |
21 | ||
22 | If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx. | |
23 | ||
48c93112 | 24 | config PPC_BOOK3S_32 |
e177edcd | 25 | bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx" |
a0ae9c7c AB |
26 | select PPC_FPU |
27 | ||
a0ae9c7c AB |
28 | config PPC_85xx |
29 | bool "Freescale 85xx" | |
30 | select E500 | |
a0ae9c7c | 31 | |
a0ae9c7c AB |
32 | config PPC_8xx |
33 | bool "Freescale 8xx" | |
34 | select FSL_SOC | |
35 | select 8xx | |
1088a209 | 36 | select PPC_LIB_RHEAP |
a0ae9c7c AB |
37 | |
38 | config 40x | |
39 | bool "AMCC 40x" | |
40 | select PPC_DCR_NATIVE | |
9dae8afd | 41 | select PPC_UDBG_16550 |
93173ce2 | 42 | select 4xx_SOC |
b500563b | 43 | select PPC_PCI_CHOICE |
a0ae9c7c AB |
44 | |
45 | config 44x | |
e7f75ad0 | 46 | bool "AMCC 44x, 46x or 47x" |
a0ae9c7c | 47 | select PPC_DCR_NATIVE |
1d5499b5 | 48 | select PPC_UDBG_16550 |
93173ce2 | 49 | select 4xx_SOC |
b500563b | 50 | select PPC_PCI_CHOICE |
4ee7084e | 51 | select PHYS_64BIT |
a0ae9c7c AB |
52 | |
53 | config E200 | |
54 | bool "Freescale e200" | |
55 | ||
56 | endchoice | |
57 | ||
2d27cfd3 BH |
58 | choice |
59 | prompt "Processor Type" | |
5b7c3c91 | 60 | depends on PPC64 |
2d27cfd3 BH |
61 | help |
62 | There are two families of 64 bit PowerPC chips supported. | |
63 | The most common ones are the desktop and server CPUs | |
64 | (POWER3, RS64, POWER4, POWER5, POWER5+, POWER6, ...) | |
65 | ||
66 | The other are the "embedded" processors compliant with the | |
67 | "Book 3E" variant of the architecture | |
68 | ||
69 | config PPC_BOOK3S_64 | |
70 | bool "Server processors" | |
5b7c3c91 | 71 | select PPC_FPU |
5adfd346 | 72 | select PPC_HAVE_PMU_SUPPORT |
41151e77 | 73 | select SYS_SUPPORTS_HUGETLBFS |
074c2eae | 74 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE if PPC_64K_PAGES |
c34a51ce | 75 | select ARCH_SUPPORTS_NUMA_BALANCING |
527518f1 | 76 | select IRQ_WORK |
5b7c3c91 | 77 | |
2d27cfd3 BH |
78 | config PPC_BOOK3E_64 |
79 | bool "Embedded processors" | |
80 | select PPC_FPU # Make it a choice ? | |
1ece355b | 81 | select PPC_SMP_MUXED_IPI |
440bc685 | 82 | select PPC_DOORBELL |
2d27cfd3 BH |
83 | |
84 | endchoice | |
85 | ||
d23c6fb4 AB |
86 | choice |
87 | prompt "CPU selection" | |
88 | depends on PPC64 | |
89 | default GENERIC_CPU | |
90 | help | |
91 | This will create a kernel which is optimised for a particular CPU. | |
92 | The resulting kernel may not run on other CPUs, so use this with care. | |
93 | ||
94 | If unsure, select Generic. | |
95 | ||
96 | config GENERIC_CPU | |
97 | bool "Generic" | |
686245be | 98 | depends on !CPU_LITTLE_ENDIAN |
d23c6fb4 AB |
99 | |
100 | config CELL_CPU | |
101 | bool "Cell Broadband Engine" | |
686245be | 102 | depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN |
d23c6fb4 AB |
103 | |
104 | config POWER4_CPU | |
105 | bool "POWER4" | |
686245be | 106 | depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN |
d23c6fb4 AB |
107 | |
108 | config POWER5_CPU | |
109 | bool "POWER5" | |
686245be | 110 | depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN |
d23c6fb4 AB |
111 | |
112 | config POWER6_CPU | |
113 | bool "POWER6" | |
686245be | 114 | depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN |
d23c6fb4 AB |
115 | |
116 | config POWER7_CPU | |
117 | bool "POWER7" | |
01718ba6 SW |
118 | depends on PPC_BOOK3S_64 |
119 | ||
120 | config E5500_CPU | |
121 | bool "Freescale e5500" | |
122 | depends on E500 | |
123 | ||
124 | config E6500_CPU | |
125 | bool "Freescale e6500" | |
126 | depends on E500 | |
d23c6fb4 AB |
127 | |
128 | endchoice | |
129 | ||
48c93112 BH |
130 | config PPC_BOOK3S |
131 | def_bool y | |
132 | depends on PPC_BOOK3S_32 || PPC_BOOK3S_64 | |
28794d34 | 133 | |
2d27cfd3 BH |
134 | config PPC_BOOK3E |
135 | def_bool y | |
136 | depends on PPC_BOOK3E_64 | |
137 | ||
5b7c3c91 BH |
138 | config 6xx |
139 | def_bool y | |
140 | depends on PPC32 && PPC_BOOK3S | |
7325927e | 141 | select PPC_HAVE_PMU_SUPPORT |
5b7c3c91 | 142 | |
a0ae9c7c | 143 | config POWER4 |
28794d34 | 144 | depends on PPC64 && PPC_BOOK3S |
a0ae9c7c AB |
145 | def_bool y |
146 | ||
3164cccd AB |
147 | config TUNE_CELL |
148 | bool "Optimize for Cell Broadband Engine" | |
28794d34 | 149 | depends on PPC64 && PPC_BOOK3S |
3164cccd AB |
150 | help |
151 | Cause the compiler to optimize for the PPE of the Cell Broadband | |
152 | Engine. This will make the code run considerably faster on Cell | |
153 | but somewhat slower on other machines. This option only changes | |
154 | the scheduling of instructions, not the selection of instructions | |
155 | itself, so the resulting kernel will keep running on all other | |
ff2d7587 | 156 | machines. |
3164cccd | 157 | |
a0ae9c7c AB |
158 | # this is temp to handle compat with arch=ppc |
159 | config 8xx | |
160 | bool | |
161 | ||
a0ae9c7c | 162 | config E500 |
39aef685 | 163 | select FSL_EMB_PERFMON |
4490c06b | 164 | select PPC_FSL_BOOK3E |
a0ae9c7c AB |
165 | bool |
166 | ||
3dfa8773 KG |
167 | config PPC_E500MC |
168 | bool "e500mc Support" | |
169 | select PPC_FPU | |
555eae97 | 170 | select COMMON_CLK |
3dfa8773 | 171 | depends on E500 |
9653018b SW |
172 | help |
173 | This must be enabled for running on e500mc (and derivatives | |
174 | such as e5500/e6500), and must be disabled for running on | |
175 | e500v1 or e500v2. | |
3dfa8773 | 176 | |
a0ae9c7c AB |
177 | config PPC_FPU |
178 | bool | |
179 | default y if PPC64 | |
180 | ||
5753c082 KG |
181 | config FSL_EMB_PERFMON |
182 | bool "Freescale Embedded Perfmon" | |
183 | depends on E500 || PPC_83xx | |
184 | help | |
185 | This is the Performance Monitor support found on the e500 core | |
186 | and some e300 cores (c3 and c4). Select this only if your | |
187 | core supports the Embedded Performance Monitor APU | |
188 | ||
a1110654 SW |
189 | config FSL_EMB_PERF_EVENT |
190 | bool | |
191 | depends on FSL_EMB_PERFMON && PERF_EVENTS && !PPC_PERF_CTRS | |
192 | default y | |
193 | ||
194 | config FSL_EMB_PERF_EVENT_E500 | |
195 | bool | |
196 | depends on FSL_EMB_PERF_EVENT && E500 | |
197 | default y | |
198 | ||
a0ae9c7c AB |
199 | config 4xx |
200 | bool | |
201 | depends on 40x || 44x | |
202 | default y | |
203 | ||
204 | config BOOKE | |
205 | bool | |
2d27cfd3 | 206 | depends on E200 || E500 || 44x || PPC_BOOK3E |
a0ae9c7c AB |
207 | default y |
208 | ||
209 | config FSL_BOOKE | |
210 | bool | |
4490c06b | 211 | depends on (E200 || E500) && PPC32 |
a0ae9c7c AB |
212 | default y |
213 | ||
4490c06b KG |
214 | # this is for common code between PPC32 & PPC64 FSL BOOKE |
215 | config PPC_FSL_BOOK3E | |
216 | bool | |
217 | select FSL_EMB_PERFMON | |
1ece355b | 218 | select PPC_SMP_MUXED_IPI |
a475c8ec | 219 | select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64 |
440bc685 | 220 | select PPC_DOORBELL |
4490c06b | 221 | default y if FSL_BOOKE |
39aef685 | 222 | |
a0ae9c7c AB |
223 | config PTE_64BIT |
224 | bool | |
4ee7084e BB |
225 | depends on 44x || E500 || PPC_86xx |
226 | default y if PHYS_64BIT | |
a0ae9c7c AB |
227 | |
228 | config PHYS_64BIT | |
4ee7084e BB |
229 | bool 'Large physical address support' if E500 || PPC_86xx |
230 | depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx | |
a0ae9c7c AB |
231 | ---help--- |
232 | This option enables kernel support for larger than 32-bit physical | |
4ee7084e BB |
233 | addresses. This feature may not be available on all cores. |
234 | ||
235 | If you have more than 3.5GB of RAM or so, you also need to enable | |
236 | SWIOTLB under Kernel Options for this to work. The actual number | |
237 | is platform-dependent. | |
a0ae9c7c AB |
238 | |
239 | If in doubt, say N here. | |
240 | ||
241 | config ALTIVEC | |
242 | bool "AltiVec Support" | |
cd66cc2e | 243 | depends on 6xx || POWER4 || (PPC_E500MC && PPC64) |
a0ae9c7c AB |
244 | ---help--- |
245 | This option enables kernel support for the Altivec extensions to the | |
246 | PowerPC processor. The kernel currently supports saving and restoring | |
247 | altivec registers, and turning on the 'altivec enable' bit so user | |
248 | processes can execute altivec instructions. | |
249 | ||
250 | This option is only usefully if you have a processor that supports | |
251 | altivec (G4, otherwise known as 74xx series), but does not have | |
252 | any affect on a non-altivec cpu (it does, however add code to the | |
253 | kernel). | |
254 | ||
255 | If in doubt, say Y here. | |
256 | ||
96d5b52c MN |
257 | config VSX |
258 | bool "VSX Support" | |
259 | depends on POWER4 && ALTIVEC && PPC_FPU | |
260 | ---help--- | |
261 | ||
262 | This option enables kernel support for the Vector Scaler extensions | |
263 | to the PowerPC processor. The kernel currently supports saving and | |
264 | restoring VSX registers, and turning on the 'VSX enable' bit so user | |
265 | processes can execute VSX instructions. | |
266 | ||
267 | This option is only useful if you have a processor that supports | |
268 | VSX (P7 and above), but does not have any affect on a non-VSX | |
269 | CPUs (it does, however add code to the kernel). | |
270 | ||
271 | If in doubt, say Y here. | |
272 | ||
851d2e2f THFL |
273 | config PPC_ICSWX |
274 | bool "Support for PowerPC icswx coprocessor instruction" | |
fb5a5157 | 275 | depends on POWER4 |
851d2e2f THFL |
276 | default n |
277 | ---help--- | |
278 | ||
279 | This option enables kernel support for the PowerPC Initiate | |
280 | Coprocessor Store Word (icswx) coprocessor instruction on POWER7 | |
281 | or newer processors. | |
282 | ||
283 | This option is only useful if you have a processor that supports | |
284 | the icswx coprocessor instruction. It does not have any effect | |
285 | on processors without the icswx coprocessor instruction. | |
286 | ||
287 | This option slightly increases kernel memory usage. | |
288 | ||
289 | If in doubt, say N here. | |
290 | ||
9d670280 JX |
291 | config PPC_ICSWX_PID |
292 | bool "icswx requires direct PID management" | |
293 | depends on PPC_ICSWX && POWER4 | |
294 | default y | |
295 | ---help--- | |
c3dcf53a | 296 | The PID register in server is used explicitly for ICSWX. In |
6b2aac42 | 297 | embedded systems PID management is done by the system. |
9d670280 | 298 | |
c3dcf53a JX |
299 | config PPC_ICSWX_USE_SIGILL |
300 | bool "Should a bad CT cause a SIGILL?" | |
301 | depends on PPC_ICSWX | |
302 | default n | |
303 | ---help--- | |
304 | Should a bad CT used for "non-record form ICSWX" cause an | |
6b2aac42 | 305 | illegal instruction signal or should it be silent as |
c3dcf53a JX |
306 | architected. |
307 | ||
308 | If in doubt, say N here. | |
309 | ||
a0ae9c7c AB |
310 | config SPE |
311 | bool "SPE Support" | |
3dfa8773 | 312 | depends on E200 || (E500 && !PPC_E500MC) |
a0ae9c7c AB |
313 | default y |
314 | ---help--- | |
315 | This option enables kernel support for the Signal Processing | |
316 | Extensions (SPE) to the PowerPC processor. The kernel currently | |
317 | supports saving and restoring SPE registers, and turning on the | |
318 | 'spe enable' bit so user processes can execute SPE instructions. | |
319 | ||
320 | This option is only useful if you have a processor that supports | |
321 | SPE (e500, otherwise known as 85xx series), but does not have any | |
322 | effect on a non-spe cpu (it does, however add code to the kernel). | |
323 | ||
324 | If in doubt, say Y here. | |
325 | ||
326 | config PPC_STD_MMU | |
5b7c3c91 BH |
327 | def_bool y |
328 | depends on PPC_BOOK3S | |
a0ae9c7c AB |
329 | |
330 | config PPC_STD_MMU_32 | |
331 | def_bool y | |
332 | depends on PPC_STD_MMU && PPC32 | |
333 | ||
5e696617 BH |
334 | config PPC_STD_MMU_64 |
335 | def_bool y | |
336 | depends on PPC_STD_MMU && PPC64 | |
337 | ||
338 | config PPC_MMU_NOHASH | |
339 | def_bool y | |
340 | depends on !PPC_STD_MMU | |
341 | ||
70fe3af8 KG |
342 | config PPC_BOOK3E_MMU |
343 | def_bool y | |
2d27cfd3 | 344 | depends on FSL_BOOKE || PPC_BOOK3E |
70fe3af8 | 345 | |
a0ae9c7c AB |
346 | config PPC_MM_SLICES |
347 | bool | |
a475c8ec | 348 | default y if (!PPC_FSL_BOOK3E && PPC64 && HUGETLB_PAGE) || (PPC_STD_MMU_64 && PPC_64K_PAGES) |
a0ae9c7c AB |
349 | default n |
350 | ||
105988c0 PM |
351 | config PPC_HAVE_PMU_SUPPORT |
352 | bool | |
353 | ||
354 | config PPC_PERF_CTRS | |
355 | def_bool y | |
cdd6c482 | 356 | depends on PERF_EVENTS && PPC_HAVE_PMU_SUPPORT |
105988c0 | 357 | help |
cdd6c482 | 358 | This enables the powerpc-specific perf_event back-end. |
105988c0 | 359 | |
a0ae9c7c | 360 | config SMP |
e7f75ad0 | 361 | depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE || PPC_47x |
a0ae9c7c AB |
362 | bool "Symmetric multi-processing support" |
363 | ---help--- | |
364 | This enables support for systems with more than one CPU. If you have | |
365 | a system with only one CPU, say N. If you have a system with more | |
366 | than one CPU, say Y. Note that the kernel does not currently | |
367 | support SMP machines with 603/603e/603ev or PPC750 ("G3") processors | |
368 | since they have inadequate hardware support for multiprocessor | |
369 | operation. | |
370 | ||
371 | If you say N here, the kernel will run on single and multiprocessor | |
372 | machines, but will use only one CPU of a multiprocessor machine. If | |
373 | you say Y here, the kernel will run on single-processor machines. | |
374 | On a single-processor machine, the kernel will run faster if you say | |
375 | N here. | |
376 | ||
377 | If you don't know what to do here, say N. | |
378 | ||
379 | config NR_CPUS | |
2d8ae638 MN |
380 | int "Maximum number of CPUs (2-8192)" |
381 | range 2 8192 | |
a0ae9c7c AB |
382 | depends on SMP |
383 | default "32" if PPC64 | |
384 | default "4" | |
385 | ||
386 | config NOT_COHERENT_CACHE | |
387 | bool | |
b91a143b | 388 | depends on 4xx || 8xx || E200 || PPC_MPC512x || GAMECUBE_COMMON |
e7f75ad0 | 389 | default n if PPC_47x |
a0ae9c7c AB |
390 | default y |
391 | ||
f8eb77d6 | 392 | config CHECK_CACHE_COHERENCY |
a0ae9c7c AB |
393 | bool |
394 | ||
440bc685 IM |
395 | config PPC_DOORBELL |
396 | bool | |
397 | default n | |
398 | ||
a0ae9c7c | 399 | endmenu |
7c105b63 | 400 | |
962bc221 AB |
401 | choice |
402 | prompt "Endianness selection" | |
403 | default CPU_BIG_ENDIAN | |
7c105b63 AB |
404 | help |
405 | This option selects whether a big endian or little endian kernel will | |
406 | be built. | |
407 | ||
962bc221 AB |
408 | config CPU_BIG_ENDIAN |
409 | bool "Build big endian kernel" | |
410 | help | |
411 | Build a big endian kernel. | |
412 | ||
413 | If unsure, select this option. | |
414 | ||
415 | config CPU_LITTLE_ENDIAN | |
416 | bool "Build little endian kernel" | |
147c0516 | 417 | select PPC64_BOOT_WRAPPER |
962bc221 AB |
418 | help |
419 | Build a little endian kernel. | |
420 | ||
7c105b63 AB |
421 | Note that if cross compiling a little endian kernel, |
422 | CROSS_COMPILE must point to a toolchain capable of targeting | |
423 | little endian powerpc. | |
962bc221 AB |
424 | |
425 | endchoice | |
147c0516 CLG |
426 | |
427 | config PPC64_BOOT_WRAPPER | |
428 | def_bool n | |
429 | depends on CPU_LITTLE_ENDIAN |