[deliverable/linux.git] / arch / powerpc / platforms / Kconfig.cputype

config PPC64
	bool "64-bit kernel"
	default n
	help
	  This option selects whether a 32-bit or a 64-bit kernel
	  will be built.

menu "Processor support"
choice
	prompt "Processor Type"
	depends on PPC32
	help
	  There are five families of 32 bit PowerPC chips supported.
	  The most common ones are the desktop and server CPUs (601, 603,
	  604, 740, 750, 74xx) CPUs from Freescale and IBM, with their
	  embedded 512x/52xx/82xx/83xx/86xx counterparts.
	  The other embeeded parts, namely 4xx, 8xx, e200 (55xx) and e500
	  (85xx) each form a family of their own that is not compatible
	  with the others.

	  If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx.

config PPC_BOOK3S_32
	bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx"
	select PPC_FPU

config PPC_85xx
	bool "Freescale 85xx"
	select E500

config PPC_8xx
	bool "Freescale 8xx"
	select FSL_SOC
	select 8xx
	select PPC_LIB_RHEAP

config 40x
	bool "AMCC 40x"
	select PPC_DCR_NATIVE
	select PPC_UDBG_16550
	select 4xx_SOC
	select PPC_PCI_CHOICE

config 44x
	bool "AMCC 44x, 46x or 47x"
	select PPC_DCR_NATIVE
	select PPC_UDBG_16550
	select 4xx_SOC
	select PPC_PCI_CHOICE
	select PHYS_64BIT

config E200
	bool "Freescale e200"

endchoice

choice
	prompt "Processor Type"
	depends on PPC64
	help
	  There are two families of 64 bit PowerPC chips supported.
	  The most common ones are the desktop and server CPUs
	  (POWER3, RS64, POWER4, POWER5, POWER5+, POWER6, ...)

	  The other are the "embedded" processors compliant with the
	  "Book 3E" variant of the architecture

config PPC_BOOK3S_64
	bool "Server processors"
	select PPC_FPU
	select PPC_HAVE_PMU_SUPPORT
	select SYS_SUPPORTS_HUGETLBFS

config PPC_BOOK3E_64
	bool "Embedded processors"
	select PPC_FPU # Make it a choice ?
	select PPC_SMP_MUXED_IPI

endchoice

config PPC_BOOK3S
	def_bool y
	depends on PPC_BOOK3S_32 || PPC_BOOK3S_64

config PPC_BOOK3E
	def_bool y
	depends on PPC_BOOK3E_64

config POWER4_ONLY
	bool "Optimize for POWER4"
	depends on PPC64 && PPC_BOOK3S
	default n
	---help---
	  Cause the compiler to optimize for POWER4/POWER5/PPC970 processors.
	  The resulting binary will not work on POWER3 or RS64 processors
	  when compiled with binutils 2.15 or later.

config 6xx
	def_bool y
	depends on PPC32 && PPC_BOOK3S
	select PPC_HAVE_PMU_SUPPORT

config POWER3
	bool
	depends on PPC64 && PPC_BOOK3S
	default y if !POWER4_ONLY

config POWER4
	depends on PPC64 && PPC_BOOK3S
	def_bool y

config PPC_A2
	bool
	depends on PPC_BOOK3E_64

config TUNE_CELL
	bool "Optimize for Cell Broadband Engine"
	depends on PPC64 && PPC_BOOK3S
	help
	  Cause the compiler to optimize for the PPE of the Cell Broadband
	  Engine. This will make the code run considerably faster on Cell
	  but somewhat slower on other machines. This option only changes
	  the scheduling of instructions, not the selection of instructions
	  itself, so the resulting kernel will keep running on all other
	  machines. When building a kernel that is supposed to run only
	  on Cell, you should also select the POWER4_ONLY option.

# this is temp to handle compat with arch=ppc
config 8xx
	bool

config E500
	select FSL_EMB_PERFMON
	select PPC_FSL_BOOK3E
	bool

config PPC_E500MC
	bool "e500mc Support"
	select PPC_FPU
	depends on E500

config PPC_FPU
	bool
	default y if PPC64

config FSL_EMB_PERFMON
	bool "Freescale Embedded Perfmon"
	depends on E500 || PPC_83xx
	help
	  This is the Performance Monitor support found on the e500 core
	  and some e300 cores (c3 and c4).  Select this only if your
	  core supports the Embedded Performance Monitor APU

config FSL_EMB_PERF_EVENT
	bool
	depends on FSL_EMB_PERFMON && PERF_EVENTS && !PPC_PERF_CTRS
	default y

config FSL_EMB_PERF_EVENT_E500
	bool
	depends on FSL_EMB_PERF_EVENT && E500
	default y

config 4xx
	bool
	depends on 40x || 44x
	default y

config BOOKE
	bool
	depends on E200 || E500 || 44x || PPC_BOOK3E
	default y

config FSL_BOOKE
	bool
	depends on (E200 || E500) && PPC32
	select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT
	default y

# this is for common code between PPC32 & PPC64 FSL BOOKE
config PPC_FSL_BOOK3E
	bool
	select FSL_EMB_PERFMON
	select PPC_SMP_MUXED_IPI
	default y if FSL_BOOKE

config PTE_64BIT
	bool
	depends on 44x || E500 || PPC_86xx
	default y if PHYS_64BIT

config PHYS_64BIT
	bool 'Large physical address support' if E500 || PPC_86xx
	depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx
	---help---
	  This option enables kernel support for larger than 32-bit physical
	  addresses.  This feature may not be available on all cores.

	  If you have more than 3.5GB of RAM or so, you also need to enable
	  SWIOTLB under Kernel Options for this to work.  The actual number
	  is platform-dependent.

	  If in doubt, say N here.

config ALTIVEC
	bool "AltiVec Support"
	depends on 6xx || POWER4
	---help---
	  This option enables kernel support for the Altivec extensions to the
	  PowerPC processor. The kernel currently supports saving and restoring
	  altivec registers, and turning on the 'altivec enable' bit so user
	  processes can execute altivec instructions.

	  This option is only usefully if you have a processor that supports
	  altivec (G4, otherwise known as 74xx series), but does not have
	  any affect on a non-altivec cpu (it does, however add code to the
	  kernel).

	  If in doubt, say Y here.

config VSX
	bool "VSX Support"
	depends on POWER4 && ALTIVEC && PPC_FPU
	---help---

	  This option enables kernel support for the Vector Scaler extensions
	  to the PowerPC processor. The kernel currently supports saving and
	  restoring VSX registers, and turning on the 'VSX enable' bit so user
	  processes can execute VSX instructions.

	  This option is only useful if you have a processor that supports
	  VSX (P7 and above), but does not have any affect on a non-VSX
	  CPUs (it does, however add code to the kernel).

	  If in doubt, say Y here.

config PPC_ICSWX
	bool "Support for PowerPC icswx coprocessor instruction"
	depends on POWER4
	default n
	---help---

	  This option enables kernel support for the PowerPC Initiate
	  Coprocessor Store Word (icswx) coprocessor instruction on POWER7
	  or newer processors.

	  This option is only useful if you have a processor that supports
	  the icswx coprocessor instruction. It does not have any effect
	  on processors without the icswx coprocessor instruction.

	  This option slightly increases kernel memory usage.

	  If in doubt, say N here.

config PPC_ICSWX_PID
	bool "icswx requires direct PID management"
	depends on PPC_ICSWX && POWER4
	default y
	---help---
	  PID register in server is used explicitly for ICSWX.  In
	  embedded systems PID managment is done by the system.

config SPE
	bool "SPE Support"
	depends on E200 || (E500 && !PPC_E500MC)
	default y
	---help---
	  This option enables kernel support for the Signal Processing
	  Extensions (SPE) to the PowerPC processor. The kernel currently
	  supports saving and restoring SPE registers, and turning on the
	  'spe enable' bit so user processes can execute SPE instructions.

	  This option is only useful if you have a processor that supports
	  SPE (e500, otherwise known as 85xx series), but does not have any
	  effect on a non-spe cpu (it does, however add code to the kernel).

	  If in doubt, say Y here.

config PPC_STD_MMU
	def_bool y
	depends on PPC_BOOK3S

config PPC_STD_MMU_32
	def_bool y
	depends on PPC_STD_MMU && PPC32

config PPC_STD_MMU_64
	def_bool y
	depends on PPC_STD_MMU && PPC64

config PPC_MMU_NOHASH
	def_bool y
	depends on !PPC_STD_MMU

config PPC_BOOK3E_MMU
	def_bool y
	depends on FSL_BOOKE || PPC_BOOK3E

config PPC_MM_SLICES
	bool
	default y if (PPC64 && HUGETLB_PAGE) || (PPC_STD_MMU_64 && PPC_64K_PAGES)
	default n

config VIRT_CPU_ACCOUNTING
	bool "Deterministic task and CPU time accounting"
	depends on PPC64
	default y
	help
	  Select this option to enable more accurate task and CPU time
	  accounting.  This is done by reading a CPU counter on each
	  kernel entry and exit and on transitions within the kernel
	  between system, softirq and hardirq state, so there is a
	  small performance impact.  This also enables accounting of
	  stolen time on logically-partitioned systems running on
	  IBM POWER5-based machines.

	  If in doubt, say Y here.

config PPC_HAVE_PMU_SUPPORT
       bool

config PPC_PERF_CTRS
       def_bool y
       depends on PERF_EVENTS && PPC_HAVE_PMU_SUPPORT
       help
         This enables the powerpc-specific perf_event back-end.

config SMP
	depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE || PPC_47x
	bool "Symmetric multi-processing support"
	---help---
	  This enables support for systems with more than one CPU. If you have
	  a system with only one CPU, say N. If you have a system with more
	  than one CPU, say Y.  Note that the kernel does not currently
	  support SMP machines with 603/603e/603ev or PPC750 ("G3") processors
	  since they have inadequate hardware support for multiprocessor
	  operation.

	  If you say N here, the kernel will run on single and multiprocessor
	  machines, but will use only one CPU of a multiprocessor machine. If
	  you say Y here, the kernel will run on single-processor machines.
	  On a single-processor machine, the kernel will run faster if you say
	  N here.

	  If you don't know what to do here, say N.

config NR_CPUS
	int "Maximum number of CPUs (2-8192)"
	range 2 8192
	depends on SMP
	default "32" if PPC64
	default "4"

config NOT_COHERENT_CACHE
	bool
	depends on 4xx || 8xx || E200 || PPC_MPC512x || GAMECUBE_COMMON
	default n if PPC_47x
	default y

config CHECK_CACHE_COHERENCY
	bool

endmenu
Commit	Line	Data
a0ae9c7c AB	1	config PPC64
	2	bool "64-bit kernel"
	3	default n
	4	help
	5	This option selects whether a 32-bit or a 64-bit kernel
	6	will be built.
	7
	8	menu "Processor support"
	9	choice
	10	prompt "Processor Type"
	11	depends on PPC32
a0ae9c7c	12	help
b9fd305d AB	13	There are five families of 32 bit PowerPC chips supported.
	14	The most common ones are the desktop and server CPUs (601, 603,
	15	604, 740, 750, 74xx) CPUs from Freescale and IBM, with their
e177edcd	16	embedded 512x/52xx/82xx/83xx/86xx counterparts.
b9fd305d AB	17	The other embeeded parts, namely 4xx, 8xx, e200 (55xx) and e500
	18	(85xx) each form a family of their own that is not compatible
	19	with the others.
	20
	21	If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx.
	22
48c93112	23	config PPC_BOOK3S_32
e177edcd	24	bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx"
a0ae9c7c AB	25	select PPC_FPU
a0ae9c7c AB	26
a0ae9c7c AB	27	config PPC_85xx
	28	bool "Freescale 85xx"
	29	select E500
a0ae9c7c	30
a0ae9c7c AB	31	config PPC_8xx
	32	bool "Freescale 8xx"
	33	select FSL_SOC
	34	select 8xx
1088a209	35	select PPC_LIB_RHEAP
a0ae9c7c AB	36
	37	config 40x
	38	bool "AMCC 40x"
	39	select PPC_DCR_NATIVE
9dae8afd	40	select PPC_UDBG_16550
93173ce2	41	select 4xx_SOC
b500563b	42	select PPC_PCI_CHOICE
a0ae9c7c AB	43
a0ae9c7c AB	44	config 44x
e7f75ad0	45	bool "AMCC 44x, 46x or 47x"
a0ae9c7c	46	select PPC_DCR_NATIVE
1d5499b5	47	select PPC_UDBG_16550
93173ce2	48	select 4xx_SOC
b500563b	49	select PPC_PCI_CHOICE
4ee7084e	50	select PHYS_64BIT
a0ae9c7c AB	51
	52	config E200
	53	bool "Freescale e200"
	54
	55	endchoice
	56
2d27cfd3 BH	57	choice
2d27cfd3 BH	58	prompt "Processor Type"
5b7c3c91	59	depends on PPC64
2d27cfd3 BH	60	help
	61	There are two families of 64 bit PowerPC chips supported.
	62	The most common ones are the desktop and server CPUs
	63	(POWER3, RS64, POWER4, POWER5, POWER5+, POWER6, ...)
	64
	65	The other are the "embedded" processors compliant with the
	66	"Book 3E" variant of the architecture
	67
	68	config PPC_BOOK3S_64
	69	bool "Server processors"
5b7c3c91	70	select PPC_FPU
5adfd346	71	select PPC_HAVE_PMU_SUPPORT
41151e77	72	select SYS_SUPPORTS_HUGETLBFS
5b7c3c91	73
2d27cfd3 BH	74	config PPC_BOOK3E_64
	75	bool "Embedded processors"
	76	select PPC_FPU # Make it a choice ?
1ece355b	77	select PPC_SMP_MUXED_IPI
2d27cfd3 BH	78
	79	endchoice
	80
48c93112 BH	81	config PPC_BOOK3S
	82	def_bool y
	83	depends on PPC_BOOK3S_32 \|\| PPC_BOOK3S_64
28794d34	84
2d27cfd3 BH	85	config PPC_BOOK3E
	86	def_bool y
	87	depends on PPC_BOOK3E_64
	88
a0ae9c7c AB	89	config POWER4_ONLY
a0ae9c7c AB	90	bool "Optimize for POWER4"
28794d34	91	depends on PPC64 && PPC_BOOK3S
a0ae9c7c AB	92	default n
	93	---help---
	94	Cause the compiler to optimize for POWER4/POWER5/PPC970 processors.
	95	The resulting binary will not work on POWER3 or RS64 processors
	96	when compiled with binutils 2.15 or later.
	97
5b7c3c91 BH	98	config 6xx
	99	def_bool y
	100	depends on PPC32 && PPC_BOOK3S
7325927e	101	select PPC_HAVE_PMU_SUPPORT
5b7c3c91	102
a0ae9c7c AB	103	config POWER3
a0ae9c7c AB	104	bool
28794d34	105	depends on PPC64 && PPC_BOOK3S
a0ae9c7c AB	106	default y if !POWER4_ONLY
	107
	108	config POWER4
28794d34	109	depends on PPC64 && PPC_BOOK3S
a0ae9c7c AB	110	def_bool y
a0ae9c7c AB	111
76b4eda8 BH	112	config PPC_A2
	113	bool
	114	depends on PPC_BOOK3E_64
	115
3164cccd AB	116	config TUNE_CELL
3164cccd AB	117	bool "Optimize for Cell Broadband Engine"
28794d34	118	depends on PPC64 && PPC_BOOK3S
3164cccd AB	119	help
	120	Cause the compiler to optimize for the PPE of the Cell Broadband
	121	Engine. This will make the code run considerably faster on Cell
	122	but somewhat slower on other machines. This option only changes
	123	the scheduling of instructions, not the selection of instructions
	124	itself, so the resulting kernel will keep running on all other
	125	machines. When building a kernel that is supposed to run only
	126	on Cell, you should also select the POWER4_ONLY option.
	127
a0ae9c7c AB	128	# this is temp to handle compat with arch=ppc
	129	config 8xx
	130	bool
	131
a0ae9c7c	132	config E500
39aef685	133	select FSL_EMB_PERFMON
4490c06b	134	select PPC_FSL_BOOK3E
a0ae9c7c AB	135	bool
a0ae9c7c AB	136
3dfa8773 KG	137	config PPC_E500MC
	138	bool "e500mc Support"
	139	select PPC_FPU
	140	depends on E500
	141
a0ae9c7c AB	142	config PPC_FPU
	143	bool
	144	default y if PPC64
	145
5753c082 KG	146	config FSL_EMB_PERFMON
	147	bool "Freescale Embedded Perfmon"
	148	depends on E500 \|\| PPC_83xx
	149	help
	150	This is the Performance Monitor support found on the e500 core
	151	and some e300 cores (c3 and c4). Select this only if your
	152	core supports the Embedded Performance Monitor APU
	153
a1110654 SW	154	config FSL_EMB_PERF_EVENT
	155	bool
	156	depends on FSL_EMB_PERFMON && PERF_EVENTS && !PPC_PERF_CTRS
	157	default y
	158
	159	config FSL_EMB_PERF_EVENT_E500
	160	bool
	161	depends on FSL_EMB_PERF_EVENT && E500
	162	default y
	163
a0ae9c7c AB	164	config 4xx
	165	bool
	166	depends on 40x \|\| 44x
	167	default y
	168
	169	config BOOKE
	170	bool
2d27cfd3	171	depends on E200 \|\| E500 \|\| 44x \|\| PPC_BOOK3E
a0ae9c7c AB	172	default y
	173
	174	config FSL_BOOKE
	175	bool
4490c06b	176	depends on (E200 \|\| E500) && PPC32
41151e77	177	select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT
a0ae9c7c AB	178	default y
a0ae9c7c AB	179
4490c06b KG	180	# this is for common code between PPC32 & PPC64 FSL BOOKE
	181	config PPC_FSL_BOOK3E
	182	bool
	183	select FSL_EMB_PERFMON
1ece355b	184	select PPC_SMP_MUXED_IPI
4490c06b	185	default y if FSL_BOOKE
39aef685	186
a0ae9c7c AB	187	config PTE_64BIT
a0ae9c7c AB	188	bool
4ee7084e BB	189	depends on 44x \|\| E500 \|\| PPC_86xx
4ee7084e BB	190	default y if PHYS_64BIT
a0ae9c7c AB	191
a0ae9c7c AB	192	config PHYS_64BIT
4ee7084e BB	193	bool 'Large physical address support' if E500 \|\| PPC_86xx
4ee7084e BB	194	depends on (44x \|\| E500 \|\| PPC_86xx) && !PPC_83xx && !PPC_82xx
a0ae9c7c AB	195	---help---
a0ae9c7c AB	196	This option enables kernel support for larger than 32-bit physical
4ee7084e BB	197	addresses. This feature may not be available on all cores.
	198
	199	If you have more than 3.5GB of RAM or so, you also need to enable
	200	SWIOTLB under Kernel Options for this to work. The actual number
	201	is platform-dependent.
a0ae9c7c AB	202
	203	If in doubt, say N here.
	204
	205	config ALTIVEC
	206	bool "AltiVec Support"
28794d34	207	depends on 6xx \|\| POWER4
a0ae9c7c AB	208	---help---
	209	This option enables kernel support for the Altivec extensions to the
	210	PowerPC processor. The kernel currently supports saving and restoring
	211	altivec registers, and turning on the 'altivec enable' bit so user
	212	processes can execute altivec instructions.
	213
	214	This option is only usefully if you have a processor that supports
	215	altivec (G4, otherwise known as 74xx series), but does not have
	216	any affect on a non-altivec cpu (it does, however add code to the
	217	kernel).
	218
	219	If in doubt, say Y here.
	220
96d5b52c MN	221	config VSX
	222	bool "VSX Support"
	223	depends on POWER4 && ALTIVEC && PPC_FPU
	224	---help---
	225
	226	This option enables kernel support for the Vector Scaler extensions
	227	to the PowerPC processor. The kernel currently supports saving and
	228	restoring VSX registers, and turning on the 'VSX enable' bit so user
	229	processes can execute VSX instructions.
	230
	231	This option is only useful if you have a processor that supports
	232	VSX (P7 and above), but does not have any affect on a non-VSX
	233	CPUs (it does, however add code to the kernel).
	234
	235	If in doubt, say Y here.
	236
851d2e2f THFL	237	config PPC_ICSWX
	238	bool "Support for PowerPC icswx coprocessor instruction"
	239	depends on POWER4
	240	default n
	241	---help---
	242
	243	This option enables kernel support for the PowerPC Initiate
	244	Coprocessor Store Word (icswx) coprocessor instruction on POWER7
	245	or newer processors.
	246
	247	This option is only useful if you have a processor that supports
	248	the icswx coprocessor instruction. It does not have any effect
	249	on processors without the icswx coprocessor instruction.
	250
	251	This option slightly increases kernel memory usage.
	252
	253	If in doubt, say N here.
	254
9d670280 JX	255	config PPC_ICSWX_PID
	256	bool "icswx requires direct PID management"
	257	depends on PPC_ICSWX && POWER4
	258	default y
	259	---help---
	260	PID register in server is used explicitly for ICSWX. In
	261	embedded systems PID managment is done by the system.
	262
a0ae9c7c AB	263	config SPE
a0ae9c7c AB	264	bool "SPE Support"
3dfa8773	265	depends on E200 \|\| (E500 && !PPC_E500MC)
a0ae9c7c AB	266	default y
	267	---help---
	268	This option enables kernel support for the Signal Processing
	269	Extensions (SPE) to the PowerPC processor. The kernel currently
	270	supports saving and restoring SPE registers, and turning on the
	271	'spe enable' bit so user processes can execute SPE instructions.
	272
	273	This option is only useful if you have a processor that supports
	274	SPE (e500, otherwise known as 85xx series), but does not have any
	275	effect on a non-spe cpu (it does, however add code to the kernel).
	276
	277	If in doubt, say Y here.
	278
	279	config PPC_STD_MMU
5b7c3c91 BH	280	def_bool y
5b7c3c91 BH	281	depends on PPC_BOOK3S
a0ae9c7c AB	282
	283	config PPC_STD_MMU_32
	284	def_bool y
	285	depends on PPC_STD_MMU && PPC32
	286
5e696617 BH	287	config PPC_STD_MMU_64
	288	def_bool y
	289	depends on PPC_STD_MMU && PPC64
	290
	291	config PPC_MMU_NOHASH
	292	def_bool y
	293	depends on !PPC_STD_MMU
	294
70fe3af8 KG	295	config PPC_BOOK3E_MMU
70fe3af8 KG	296	def_bool y
2d27cfd3	297	depends on FSL_BOOKE \|\| PPC_BOOK3E
70fe3af8	298
a0ae9c7c AB	299	config PPC_MM_SLICES
a0ae9c7c AB	300	bool
41151e77	301	default y if (PPC64 && HUGETLB_PAGE) \|\| (PPC_STD_MMU_64 && PPC_64K_PAGES)
a0ae9c7c AB	302	default n
	303
	304	config VIRT_CPU_ACCOUNTING
	305	bool "Deterministic task and CPU time accounting"
	306	depends on PPC64
	307	default y
	308	help
	309	Select this option to enable more accurate task and CPU time
	310	accounting. This is done by reading a CPU counter on each
	311	kernel entry and exit and on transitions within the kernel
	312	between system, softirq and hardirq state, so there is a
	313	small performance impact. This also enables accounting of
	314	stolen time on logically-partitioned systems running on
	315	IBM POWER5-based machines.
	316
	317	If in doubt, say Y here.
	318
105988c0 PM	319	config PPC_HAVE_PMU_SUPPORT
	320	bool
	321
	322	config PPC_PERF_CTRS
	323	def_bool y
cdd6c482	324	depends on PERF_EVENTS && PPC_HAVE_PMU_SUPPORT
105988c0	325	help
cdd6c482	326	This enables the powerpc-specific perf_event back-end.
105988c0	327
a0ae9c7c	328	config SMP
e7f75ad0	329	depends on PPC_BOOK3S \|\| PPC_BOOK3E \|\| FSL_BOOKE \|\| PPC_47x
a0ae9c7c AB	330	bool "Symmetric multi-processing support"
	331	---help---
	332	This enables support for systems with more than one CPU. If you have
	333	a system with only one CPU, say N. If you have a system with more
	334	than one CPU, say Y. Note that the kernel does not currently
	335	support SMP machines with 603/603e/603ev or PPC750 ("G3") processors
	336	since they have inadequate hardware support for multiprocessor
	337	operation.
	338
	339	If you say N here, the kernel will run on single and multiprocessor
	340	machines, but will use only one CPU of a multiprocessor machine. If
	341	you say Y here, the kernel will run on single-processor machines.
	342	On a single-processor machine, the kernel will run faster if you say
	343	N here.
	344
	345	If you don't know what to do here, say N.
	346
	347	config NR_CPUS
2d8ae638 MN	348	int "Maximum number of CPUs (2-8192)"
2d8ae638 MN	349	range 2 8192
a0ae9c7c AB	350	depends on SMP
	351	default "32" if PPC64
	352	default "4"
	353
	354	config NOT_COHERENT_CACHE
	355	bool
b91a143b	356	depends on 4xx \|\| 8xx \|\| E200 \|\| PPC_MPC512x \|\| GAMECUBE_COMMON
e7f75ad0	357	default n if PPC_47x
a0ae9c7c AB	358	default y
a0ae9c7c AB	359
f8eb77d6	360	config CHECK_CACHE_COHERENCY
a0ae9c7c AB	361	bool
	362
	363	endmenu