[deliverable/linux.git] / arch / powerpc / platforms / cell / Kconfig

config PPC_CELL
	bool
	default n

config PPC_CELL_COMMON
	bool
	select PPC_CELL
	select PPC_DCR_MMIO
	select PPC_INDIRECT_IO
	select PPC_NATIVE
	select PPC_RTAS

config PPC_CELL_NATIVE
	bool
	select PPC_CELL_COMMON
	select MPIC
	select IBM_NEW_EMAC_EMAC4
	select IBM_NEW_EMAC_RGMII
	select IBM_NEW_EMAC_ZMII #test only
	select IBM_NEW_EMAC_TAH  #test only
	default n

config PPC_IBM_CELL_BLADE
	bool "IBM Cell Blade"
	depends on PPC64 && PPC_BOOK3S
	select PPC_CELL_NATIVE
	select PPC_OF_PLATFORM_PCI
	select PCI
	select MMIO_NVRAM
	select PPC_UDBG_16550
	select UDBG_RTAS_CONSOLE

config PPC_CELLEB
	bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
	depends on PPC64 && PPC_BOOK3S
	select PPC_CELL_NATIVE
	select PPC_OF_PLATFORM_PCI
	select PCI
	select HAS_TXX9_SERIAL
	select PPC_UDBG_BEAT
	select USB_OHCI_BIG_ENDIAN_MMIO
	select USB_EHCI_BIG_ENDIAN_MMIO

config PPC_CELL_QPACE
	bool "IBM Cell - QPACE"
	depends on PPC64 && PPC_BOOK3S
	select PPC_CELL_COMMON

config AXON_MSI
	bool
	depends on PPC_IBM_CELL_BLADE && PCI_MSI
	default y

menu "Cell Broadband Engine options"
	depends on PPC_CELL

config SPU_FS
	tristate "SPU file system"
	default m
	depends on PPC_CELL
	select SPU_BASE
	select MEMORY_HOTPLUG
	help
	  The SPU file system is used to access Synergistic Processing
	  Units on machines implementing the Broadband Processor
	  Architecture.

config SPU_FS_64K_LS
	bool "Use 64K pages to map SPE local  store"
	# we depend on PPC_MM_SLICES for now rather than selecting
	# it because we depend on hugetlbfs hooks being present. We
	# will fix that when the generic code has been improved to
	# not require hijacking hugetlbfs hooks.
	depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
	default y
	select PPC_HAS_HASH_64K
	help
	  This option causes SPE local stores to be mapped in process
	  address spaces using 64K pages while the rest of the kernel
	  uses 4K pages. This can improve performances of applications
	  using multiple SPEs by lowering the TLB pressure on them.

config SPU_BASE
	bool
	default n

config CBE_RAS
	bool "RAS features for bare metal Cell BE"
	depends on PPC_CELL_NATIVE
	default y

config PPC_IBM_CELL_RESETBUTTON
	bool "IBM Cell Blade Pinhole reset button"
	depends on CBE_RAS && PPC_IBM_CELL_BLADE
	default y
	help
	  Support Pinhole Resetbutton on IBM Cell blades.
	  This adds a method to trigger system reset via front panel pinhole button.

config PPC_IBM_CELL_POWERBUTTON
	tristate "IBM Cell Blade power button"
	depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV
	default y
	help
	  Support Powerbutton on IBM Cell blades.
	  This will enable the powerbutton as an input device.

config CBE_THERM
	tristate "CBE thermal support"
	default m
	depends on CBE_RAS && SPU_BASE

config CBE_CPUFREQ
	tristate "CBE frequency scaling"
	depends on CBE_RAS && CPU_FREQ
	default m
	help
	  This adds the cpufreq driver for Cell BE processors.
	  For details, take a look at <file:Documentation/cpu-freq/>.
	  If you don't have such processor, say N

config CBE_CPUFREQ_PMI_ENABLE
	bool "CBE frequency scaling using PMI interface"
	depends on CBE_CPUFREQ && EXPERIMENTAL
	default n
	help
	  Select this, if you want to use the PMI interface
	  to switch frequencies. Using PMI, the
	  processor will not only be able to run at lower speed,
	  but also at lower core voltage.

config CBE_CPUFREQ_PMI
	tristate
	depends on CBE_CPUFREQ_PMI_ENABLE
	default CBE_CPUFREQ

config PPC_PMI
	tristate
	default y
	depends on CBE_CPUFREQ_PMI || PPC_IBM_CELL_POWERBUTTON
	help
	  PMI (Platform Management Interrupt) is a way to
	  communicate with the BMC (Baseboard Management Controller).
	  It is used in some IBM Cell blades.

config CBE_CPUFREQ_SPU_GOVERNOR
	tristate "CBE frequency scaling based on SPU usage"
	depends on SPU_FS && CPU_FREQ
	default m
	help
	  This governor checks for spu usage to adjust the cpu frequency.
	  If no spu is running on a given cpu, that cpu will be throttled to
	  the minimal possible frequency.

endmenu

config OPROFILE_CELL
	def_bool y
	depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE
Commit	Line	Data
72e77a1b KG	1	config PPC_CELL
	2	bool
	3	default n
	4
def434c2	5	config PPC_CELL_COMMON
72e77a1b KG	6	bool
	7	select PPC_CELL
	8	select PPC_DCR_MMIO
72e77a1b KG	9	select PPC_INDIRECT_IO
72e77a1b KG	10	select PPC_NATIVE
def434c2 BK	11	select PPC_RTAS
	12
	13	config PPC_CELL_NATIVE
	14	bool
	15	select PPC_CELL_COMMON
72e77a1b	16	select MPIC
1d3bb996 DG	17	select IBM_NEW_EMAC_EMAC4
	18	select IBM_NEW_EMAC_RGMII
	19	select IBM_NEW_EMAC_ZMII #test only
	20	select IBM_NEW_EMAC_TAH #test only
72e77a1b KG	21	default n
	22
	23	config PPC_IBM_CELL_BLADE
	24	bool "IBM Cell Blade"
28794d34	25	depends on PPC64 && PPC_BOOK3S
72e77a1b	26	select PPC_CELL_NATIVE
ff61e5cc ME	27	select PPC_OF_PLATFORM_PCI
ff61e5cc ME	28	select PCI
72e77a1b KG	29	select MMIO_NVRAM
	30	select PPC_UDBG_16550
	31	select UDBG_RTAS_CONSOLE
	32
116bdc42 IK	33	config PPC_CELLEB
116bdc42 IK	34	bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
28794d34	35	depends on PPC64 && PPC_BOOK3S
116bdc42	36	select PPC_CELL_NATIVE
ff61e5cc ME	37	select PPC_OF_PLATFORM_PCI
ff61e5cc ME	38	select PCI
116bdc42 IK	39	select HAS_TXX9_SERIAL
	40	select PPC_UDBG_BEAT
	41	select USB_OHCI_BIG_ENDIAN_MMIO
	42	select USB_EHCI_BIG_ENDIAN_MMIO
	43
def434c2 BK	44	config PPC_CELL_QPACE
def434c2 BK	45	bool "IBM Cell - QPACE"
28794d34	46	depends on PPC64 && PPC_BOOK3S
def434c2 BK	47	select PPC_CELL_COMMON
def434c2 BK	48
47c3c6ef ME	49	config AXON_MSI
	50	bool
	51	depends on PPC_IBM_CELL_BLADE && PCI_MSI
	52	default y
	53
67207b96 AB	54	menu "Cell Broadband Engine options"
	55	depends on PPC_CELL
	56
	57	config SPU_FS
	58	tristate "SPU file system"
	59	default m
	60	depends on PPC_CELL
c01ea72a	61	select SPU_BASE
4da30d15	62	select MEMORY_HOTPLUG
67207b96 AB	63	help
	64	The SPU file system is used to access Synergistic Processing
	65	Units on machines implementing the Broadband Processor
	66	Architecture.
	67
f1fa74f4 BH	68	config SPU_FS_64K_LS
	69	bool "Use 64K pages to map SPE local store"
	70	# we depend on PPC_MM_SLICES for now rather than selecting
	71	# it because we depend on hugetlbfs hooks being present. We
	72	# will fix that when the generic code has been improved to
	73	# not require hijacking hugetlbfs hooks.
	74	depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
	75	default y
	76	select PPC_HAS_HASH_64K
	77	help
	78	This option causes SPE local stores to be mapped in process
	79	address spaces using 64K pages while the rest of the kernel
	80	uses 4K pages. This can improve performances of applications
	81	using multiple SPEs by lowering the TLB pressure on them.
	82
c01ea72a GL	83	config SPU_BASE
	84	bool
	85	default n
	86
acf7d768 BH	87	config CBE_RAS
acf7d768 BH	88	bool "RAS features for bare metal Cell BE"
28066ae9	89	depends on PPC_CELL_NATIVE
acf7d768 BH	90	default y
acf7d768 BH	91
70694a8b CK	92	config PPC_IBM_CELL_RESETBUTTON
	93	bool "IBM Cell Blade Pinhole reset button"
	94	depends on CBE_RAS && PPC_IBM_CELL_BLADE
	95	default y
	96	help
	97	Support Pinhole Resetbutton on IBM Cell blades.
	98	This adds a method to trigger system reset via front panel pinhole button.
	99
4795b780 CK	100	config PPC_IBM_CELL_POWERBUTTON
4795b780 CK	101	tristate "IBM Cell Blade power button"
6ed8d128	102	depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV
4795b780 CK	103	default y
	104	help
	105	Support Powerbutton on IBM Cell blades.
	106	This will enable the powerbutton as an input device.
	107
b3d7dc19 CK	108	config CBE_THERM
	109	tristate "CBE thermal support"
	110	default m
e68558dd	111	depends on CBE_RAS && SPU_BASE
b3d7dc19	112
36ca4ba4 CK	113	config CBE_CPUFREQ
	114	tristate "CBE frequency scaling"
	115	depends on CBE_RAS && CPU_FREQ
	116	default m
	117	help
	118	This adds the cpufreq driver for Cell BE processors.
	119	For details, take a look at <file:Documentation/cpu-freq/>.
	120	If you don't have such processor, say N
	121
6ed8d128 AB	122	config CBE_CPUFREQ_PMI_ENABLE
	123	bool "CBE frequency scaling using PMI interface"
	124	depends on CBE_CPUFREQ && EXPERIMENTAL
74889e41 CK	125	default n
	126	help
	127	Select this, if you want to use the PMI interface
	128	to switch frequencies. Using PMI, the
	129	processor will not only be able to run at lower speed,
	130	but also at lower core voltage.
	131
6ed8d128 AB	132	config CBE_CPUFREQ_PMI
	133	tristate
	134	depends on CBE_CPUFREQ_PMI_ENABLE
	135	default CBE_CPUFREQ
	136
	137	config PPC_PMI
	138	tristate
	139	default y
	140	depends on CBE_CPUFREQ_PMI \|\| PPC_IBM_CELL_POWERBUTTON
	141	help
	142	PMI (Platform Management Interrupt) is a way to
	143	communicate with the BMC (Baseboard Management Controller).
	144	It is used in some IBM Cell blades.
	145
880e7105 CK	146	config CBE_CPUFREQ_SPU_GOVERNOR
	147	tristate "CBE frequency scaling based on SPU usage"
	148	depends on SPU_FS && CPU_FREQ
	149	default m
	150	help
	151	This governor checks for spu usage to adjust the cpu frequency.
	152	If no spu is running on a given cpu, that cpu will be throttled to
	153	the minimal possible frequency.
	154
67207b96	155	endmenu
aed3a8c9 BN	156
	157	config OPROFILE_CELL
	158	def_bool y
e68558dd	159	depends on PPC_CELL_NATIVE && (OPROFILE = m \|\| OPROFILE = y) && SPU_BASE
aed3a8c9	160