[deliverable/linux.git] / arch / powerpc / platforms / cell / Kconfig

config PPC_CELL
	bool
	default n

config PPC_CELL_COMMON
	bool
	select PPC_CELL
	select PPC_DCR_MMIO
	select PPC_INDIRECT_IO
	select PPC_NATIVE
	select PPC_RTAS

config PPC_CELL_NATIVE
	bool
	select PPC_CELL_COMMON
	select PPC_OF_PLATFORM_PCI
	select MPIC
	select IBM_NEW_EMAC_EMAC4
	select IBM_NEW_EMAC_RGMII
	select IBM_NEW_EMAC_ZMII #test only
	select IBM_NEW_EMAC_TAH  #test only
	default n

config PPC_IBM_CELL_BLADE
	bool "IBM Cell Blade"
	depends on PPC64 && PPC_BOOK3S
	select PPC_CELL_NATIVE
	select MMIO_NVRAM
	select PPC_UDBG_16550
	select UDBG_RTAS_CONSOLE

config PPC_CELLEB
	bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
	depends on PPC64 && PPC_BOOK3S
	select PPC_CELL_NATIVE
	select HAS_TXX9_SERIAL
	select PPC_UDBG_BEAT
	select USB_OHCI_BIG_ENDIAN_MMIO
	select USB_EHCI_BIG_ENDIAN_MMIO

config PPC_CELL_QPACE
	bool "IBM Cell - QPACE"
	depends on PPC64 && PPC_BOOK3S
	select PPC_CELL_COMMON

config AXON_MSI
	bool
	depends on PPC_IBM_CELL_BLADE && PCI_MSI
	default y

menu "Cell Broadband Engine options"
	depends on PPC_CELL

config SPU_FS
	tristate "SPU file system"
	default m
	depends on PPC_CELL
	select SPU_BASE
	select MEMORY_HOTPLUG
	help
	  The SPU file system is used to access Synergistic Processing
	  Units on machines implementing the Broadband Processor
	  Architecture.

config SPU_FS_64K_LS
	bool "Use 64K pages to map SPE local  store"
	# we depend on PPC_MM_SLICES for now rather than selecting
	# it because we depend on hugetlbfs hooks being present. We
	# will fix that when the generic code has been improved to
	# not require hijacking hugetlbfs hooks.
	depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
	default y
	select PPC_HAS_HASH_64K
	help
	  This option causes SPE local stores to be mapped in process
	  address spaces using 64K pages while the rest of the kernel
	  uses 4K pages. This can improve performances of applications
	  using multiple SPEs by lowering the TLB pressure on them.

config SPU_TRACE
	tristate "SPU event tracing support"
	depends on SPU_FS && MARKERS
	help
	  This option allows reading a trace of spu-related events through
	  the sputrace file in procfs.

config SPU_BASE
	bool
	default n

config CBE_RAS
	bool "RAS features for bare metal Cell BE"
	depends on PPC_CELL_NATIVE
	default y

config PPC_IBM_CELL_RESETBUTTON
	bool "IBM Cell Blade Pinhole reset button"
	depends on CBE_RAS && PPC_IBM_CELL_BLADE
	default y
	help
	  Support Pinhole Resetbutton on IBM Cell blades.
	  This adds a method to trigger system reset via front panel pinhole button.

config PPC_IBM_CELL_POWERBUTTON
	tristate "IBM Cell Blade power button"
	depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV
	default y
	help
	  Support Powerbutton on IBM Cell blades.
	  This will enable the powerbutton as an input device.

config CBE_THERM
	tristate "CBE thermal support"
	default m
	depends on CBE_RAS && SPU_BASE

config CBE_CPUFREQ
	tristate "CBE frequency scaling"
	depends on CBE_RAS && CPU_FREQ
	default m
	help
	  This adds the cpufreq driver for Cell BE processors.
	  For details, take a look at <file:Documentation/cpu-freq/>.
	  If you don't have such processor, say N

config CBE_CPUFREQ_PMI_ENABLE
	bool "CBE frequency scaling using PMI interface"
	depends on CBE_CPUFREQ && EXPERIMENTAL
	default n
	help
	  Select this, if you want to use the PMI interface
	  to switch frequencies. Using PMI, the
	  processor will not only be able to run at lower speed,
	  but also at lower core voltage.

config CBE_CPUFREQ_PMI
	tristate
	depends on CBE_CPUFREQ_PMI_ENABLE
	default CBE_CPUFREQ

config PPC_PMI
	tristate
	default y
	depends on CBE_CPUFREQ_PMI || PPC_IBM_CELL_POWERBUTTON
	help
	  PMI (Platform Management Interrupt) is a way to
	  communicate with the BMC (Baseboard Management Controller).
	  It is used in some IBM Cell blades.

config CBE_CPUFREQ_SPU_GOVERNOR
	tristate "CBE frequency scaling based on SPU usage"
	depends on SPU_FS && CPU_FREQ
	default m
	help
	  This governor checks for spu usage to adjust the cpu frequency.
	  If no spu is running on a given cpu, that cpu will be throttled to
	  the minimal possible frequency.

endmenu

config OPROFILE_CELL
	def_bool y
	depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE
Commit	Line	Data
72e77a1b KG	1	config PPC_CELL
	2	bool
	3	default n
	4
def434c2	5	config PPC_CELL_COMMON
72e77a1b KG	6	bool
	7	select PPC_CELL
	8	select PPC_DCR_MMIO
72e77a1b KG	9	select PPC_INDIRECT_IO
72e77a1b KG	10	select PPC_NATIVE
def434c2 BK	11	select PPC_RTAS
	12
	13	config PPC_CELL_NATIVE
	14	bool
	15	select PPC_CELL_COMMON
	16	select PPC_OF_PLATFORM_PCI
72e77a1b	17	select MPIC
1d3bb996 DG	18	select IBM_NEW_EMAC_EMAC4
	19	select IBM_NEW_EMAC_RGMII
	20	select IBM_NEW_EMAC_ZMII #test only
	21	select IBM_NEW_EMAC_TAH #test only
72e77a1b KG	22	default n
	23
	24	config PPC_IBM_CELL_BLADE
	25	bool "IBM Cell Blade"
28794d34	26	depends on PPC64 && PPC_BOOK3S
72e77a1b	27	select PPC_CELL_NATIVE
72e77a1b KG	28	select MMIO_NVRAM
	29	select PPC_UDBG_16550
	30	select UDBG_RTAS_CONSOLE
	31
116bdc42 IK	32	config PPC_CELLEB
116bdc42 IK	33	bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
28794d34	34	depends on PPC64 && PPC_BOOK3S
116bdc42	35	select PPC_CELL_NATIVE
116bdc42 IK	36	select HAS_TXX9_SERIAL
	37	select PPC_UDBG_BEAT
	38	select USB_OHCI_BIG_ENDIAN_MMIO
	39	select USB_EHCI_BIG_ENDIAN_MMIO
	40
def434c2 BK	41	config PPC_CELL_QPACE
def434c2 BK	42	bool "IBM Cell - QPACE"
28794d34	43	depends on PPC64 && PPC_BOOK3S
def434c2 BK	44	select PPC_CELL_COMMON
def434c2 BK	45
47c3c6ef ME	46	config AXON_MSI
	47	bool
	48	depends on PPC_IBM_CELL_BLADE && PCI_MSI
	49	default y
	50
67207b96 AB	51	menu "Cell Broadband Engine options"
	52	depends on PPC_CELL
	53
	54	config SPU_FS
	55	tristate "SPU file system"
	56	default m
	57	depends on PPC_CELL
c01ea72a	58	select SPU_BASE
4da30d15	59	select MEMORY_HOTPLUG
67207b96 AB	60	help
	61	The SPU file system is used to access Synergistic Processing
	62	Units on machines implementing the Broadband Processor
	63	Architecture.
	64
f1fa74f4 BH	65	config SPU_FS_64K_LS
	66	bool "Use 64K pages to map SPE local store"
	67	# we depend on PPC_MM_SLICES for now rather than selecting
	68	# it because we depend on hugetlbfs hooks being present. We
	69	# will fix that when the generic code has been improved to
	70	# not require hijacking hugetlbfs hooks.
	71	depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
	72	default y
	73	select PPC_HAS_HASH_64K
	74	help
	75	This option causes SPE local stores to be mapped in process
	76	address spaces using 64K pages while the rest of the kernel
	77	uses 4K pages. This can improve performances of applications
	78	using multiple SPEs by lowering the TLB pressure on them.
	79
038200cf CH	80	config SPU_TRACE
	81	tristate "SPU event tracing support"
	82	depends on SPU_FS && MARKERS
	83	help
	84	This option allows reading a trace of spu-related events through
	85	the sputrace file in procfs.
	86
c01ea72a GL	87	config SPU_BASE
	88	bool
	89	default n
	90
acf7d768 BH	91	config CBE_RAS
acf7d768 BH	92	bool "RAS features for bare metal Cell BE"
28066ae9	93	depends on PPC_CELL_NATIVE
acf7d768 BH	94	default y
acf7d768 BH	95
70694a8b CK	96	config PPC_IBM_CELL_RESETBUTTON
	97	bool "IBM Cell Blade Pinhole reset button"
	98	depends on CBE_RAS && PPC_IBM_CELL_BLADE
	99	default y
	100	help
	101	Support Pinhole Resetbutton on IBM Cell blades.
	102	This adds a method to trigger system reset via front panel pinhole button.
	103
4795b780 CK	104	config PPC_IBM_CELL_POWERBUTTON
4795b780 CK	105	tristate "IBM Cell Blade power button"
6ed8d128	106	depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV
4795b780 CK	107	default y
	108	help
	109	Support Powerbutton on IBM Cell blades.
	110	This will enable the powerbutton as an input device.
	111
b3d7dc19 CK	112	config CBE_THERM
	113	tristate "CBE thermal support"
	114	default m
e68558dd	115	depends on CBE_RAS && SPU_BASE
b3d7dc19	116
36ca4ba4 CK	117	config CBE_CPUFREQ
	118	tristate "CBE frequency scaling"
	119	depends on CBE_RAS && CPU_FREQ
	120	default m
	121	help
	122	This adds the cpufreq driver for Cell BE processors.
	123	For details, take a look at <file:Documentation/cpu-freq/>.
	124	If you don't have such processor, say N
	125
6ed8d128 AB	126	config CBE_CPUFREQ_PMI_ENABLE
	127	bool "CBE frequency scaling using PMI interface"
	128	depends on CBE_CPUFREQ && EXPERIMENTAL
74889e41 CK	129	default n
	130	help
	131	Select this, if you want to use the PMI interface
	132	to switch frequencies. Using PMI, the
	133	processor will not only be able to run at lower speed,
	134	but also at lower core voltage.
	135
6ed8d128 AB	136	config CBE_CPUFREQ_PMI
	137	tristate
	138	depends on CBE_CPUFREQ_PMI_ENABLE
	139	default CBE_CPUFREQ
	140
	141	config PPC_PMI
	142	tristate
	143	default y
	144	depends on CBE_CPUFREQ_PMI \|\| PPC_IBM_CELL_POWERBUTTON
	145	help
	146	PMI (Platform Management Interrupt) is a way to
	147	communicate with the BMC (Baseboard Management Controller).
	148	It is used in some IBM Cell blades.
	149
880e7105 CK	150	config CBE_CPUFREQ_SPU_GOVERNOR
	151	tristate "CBE frequency scaling based on SPU usage"
	152	depends on SPU_FS && CPU_FREQ
	153	default m
	154	help
	155	This governor checks for spu usage to adjust the cpu frequency.
	156	If no spu is running on a given cpu, that cpu will be throttled to
	157	the minimal possible frequency.
	158
67207b96	159	endmenu
aed3a8c9 BN	160
	161	config OPROFILE_CELL
	162	def_bool y
e68558dd	163	depends on PPC_CELL_NATIVE && (OPROFILE = m \|\| OPROFILE = y) && SPU_BASE
aed3a8c9	164