projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 72e77a1b KG |
1 | config PPC_CELL |
| 2 | bool | |
| 3 | default n | |
| 4 | ||
| def434c2 | 5 | config PPC_CELL_COMMON |
| 72e77a1b KG |
6 | bool |
| 7 | select PPC_CELL | |
| 8 | select PPC_DCR_MMIO | |
| 72e77a1b KG |
9 | select PPC_INDIRECT_IO |
| 10 | select PPC_NATIVE | |
| def434c2 BK |
11 | select PPC_RTAS |
| 12 | ||
| 13 | config PPC_CELL_NATIVE | |
| 14 | bool | |
| 15 | select PPC_CELL_COMMON | |
| 16 | select PPC_OF_PLATFORM_PCI | |
| 72e77a1b | 17 | select MPIC |
| 1d3bb996 DG |
18 | select IBM_NEW_EMAC_EMAC4 |
| 19 | select IBM_NEW_EMAC_RGMII | |
| 20 | select IBM_NEW_EMAC_ZMII #test only | |
| 21 | select IBM_NEW_EMAC_TAH #test only | |
| 72e77a1b KG |
22 | default n |
| 23 | ||
| 24 | config PPC_IBM_CELL_BLADE | |
| 25 | bool "IBM Cell Blade" | |
| 26 | depends on PPC_MULTIPLATFORM && PPC64 | |
| 27 | select PPC_CELL_NATIVE | |
| 72e77a1b KG |
28 | select MMIO_NVRAM |
| 29 | select PPC_UDBG_16550 | |
| 30 | select UDBG_RTAS_CONSOLE | |
| 31 | ||
| 116bdc42 IK |
32 | config PPC_CELLEB |
| 33 | bool "Toshiba's Cell Reference Set 'Celleb' Architecture" | |
| 34 | depends on PPC_MULTIPLATFORM && PPC64 | |
| 116bdc42 | 35 | select PPC_CELL_NATIVE |
| 116bdc42 IK |
36 | select HAS_TXX9_SERIAL |
| 37 | select PPC_UDBG_BEAT | |
| 38 | select USB_OHCI_BIG_ENDIAN_MMIO | |
| 39 | select USB_EHCI_BIG_ENDIAN_MMIO | |
| 40 | ||
| def434c2 BK |
41 | config PPC_CELL_QPACE |
| 42 | bool "IBM Cell - QPACE" | |
| 43 | depends on PPC_MULTIPLATFORM && PPC64 | |
| 44 | select PPC_CELL_COMMON | |
| 45 | ||
| 67207b96 AB |
46 | menu "Cell Broadband Engine options" |
| 47 | depends on PPC_CELL | |
| 48 | ||
| 49 | config SPU_FS | |
| 50 | tristate "SPU file system" | |
| 51 | default m | |
| 52 | depends on PPC_CELL | |
| c01ea72a | 53 | select SPU_BASE |
| 4da30d15 | 54 | select MEMORY_HOTPLUG |
| 67207b96 AB |
55 | help |
| 56 | The SPU file system is used to access Synergistic Processing | |
| 57 | Units on machines implementing the Broadband Processor | |
| 58 | Architecture. | |
| 59 | ||
| f1fa74f4 BH |
60 | config SPU_FS_64K_LS |
| 61 | bool "Use 64K pages to map SPE local store" | |
| 62 | # we depend on PPC_MM_SLICES for now rather than selecting | |
| 63 | # it because we depend on hugetlbfs hooks being present. We | |
| 64 | # will fix that when the generic code has been improved to | |
| 65 | # not require hijacking hugetlbfs hooks. | |
| 66 | depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES | |
| 67 | default y | |
| 68 | select PPC_HAS_HASH_64K | |
| 69 | help | |
| 70 | This option causes SPE local stores to be mapped in process | |
| 71 | address spaces using 64K pages while the rest of the kernel | |
| 72 | uses 4K pages. This can improve performances of applications | |
| 73 | using multiple SPEs by lowering the TLB pressure on them. | |
| 74 | ||
| 038200cf CH |
75 | config SPU_TRACE |
| 76 | tristate "SPU event tracing support" | |
| 77 | depends on SPU_FS && MARKERS | |
| 78 | help | |
| 79 | This option allows reading a trace of spu-related events through | |
| 80 | the sputrace file in procfs. | |
| 81 | ||
| c01ea72a GL |
82 | config SPU_BASE |
| 83 | bool | |
| 84 | default n | |
| 85 | ||
| acf7d768 BH |
86 | config CBE_RAS |
| 87 | bool "RAS features for bare metal Cell BE" | |
| 28066ae9 | 88 | depends on PPC_CELL_NATIVE |
| acf7d768 BH |
89 | default y |
| 90 | ||
| 70694a8b CK |
91 | config PPC_IBM_CELL_RESETBUTTON |
| 92 | bool "IBM Cell Blade Pinhole reset button" | |
| 93 | depends on CBE_RAS && PPC_IBM_CELL_BLADE | |
| 94 | default y | |
| 95 | help | |
| 96 | Support Pinhole Resetbutton on IBM Cell blades. | |
| 97 | This adds a method to trigger system reset via front panel pinhole button. | |
| 98 | ||
| 4795b780 CK |
99 | config PPC_IBM_CELL_POWERBUTTON |
| 100 | tristate "IBM Cell Blade power button" | |
| 101 | depends on PPC_IBM_CELL_BLADE && PPC_PMI && INPUT_EVDEV | |
| 102 | default y | |
| 103 | help | |
| 104 | Support Powerbutton on IBM Cell blades. | |
| 105 | This will enable the powerbutton as an input device. | |
| 106 | ||
| b3d7dc19 CK |
107 | config CBE_THERM |
| 108 | tristate "CBE thermal support" | |
| 109 | default m | |
| e68558dd | 110 | depends on CBE_RAS && SPU_BASE |
| b3d7dc19 | 111 | |
| 36ca4ba4 CK |
112 | config CBE_CPUFREQ |
| 113 | tristate "CBE frequency scaling" | |
| 114 | depends on CBE_RAS && CPU_FREQ | |
| 115 | default m | |
| 116 | help | |
| 117 | This adds the cpufreq driver for Cell BE processors. | |
| 118 | For details, take a look at <file:Documentation/cpu-freq/>. | |
| 119 | If you don't have such processor, say N | |
| 120 | ||
| 74889e41 CK |
121 | config CBE_CPUFREQ_PMI |
| 122 | tristate "CBE frequency scaling using PMI interface" | |
| 123 | depends on CBE_CPUFREQ && PPC_PMI && EXPERIMENTAL | |
| 124 | default n | |
| 125 | help | |
| 126 | Select this, if you want to use the PMI interface | |
| 127 | to switch frequencies. Using PMI, the | |
| 128 | processor will not only be able to run at lower speed, | |
| 129 | but also at lower core voltage. | |
| 130 | ||
| 880e7105 CK |
131 | config CBE_CPUFREQ_SPU_GOVERNOR |
| 132 | tristate "CBE frequency scaling based on SPU usage" | |
| 133 | depends on SPU_FS && CPU_FREQ | |
| 134 | default m | |
| 135 | help | |
| 136 | This governor checks for spu usage to adjust the cpu frequency. | |
| 137 | If no spu is running on a given cpu, that cpu will be throttled to | |
| 138 | the minimal possible frequency. | |
| 139 | ||
| 67207b96 | 140 | endmenu |
| aed3a8c9 BN |
141 | |
| 142 | config OPROFILE_CELL | |
| 143 | def_bool y | |
| e68558dd | 144 | depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE |
| aed3a8c9 | 145 |