Commit | Line | Data |
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ce21b3c9 ME |
1 | /* |
2 | * Copyright 2007, Michael Ellerman, IBM Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | ||
11 | #include <linux/interrupt.h> | |
12 | #include <linux/irq.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/msi.h> | |
e4347dfb | 16 | #include <linux/of_platform.h> |
72cac213 | 17 | #include <linux/debugfs.h> |
ce21b3c9 ME |
18 | |
19 | #include <asm/dcr.h> | |
20 | #include <asm/machdep.h> | |
21 | #include <asm/prom.h> | |
22 | ||
23 | ||
24 | /* | |
25 | * MSIC registers, specified as offsets from dcr_base | |
26 | */ | |
27 | #define MSIC_CTRL_REG 0x0 | |
28 | ||
29 | /* Base Address registers specify FIFO location in BE memory */ | |
30 | #define MSIC_BASE_ADDR_HI_REG 0x3 | |
31 | #define MSIC_BASE_ADDR_LO_REG 0x4 | |
32 | ||
33 | /* Hold the read/write offsets into the FIFO */ | |
34 | #define MSIC_READ_OFFSET_REG 0x5 | |
35 | #define MSIC_WRITE_OFFSET_REG 0x6 | |
36 | ||
37 | ||
38 | /* MSIC control register flags */ | |
39 | #define MSIC_CTRL_ENABLE 0x0001 | |
40 | #define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002 | |
41 | #define MSIC_CTRL_IRQ_ENABLE 0x0008 | |
42 | #define MSIC_CTRL_FULL_STOP_ENABLE 0x0010 | |
43 | ||
44 | /* | |
45 | * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB. | |
46 | * Currently we're using a 64KB FIFO size. | |
47 | */ | |
48 | #define MSIC_FIFO_SIZE_SHIFT 16 | |
49 | #define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT) | |
50 | ||
51 | /* | |
52 | * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits | |
53 | * 8-9 of the MSIC control reg. | |
54 | */ | |
55 | #define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300) | |
56 | ||
57 | /* | |
58 | * We need to mask the read/write offsets to make sure they stay within | |
59 | * the bounds of the FIFO. Also they should always be 16-byte aligned. | |
60 | */ | |
61 | #define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu) | |
62 | ||
63 | /* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */ | |
64 | #define MSIC_FIFO_ENTRY_SIZE 0x10 | |
65 | ||
66 | ||
67 | struct axon_msic { | |
ce21b3c9 | 68 | struct irq_host *irq_host; |
de4c928b ME |
69 | __le32 *fifo_virt; |
70 | dma_addr_t fifo_phys; | |
ce21b3c9 | 71 | dcr_host_t dcr_host; |
ce21b3c9 | 72 | u32 read_offset; |
72cac213 ME |
73 | #ifdef DEBUG |
74 | u32 __iomem *trigger; | |
75 | #endif | |
ce21b3c9 ME |
76 | }; |
77 | ||
72cac213 ME |
78 | #ifdef DEBUG |
79 | void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic); | |
80 | #else | |
81 | static inline void axon_msi_debug_setup(struct device_node *dn, | |
82 | struct axon_msic *msic) { } | |
83 | #endif | |
84 | ||
85 | ||
ce21b3c9 ME |
86 | static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) |
87 | { | |
88 | pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); | |
89 | ||
83f34df4 | 90 | dcr_write(msic->dcr_host, dcr_n, val); |
ce21b3c9 ME |
91 | } |
92 | ||
ce21b3c9 ME |
93 | static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) |
94 | { | |
95 | struct axon_msic *msic = get_irq_data(irq); | |
96 | u32 write_offset, msi; | |
97 | int idx; | |
d015fe99 | 98 | int retry = 0; |
ce21b3c9 | 99 | |
2843e7f7 | 100 | write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); |
ce21b3c9 ME |
101 | pr_debug("axon_msi: original write_offset 0x%x\n", write_offset); |
102 | ||
103 | /* write_offset doesn't wrap properly, so we have to mask it */ | |
104 | write_offset &= MSIC_FIFO_SIZE_MASK; | |
105 | ||
d015fe99 | 106 | while (msic->read_offset != write_offset && retry < 100) { |
ce21b3c9 | 107 | idx = msic->read_offset / sizeof(__le32); |
de4c928b | 108 | msi = le32_to_cpu(msic->fifo_virt[idx]); |
ce21b3c9 ME |
109 | msi &= 0xFFFF; |
110 | ||
111 | pr_debug("axon_msi: woff %x roff %x msi %x\n", | |
112 | write_offset, msic->read_offset, msi); | |
113 | ||
d015fe99 AB |
114 | if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) { |
115 | generic_handle_irq(msi); | |
116 | msic->fifo_virt[idx] = cpu_to_le32(0xffffffff); | |
117 | } else { | |
118 | /* | |
119 | * Reading the MSIC_WRITE_OFFSET_REG does not | |
120 | * reliably flush the outstanding DMA to the | |
121 | * FIFO buffer. Here we were reading stale | |
122 | * data, so we need to retry. | |
123 | */ | |
124 | udelay(1); | |
125 | retry++; | |
126 | pr_debug("axon_msi: invalid irq 0x%x!\n", msi); | |
127 | continue; | |
128 | } | |
129 | ||
130 | if (retry) { | |
131 | pr_debug("axon_msi: late irq 0x%x, retry %d\n", | |
132 | msi, retry); | |
133 | retry = 0; | |
134 | } | |
135 | ||
ce21b3c9 ME |
136 | msic->read_offset += MSIC_FIFO_ENTRY_SIZE; |
137 | msic->read_offset &= MSIC_FIFO_SIZE_MASK; | |
d015fe99 | 138 | } |
ce21b3c9 | 139 | |
d015fe99 AB |
140 | if (retry) { |
141 | printk(KERN_WARNING "axon_msi: irq timed out\n"); | |
142 | ||
143 | msic->read_offset += MSIC_FIFO_ENTRY_SIZE; | |
144 | msic->read_offset &= MSIC_FIFO_SIZE_MASK; | |
ce21b3c9 ME |
145 | } |
146 | ||
147 | desc->chip->eoi(irq); | |
148 | } | |
149 | ||
150 | static struct axon_msic *find_msi_translator(struct pci_dev *dev) | |
151 | { | |
152 | struct irq_host *irq_host; | |
153 | struct device_node *dn, *tmp; | |
154 | const phandle *ph; | |
155 | struct axon_msic *msic = NULL; | |
156 | ||
db220b23 | 157 | dn = of_node_get(pci_device_to_OF_node(dev)); |
ce21b3c9 ME |
158 | if (!dn) { |
159 | dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n"); | |
160 | return NULL; | |
161 | } | |
162 | ||
988479eb | 163 | for (; dn; dn = of_get_next_parent(dn)) { |
ce21b3c9 ME |
164 | ph = of_get_property(dn, "msi-translator", NULL); |
165 | if (ph) | |
166 | break; | |
167 | } | |
168 | ||
169 | if (!ph) { | |
170 | dev_dbg(&dev->dev, | |
171 | "axon_msi: no msi-translator property found\n"); | |
172 | goto out_error; | |
173 | } | |
174 | ||
175 | tmp = dn; | |
176 | dn = of_find_node_by_phandle(*ph); | |
c6d01179 | 177 | of_node_put(tmp); |
ce21b3c9 ME |
178 | if (!dn) { |
179 | dev_dbg(&dev->dev, | |
180 | "axon_msi: msi-translator doesn't point to a node\n"); | |
181 | goto out_error; | |
182 | } | |
183 | ||
184 | irq_host = irq_find_host(dn); | |
185 | if (!irq_host) { | |
186 | dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n", | |
187 | dn->full_name); | |
188 | goto out_error; | |
189 | } | |
190 | ||
191 | msic = irq_host->host_data; | |
192 | ||
193 | out_error: | |
194 | of_node_put(dn); | |
ce21b3c9 ME |
195 | |
196 | return msic; | |
197 | } | |
198 | ||
199 | static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
200 | { | |
201 | if (!find_msi_translator(dev)) | |
202 | return -ENODEV; | |
203 | ||
204 | return 0; | |
205 | } | |
206 | ||
207 | static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg) | |
208 | { | |
988479eb | 209 | struct device_node *dn; |
ce21b3c9 ME |
210 | struct msi_desc *entry; |
211 | int len; | |
212 | const u32 *prop; | |
213 | ||
db220b23 | 214 | dn = of_node_get(pci_device_to_OF_node(dev)); |
ce21b3c9 ME |
215 | if (!dn) { |
216 | dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n"); | |
217 | return -ENODEV; | |
218 | } | |
219 | ||
220 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
221 | ||
988479eb | 222 | for (; dn; dn = of_get_next_parent(dn)) { |
ce21b3c9 ME |
223 | if (entry->msi_attrib.is_64) { |
224 | prop = of_get_property(dn, "msi-address-64", &len); | |
225 | if (prop) | |
226 | break; | |
227 | } | |
228 | ||
229 | prop = of_get_property(dn, "msi-address-32", &len); | |
230 | if (prop) | |
231 | break; | |
232 | } | |
233 | ||
234 | if (!prop) { | |
235 | dev_dbg(&dev->dev, | |
236 | "axon_msi: no msi-address-(32|64) properties found\n"); | |
237 | return -ENOENT; | |
238 | } | |
239 | ||
240 | switch (len) { | |
241 | case 8: | |
242 | msg->address_hi = prop[0]; | |
243 | msg->address_lo = prop[1]; | |
244 | break; | |
245 | case 4: | |
246 | msg->address_hi = 0; | |
247 | msg->address_lo = prop[0]; | |
248 | break; | |
249 | default: | |
250 | dev_dbg(&dev->dev, | |
251 | "axon_msi: malformed msi-address-(32|64) property\n"); | |
252 | of_node_put(dn); | |
253 | return -EINVAL; | |
254 | } | |
255 | ||
256 | of_node_put(dn); | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
262 | { | |
263 | unsigned int virq, rc; | |
264 | struct msi_desc *entry; | |
265 | struct msi_msg msg; | |
266 | struct axon_msic *msic; | |
267 | ||
268 | msic = find_msi_translator(dev); | |
269 | if (!msic) | |
270 | return -ENODEV; | |
271 | ||
272 | rc = setup_msi_msg_address(dev, &msg); | |
273 | if (rc) | |
274 | return rc; | |
275 | ||
276 | /* We rely on being able to stash a virq in a u16 */ | |
277 | BUILD_BUG_ON(NR_IRQS > 65536); | |
278 | ||
279 | list_for_each_entry(entry, &dev->msi_list, list) { | |
280 | virq = irq_create_direct_mapping(msic->irq_host); | |
281 | if (virq == NO_IRQ) { | |
282 | dev_warn(&dev->dev, | |
283 | "axon_msi: virq allocation failed!\n"); | |
284 | return -1; | |
285 | } | |
286 | dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq); | |
287 | ||
288 | set_irq_msi(virq, entry); | |
289 | msg.data = virq; | |
290 | write_msi_msg(virq, &msg); | |
291 | } | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
296 | static void axon_msi_teardown_msi_irqs(struct pci_dev *dev) | |
297 | { | |
298 | struct msi_desc *entry; | |
299 | ||
300 | dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n"); | |
301 | ||
302 | list_for_each_entry(entry, &dev->msi_list, list) { | |
303 | if (entry->irq == NO_IRQ) | |
304 | continue; | |
305 | ||
306 | set_irq_msi(entry->irq, NULL); | |
307 | irq_dispose_mapping(entry->irq); | |
308 | } | |
309 | } | |
310 | ||
311 | static struct irq_chip msic_irq_chip = { | |
312 | .mask = mask_msi_irq, | |
313 | .unmask = unmask_msi_irq, | |
314 | .shutdown = unmask_msi_irq, | |
315 | .typename = "AXON-MSI", | |
316 | }; | |
317 | ||
318 | static int msic_host_map(struct irq_host *h, unsigned int virq, | |
319 | irq_hw_number_t hw) | |
320 | { | |
321 | set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq); | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
ce21b3c9 | 326 | static struct irq_host_ops msic_host_ops = { |
ce21b3c9 ME |
327 | .map = msic_host_map, |
328 | }; | |
329 | ||
e4347dfb | 330 | static int axon_msi_shutdown(struct of_device *device) |
ce21b3c9 | 331 | { |
86c27656 | 332 | struct axon_msic *msic = dev_get_drvdata(&device->dev); |
ce21b3c9 ME |
333 | u32 tmp; |
334 | ||
e4347dfb ME |
335 | pr_debug("axon_msi: disabling %s\n", |
336 | msic->irq_host->of_node->full_name); | |
337 | tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG); | |
338 | tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE; | |
339 | msic_dcr_write(msic, MSIC_CTRL_REG, tmp); | |
ce21b3c9 ME |
340 | |
341 | return 0; | |
342 | } | |
343 | ||
e4347dfb ME |
344 | static int axon_msi_probe(struct of_device *device, |
345 | const struct of_device_id *device_id) | |
ce21b3c9 | 346 | { |
e4347dfb | 347 | struct device_node *dn = device->node; |
ce21b3c9 ME |
348 | struct axon_msic *msic; |
349 | unsigned int virq; | |
4acb8896 | 350 | int dcr_base, dcr_len; |
ce21b3c9 ME |
351 | |
352 | pr_debug("axon_msi: setting up dn %s\n", dn->full_name); | |
353 | ||
354 | msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL); | |
355 | if (!msic) { | |
356 | printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n", | |
357 | dn->full_name); | |
358 | goto out; | |
359 | } | |
360 | ||
4acb8896 | 361 | dcr_base = dcr_resource_start(dn, 0); |
ce21b3c9 ME |
362 | dcr_len = dcr_resource_len(dn, 0); |
363 | ||
4acb8896 | 364 | if (dcr_base == 0 || dcr_len == 0) { |
ce21b3c9 ME |
365 | printk(KERN_ERR |
366 | "axon_msi: couldn't parse dcr properties on %s\n", | |
367 | dn->full_name); | |
368 | goto out; | |
369 | } | |
370 | ||
4acb8896 | 371 | msic->dcr_host = dcr_map(dn, dcr_base, dcr_len); |
ce21b3c9 ME |
372 | if (!DCR_MAP_OK(msic->dcr_host)) { |
373 | printk(KERN_ERR "axon_msi: dcr_map failed for %s\n", | |
374 | dn->full_name); | |
375 | goto out_free_msic; | |
376 | } | |
377 | ||
de4c928b ME |
378 | msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, |
379 | &msic->fifo_phys, GFP_KERNEL); | |
380 | if (!msic->fifo_virt) { | |
ce21b3c9 ME |
381 | printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n", |
382 | dn->full_name); | |
383 | goto out_free_msic; | |
384 | } | |
385 | ||
997526db ME |
386 | virq = irq_of_parse_and_map(dn, 0); |
387 | if (virq == NO_IRQ) { | |
388 | printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n", | |
389 | dn->full_name); | |
390 | goto out_free_fifo; | |
391 | } | |
d015fe99 | 392 | memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES); |
997526db | 393 | |
19fc65b5 | 394 | msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP, |
52964f87 | 395 | NR_IRQS, &msic_host_ops, 0); |
ce21b3c9 ME |
396 | if (!msic->irq_host) { |
397 | printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n", | |
398 | dn->full_name); | |
399 | goto out_free_fifo; | |
400 | } | |
401 | ||
402 | msic->irq_host->host_data = msic; | |
403 | ||
ce21b3c9 ME |
404 | set_irq_data(virq, msic); |
405 | set_irq_chained_handler(virq, axon_msi_cascade); | |
406 | pr_debug("axon_msi: irq 0x%x setup for axon_msi\n", virq); | |
407 | ||
408 | /* Enable the MSIC hardware */ | |
de4c928b | 409 | msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32); |
ce21b3c9 | 410 | msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG, |
de4c928b | 411 | msic->fifo_phys & 0xFFFFFFFF); |
ce21b3c9 ME |
412 | msic_dcr_write(msic, MSIC_CTRL_REG, |
413 | MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE | | |
414 | MSIC_CTRL_FIFO_SIZE); | |
415 | ||
23e0e8af AB |
416 | msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG) |
417 | & MSIC_FIFO_SIZE_MASK; | |
418 | ||
86c27656 | 419 | dev_set_drvdata(&device->dev, msic); |
e4347dfb ME |
420 | |
421 | ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs; | |
422 | ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs; | |
423 | ppc_md.msi_check_device = axon_msi_check_device; | |
ce21b3c9 | 424 | |
72cac213 ME |
425 | axon_msi_debug_setup(dn, msic); |
426 | ||
ce21b3c9 ME |
427 | printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name); |
428 | ||
429 | return 0; | |
430 | ||
ce21b3c9 | 431 | out_free_fifo: |
de4c928b ME |
432 | dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt, |
433 | msic->fifo_phys); | |
ce21b3c9 ME |
434 | out_free_msic: |
435 | kfree(msic); | |
436 | out: | |
437 | ||
438 | return -1; | |
439 | } | |
440 | ||
e4347dfb ME |
441 | static const struct of_device_id axon_msi_device_id[] = { |
442 | { | |
443 | .compatible = "ibm,axon-msic" | |
444 | }, | |
445 | {} | |
446 | }; | |
ce21b3c9 | 447 | |
e4347dfb ME |
448 | static struct of_platform_driver axon_msi_driver = { |
449 | .match_table = axon_msi_device_id, | |
450 | .probe = axon_msi_probe, | |
451 | .shutdown = axon_msi_shutdown, | |
452 | .driver = { | |
453 | .name = "axon-msi" | |
454 | }, | |
455 | }; | |
ce21b3c9 | 456 | |
e4347dfb ME |
457 | static int __init axon_msi_init(void) |
458 | { | |
459 | return of_register_platform_driver(&axon_msi_driver); | |
ce21b3c9 | 460 | } |
e4347dfb | 461 | subsys_initcall(axon_msi_init); |
72cac213 ME |
462 | |
463 | ||
464 | #ifdef DEBUG | |
465 | static int msic_set(void *data, u64 val) | |
466 | { | |
467 | struct axon_msic *msic = data; | |
468 | out_le32(msic->trigger, val); | |
469 | return 0; | |
470 | } | |
471 | ||
472 | static int msic_get(void *data, u64 *val) | |
473 | { | |
474 | *val = 0; | |
475 | return 0; | |
476 | } | |
477 | ||
478 | DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n"); | |
479 | ||
480 | void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic) | |
481 | { | |
482 | char name[8]; | |
483 | u64 addr; | |
484 | ||
485 | addr = of_translate_address(dn, of_get_property(dn, "reg", NULL)); | |
486 | if (addr == OF_BAD_ADDR) { | |
487 | pr_debug("axon_msi: couldn't translate reg property\n"); | |
488 | return; | |
489 | } | |
490 | ||
491 | msic->trigger = ioremap(addr, 0x4); | |
492 | if (!msic->trigger) { | |
493 | pr_debug("axon_msi: ioremap failed\n"); | |
494 | return; | |
495 | } | |
496 | ||
497 | snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn)); | |
498 | ||
499 | if (!debugfs_create_file(name, 0600, powerpc_debugfs_root, | |
500 | msic, &fops_msic)) { | |
501 | pr_debug("axon_msi: debugfs_create_file failed!\n"); | |
502 | return; | |
503 | } | |
504 | } | |
505 | #endif /* DEBUG */ |