[deliverable/linux.git] / arch / powerpc / platforms / cell / axon_msi.c

/*
 * Copyright 2007, Michael Ellerman, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */


#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/of_platform.h>
#include <linux/debugfs.h>
#include <linux/slab.h>

#include <asm/dcr.h>
#include <asm/machdep.h>
#include <asm/prom.h>


/*
 * MSIC registers, specified as offsets from dcr_base
 */
#define MSIC_CTRL_REG	0x0

/* Base Address registers specify FIFO location in BE memory */
#define MSIC_BASE_ADDR_HI_REG	0x3
#define MSIC_BASE_ADDR_LO_REG	0x4

/* Hold the read/write offsets into the FIFO */
#define MSIC_READ_OFFSET_REG	0x5
#define MSIC_WRITE_OFFSET_REG	0x6


/* MSIC control register flags */
#define MSIC_CTRL_ENABLE		0x0001
#define MSIC_CTRL_FIFO_FULL_ENABLE	0x0002
#define MSIC_CTRL_IRQ_ENABLE		0x0008
#define MSIC_CTRL_FULL_STOP_ENABLE	0x0010

/*
 * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
 * Currently we're using a 64KB FIFO size.
 */
#define MSIC_FIFO_SIZE_SHIFT	16
#define MSIC_FIFO_SIZE_BYTES	(1 << MSIC_FIFO_SIZE_SHIFT)

/*
 * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
 * 8-9 of the MSIC control reg.
 */
#define MSIC_CTRL_FIFO_SIZE	(((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)

/*
 * We need to mask the read/write offsets to make sure they stay within
 * the bounds of the FIFO. Also they should always be 16-byte aligned.
 */
#define MSIC_FIFO_SIZE_MASK	((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)

/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
#define MSIC_FIFO_ENTRY_SIZE	0x10


struct axon_msic {
	struct irq_host *irq_host;
	__le32 *fifo_virt;
	dma_addr_t fifo_phys;
	dcr_host_t dcr_host;
	u32 read_offset;
#ifdef DEBUG
	u32 __iomem *trigger;
#endif
};

#ifdef DEBUG
void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
#else
static inline void axon_msi_debug_setup(struct device_node *dn,
					struct axon_msic *msic) { }
#endif


static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
{
	pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);

	dcr_write(msic->dcr_host, dcr_n, val);
}

static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct axon_msic *msic = irq_get_handler_data(irq);
	u32 write_offset, msi;
	int idx;
	int retry = 0;

	write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
	pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);

	/* write_offset doesn't wrap properly, so we have to mask it */
	write_offset &= MSIC_FIFO_SIZE_MASK;

	while (msic->read_offset != write_offset && retry < 100) {
		idx  = msic->read_offset / sizeof(__le32);
		msi  = le32_to_cpu(msic->fifo_virt[idx]);
		msi &= 0xFFFF;

		pr_devel("axon_msi: woff %x roff %x msi %x\n",
			  write_offset, msic->read_offset, msi);

		if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) {
			generic_handle_irq(msi);
			msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
		} else {
			/*
			 * Reading the MSIC_WRITE_OFFSET_REG does not
			 * reliably flush the outstanding DMA to the
			 * FIFO buffer. Here we were reading stale
			 * data, so we need to retry.
			 */
			udelay(1);
			retry++;
			pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
			continue;
		}

		if (retry) {
			pr_devel("axon_msi: late irq 0x%x, retry %d\n",
				 msi, retry);
			retry = 0;
		}

		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
		msic->read_offset &= MSIC_FIFO_SIZE_MASK;
	}

	if (retry) {
		printk(KERN_WARNING "axon_msi: irq timed out\n");

		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
		msic->read_offset &= MSIC_FIFO_SIZE_MASK;
	}

	chip->irq_eoi(&desc->irq_data);
}

static struct axon_msic *find_msi_translator(struct pci_dev *dev)
{
	struct irq_host *irq_host;
	struct device_node *dn, *tmp;
	const phandle *ph;
	struct axon_msic *msic = NULL;

	dn = of_node_get(pci_device_to_OF_node(dev));
	if (!dn) {
		dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
		return NULL;
	}

	for (; dn; dn = of_get_next_parent(dn)) {
		ph = of_get_property(dn, "msi-translator", NULL);
		if (ph)
			break;
	}

	if (!ph) {
		dev_dbg(&dev->dev,
			"axon_msi: no msi-translator property found\n");
		goto out_error;
	}

	tmp = dn;
	dn = of_find_node_by_phandle(*ph);
	of_node_put(tmp);
	if (!dn) {
		dev_dbg(&dev->dev,
			"axon_msi: msi-translator doesn't point to a node\n");
		goto out_error;
	}

	irq_host = irq_find_host(dn);
	if (!irq_host) {
		dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
			dn->full_name);
		goto out_error;
	}

	msic = irq_host->host_data;

out_error:
	of_node_put(dn);

	return msic;
}

static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
{
	if (!find_msi_translator(dev))
		return -ENODEV;

	return 0;
}

static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
{
	struct device_node *dn;
	struct msi_desc *entry;
	int len;
	const u32 *prop;

	dn = of_node_get(pci_device_to_OF_node(dev));
	if (!dn) {
		dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
		return -ENODEV;
	}

	entry = list_first_entry(&dev->msi_list, struct msi_desc, list);

	for (; dn; dn = of_get_next_parent(dn)) {
		if (entry->msi_attrib.is_64) {
			prop = of_get_property(dn, "msi-address-64", &len);
			if (prop)
				break;
		}

		prop = of_get_property(dn, "msi-address-32", &len);
		if (prop)
			break;
	}

	if (!prop) {
		dev_dbg(&dev->dev,
			"axon_msi: no msi-address-(32|64) properties found\n");
		return -ENOENT;
	}

	switch (len) {
	case 8:
		msg->address_hi = prop[0];
		msg->address_lo = prop[1];
		break;
	case 4:
		msg->address_hi = 0;
		msg->address_lo = prop[0];
		break;
	default:
		dev_dbg(&dev->dev,
			"axon_msi: malformed msi-address-(32|64) property\n");
		of_node_put(dn);
		return -EINVAL;
	}

	of_node_put(dn);

	return 0;
}

static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	unsigned int virq, rc;
	struct msi_desc *entry;
	struct msi_msg msg;
	struct axon_msic *msic;

	msic = find_msi_translator(dev);
	if (!msic)
		return -ENODEV;

	rc = setup_msi_msg_address(dev, &msg);
	if (rc)
		return rc;

	/* We rely on being able to stash a virq in a u16 */
	BUILD_BUG_ON(NR_IRQS > 65536);

	list_for_each_entry(entry, &dev->msi_list, list) {
		virq = irq_create_direct_mapping(msic->irq_host);
		if (virq == NO_IRQ) {
			dev_warn(&dev->dev,
				 "axon_msi: virq allocation failed!\n");
			return -1;
		}
		dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);

		irq_set_msi_desc(virq, entry);
		msg.data = virq;
		write_msi_msg(virq, &msg);
	}

	return 0;
}

static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
{
	struct msi_desc *entry;

	dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");

	list_for_each_entry(entry, &dev->msi_list, list) {
		if (entry->irq == NO_IRQ)
			continue;

		irq_set_msi_desc(entry->irq, NULL);
		irq_dispose_mapping(entry->irq);
	}
}

static struct irq_chip msic_irq_chip = {
	.irq_mask	= mask_msi_irq,
	.irq_unmask	= unmask_msi_irq,
	.irq_shutdown	= mask_msi_irq,
	.name		= "AXON-MSI",
};

static int msic_host_map(struct irq_host *h, unsigned int virq,
			 irq_hw_number_t hw)
{
	irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);

	return 0;
}

static struct irq_host_ops msic_host_ops = {
	.map	= msic_host_map,
};

static void axon_msi_shutdown(struct platform_device *device)
{
	struct axon_msic *msic = dev_get_drvdata(&device->dev);
	u32 tmp;

	pr_devel("axon_msi: disabling %s\n",
		  msic->irq_host->of_node->full_name);
	tmp  = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
	tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
}

static int axon_msi_probe(struct platform_device *device)
{
	struct device_node *dn = device->dev.of_node;
	struct axon_msic *msic;
	unsigned int virq;
	int dcr_base, dcr_len;

	pr_devel("axon_msi: setting up dn %s\n", dn->full_name);

	msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
	if (!msic) {
		printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
		       dn->full_name);
		goto out;
	}

	dcr_base = dcr_resource_start(dn, 0);
	dcr_len = dcr_resource_len(dn, 0);

	if (dcr_base == 0 || dcr_len == 0) {
		printk(KERN_ERR
		       "axon_msi: couldn't parse dcr properties on %s\n",
			dn->full_name);
		goto out_free_msic;
	}

	msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
	if (!DCR_MAP_OK(msic->dcr_host)) {
		printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
		       dn->full_name);
		goto out_free_msic;
	}

	msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
					     &msic->fifo_phys, GFP_KERNEL);
	if (!msic->fifo_virt) {
		printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
		       dn->full_name);
		goto out_free_msic;
	}

	virq = irq_of_parse_and_map(dn, 0);
	if (virq == NO_IRQ) {
		printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
		       dn->full_name);
		goto out_free_fifo;
	}
	memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);

	msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP,
					NR_IRQS, &msic_host_ops, 0);
	if (!msic->irq_host) {
		printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
		       dn->full_name);
		goto out_free_fifo;
	}

	msic->irq_host->host_data = msic;

	irq_set_handler_data(virq, msic);
	irq_set_chained_handler(virq, axon_msi_cascade);
	pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);

	/* Enable the MSIC hardware */
	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
				  msic->fifo_phys & 0xFFFFFFFF);
	msic_dcr_write(msic, MSIC_CTRL_REG,
			MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
			MSIC_CTRL_FIFO_SIZE);

	msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
				& MSIC_FIFO_SIZE_MASK;

	dev_set_drvdata(&device->dev, msic);

	ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
	ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
	ppc_md.msi_check_device = axon_msi_check_device;

	axon_msi_debug_setup(dn, msic);

	printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);

	return 0;

out_free_fifo:
	dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
			  msic->fifo_phys);
out_free_msic:
	kfree(msic);
out:

	return -1;
}

static const struct of_device_id axon_msi_device_id[] = {
	{
		.compatible	= "ibm,axon-msic"
	},
	{}
};

static struct platform_driver axon_msi_driver = {
	.probe		= axon_msi_probe,
	.shutdown	= axon_msi_shutdown,
	.driver = {
		.name = "axon-msi",
		.owner = THIS_MODULE,
		.of_match_table = axon_msi_device_id,
	},
};

static int __init axon_msi_init(void)
{
	return platform_driver_register(&axon_msi_driver);
}
subsys_initcall(axon_msi_init);


#ifdef DEBUG
static int msic_set(void *data, u64 val)
{
	struct axon_msic *msic = data;
	out_le32(msic->trigger, val);
	return 0;
}

static int msic_get(void *data, u64 *val)
{
	*val = 0;
	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");

void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
{
	char name[8];
	u64 addr;

	addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
	if (addr == OF_BAD_ADDR) {
		pr_devel("axon_msi: couldn't translate reg property\n");
		return;
	}

	msic->trigger = ioremap(addr, 0x4);
	if (!msic->trigger) {
		pr_devel("axon_msi: ioremap failed\n");
		return;
	}

	snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));

	if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
				 msic, &fops_msic)) {
		pr_devel("axon_msi: debugfs_create_file failed!\n");
		return;
	}
}
#endif /* DEBUG */
Commit	Line	Data
ce21b3c9 ME	1	/*
	2	* Copyright 2007, Michael Ellerman, IBM Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9
	10
	11	#include <linux/interrupt.h>
	12	#include <linux/irq.h>
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
	15	#include <linux/msi.h>
e4347dfb	16	#include <linux/of_platform.h>
72cac213	17	#include <linux/debugfs.h>
5a0e3ad6	18	#include <linux/slab.h>
ce21b3c9 ME	19
	20	#include <asm/dcr.h>
	21	#include <asm/machdep.h>
	22	#include <asm/prom.h>
	23
	24
	25	/*
	26	* MSIC registers, specified as offsets from dcr_base
	27	*/
	28	#define MSIC_CTRL_REG 0x0
	29
	30	/* Base Address registers specify FIFO location in BE memory */
	31	#define MSIC_BASE_ADDR_HI_REG 0x3
	32	#define MSIC_BASE_ADDR_LO_REG 0x4
	33
	34	/* Hold the read/write offsets into the FIFO */
	35	#define MSIC_READ_OFFSET_REG 0x5
	36	#define MSIC_WRITE_OFFSET_REG 0x6
	37
	38
	39	/* MSIC control register flags */
	40	#define MSIC_CTRL_ENABLE 0x0001
	41	#define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
	42	#define MSIC_CTRL_IRQ_ENABLE 0x0008
	43	#define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
	44
	45	/*
	46	* The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
	47	* Currently we're using a 64KB FIFO size.
	48	*/
	49	#define MSIC_FIFO_SIZE_SHIFT 16
	50	#define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
	51
	52	/*
	53	* To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
	54	* 8-9 of the MSIC control reg.
	55	*/
	56	#define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
	57
	58	/*
	59	* We need to mask the read/write offsets to make sure they stay within
	60	* the bounds of the FIFO. Also they should always be 16-byte aligned.
	61	*/
	62	#define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
	63
	64	/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
	65	#define MSIC_FIFO_ENTRY_SIZE 0x10
	66
	67
	68	struct axon_msic {
ce21b3c9	69	struct irq_host *irq_host;
de4c928b ME	70	__le32 *fifo_virt;
de4c928b ME	71	dma_addr_t fifo_phys;
ce21b3c9	72	dcr_host_t dcr_host;
ce21b3c9	73	u32 read_offset;
72cac213 ME	74	#ifdef DEBUG
	75	u32 __iomem *trigger;
	76	#endif
ce21b3c9 ME	77	};
ce21b3c9 ME	78
72cac213 ME	79	#ifdef DEBUG
	80	void axon_msi_debug_setup(struct device_node dn, struct axon_msic msic);
	81	#else
	82	static inline void axon_msi_debug_setup(struct device_node *dn,
	83	struct axon_msic *msic) { }
	84	#endif
	85
	86
ce21b3c9 ME	87	static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
ce21b3c9 ME	88	{
33875f03	89	pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
ce21b3c9	90
83f34df4	91	dcr_write(msic->dcr_host, dcr_n, val);
ce21b3c9 ME	92	}
ce21b3c9 ME	93
ce21b3c9 ME	94	static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
ce21b3c9 ME	95	{
ec775d0e TG	96	struct irq_chip *chip = irq_desc_get_chip(desc);
ec775d0e TG	97	struct axon_msic *msic = irq_get_handler_data(irq);
ce21b3c9 ME	98	u32 write_offset, msi;
ce21b3c9 ME	99	int idx;
d015fe99	100	int retry = 0;
ce21b3c9	101
2843e7f7	102	write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
33875f03	103	pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);
ce21b3c9 ME	104
	105	/* write_offset doesn't wrap properly, so we have to mask it */
	106	write_offset &= MSIC_FIFO_SIZE_MASK;
	107
d015fe99	108	while (msic->read_offset != write_offset && retry < 100) {
ce21b3c9	109	idx = msic->read_offset / sizeof(__le32);
de4c928b	110	msi = le32_to_cpu(msic->fifo_virt[idx]);
ce21b3c9 ME	111	msi &= 0xFFFF;
ce21b3c9 ME	112
33875f03	113	pr_devel("axon_msi: woff %x roff %x msi %x\n",
ce21b3c9 ME	114	write_offset, msic->read_offset, msi);
ce21b3c9 ME	115
d015fe99 AB	116	if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) {
	117	generic_handle_irq(msi);
	118	msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
	119	} else {
	120	/*
	121	* Reading the MSIC_WRITE_OFFSET_REG does not
	122	* reliably flush the outstanding DMA to the
	123	* FIFO buffer. Here we were reading stale
	124	* data, so we need to retry.
	125	*/
	126	udelay(1);
	127	retry++;
33875f03	128	pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
d015fe99 AB	129	continue;
	130	}
	131
	132	if (retry) {
33875f03	133	pr_devel("axon_msi: late irq 0x%x, retry %d\n",
d015fe99 AB	134	msi, retry);
	135	retry = 0;
	136	}
	137
ce21b3c9 ME	138	msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
ce21b3c9 ME	139	msic->read_offset &= MSIC_FIFO_SIZE_MASK;
d015fe99	140	}
ce21b3c9	141
d015fe99 AB	142	if (retry) {
	143	printk(KERN_WARNING "axon_msi: irq timed out\n");
	144
	145	msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
	146	msic->read_offset &= MSIC_FIFO_SIZE_MASK;
ce21b3c9 ME	147	}
ce21b3c9 ME	148
d1ae63d4	149	chip->irq_eoi(&desc->irq_data);
ce21b3c9 ME	150	}
	151
	152	static struct axon_msic find_msi_translator(struct pci_dev dev)
	153	{
	154	struct irq_host *irq_host;
	155	struct device_node dn, tmp;
	156	const phandle *ph;
	157	struct axon_msic *msic = NULL;
	158
db220b23	159	dn = of_node_get(pci_device_to_OF_node(dev));
ce21b3c9 ME	160	if (!dn) {
	161	dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
	162	return NULL;
	163	}
	164
988479eb	165	for (; dn; dn = of_get_next_parent(dn)) {
ce21b3c9 ME	166	ph = of_get_property(dn, "msi-translator", NULL);
	167	if (ph)
	168	break;
	169	}
	170
	171	if (!ph) {
	172	dev_dbg(&dev->dev,
	173	"axon_msi: no msi-translator property found\n");
	174	goto out_error;
	175	}
	176
	177	tmp = dn;
	178	dn = of_find_node_by_phandle(*ph);
c6d01179	179	of_node_put(tmp);
ce21b3c9 ME	180	if (!dn) {
	181	dev_dbg(&dev->dev,
	182	"axon_msi: msi-translator doesn't point to a node\n");
	183	goto out_error;
	184	}
	185
	186	irq_host = irq_find_host(dn);
	187	if (!irq_host) {
	188	dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
	189	dn->full_name);
	190	goto out_error;
	191	}
	192
	193	msic = irq_host->host_data;
	194
	195	out_error:
	196	of_node_put(dn);
ce21b3c9 ME	197
	198	return msic;
	199	}
	200
	201	static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
	202	{
	203	if (!find_msi_translator(dev))
	204	return -ENODEV;
	205
	206	return 0;
	207	}
	208
	209	static int setup_msi_msg_address(struct pci_dev dev, struct msi_msg msg)
	210	{
988479eb	211	struct device_node *dn;
ce21b3c9 ME	212	struct msi_desc *entry;
	213	int len;
	214	const u32 *prop;
	215
db220b23	216	dn = of_node_get(pci_device_to_OF_node(dev));
ce21b3c9 ME	217	if (!dn) {
	218	dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
	219	return -ENODEV;
	220	}
	221
	222	entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
	223
988479eb	224	for (; dn; dn = of_get_next_parent(dn)) {
ce21b3c9 ME	225	if (entry->msi_attrib.is_64) {
	226	prop = of_get_property(dn, "msi-address-64", &len);
	227	if (prop)
	228	break;
	229	}
	230
	231	prop = of_get_property(dn, "msi-address-32", &len);
	232	if (prop)
	233	break;
	234	}
	235
	236	if (!prop) {
	237	dev_dbg(&dev->dev,
	238	"axon_msi: no msi-address-(32\|64) properties found\n");
	239	return -ENOENT;
	240	}
	241
	242	switch (len) {
	243	case 8:
	244	msg->address_hi = prop[0];
	245	msg->address_lo = prop[1];
	246	break;
	247	case 4:
	248	msg->address_hi = 0;
	249	msg->address_lo = prop[0];
	250	break;
	251	default:
	252	dev_dbg(&dev->dev,
	253	"axon_msi: malformed msi-address-(32\|64) property\n");
	254	of_node_put(dn);
	255	return -EINVAL;
	256	}
	257
	258	of_node_put(dn);
	259
	260	return 0;
	261	}
	262
	263	static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
	264	{
	265	unsigned int virq, rc;
	266	struct msi_desc *entry;
	267	struct msi_msg msg;
	268	struct axon_msic *msic;
	269
	270	msic = find_msi_translator(dev);
	271	if (!msic)
	272	return -ENODEV;
	273
	274	rc = setup_msi_msg_address(dev, &msg);
	275	if (rc)
	276	return rc;
	277
	278	/* We rely on being able to stash a virq in a u16 */
	279	BUILD_BUG_ON(NR_IRQS > 65536);
	280
	281	list_for_each_entry(entry, &dev->msi_list, list) {
	282	virq = irq_create_direct_mapping(msic->irq_host);
	283	if (virq == NO_IRQ) {
	284	dev_warn(&dev->dev,
	285	"axon_msi: virq allocation failed!\n");
	286	return -1;
	287	}
	288	dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
289
ec775d0e	290	irq_set_msi_desc(virq, entry);
ce21b3c9 ME	291	msg.data = virq;
	292	write_msi_msg(virq, &msg);
	293	}
	294
	295	return 0;
	296	}
	297
	298	static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
	299	{
	300	struct msi_desc *entry;
	301
	302	dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
	303
	304	list_for_each_entry(entry, &dev->msi_list, list) {
	305	if (entry->irq == NO_IRQ)
	306	continue;
	307
ec775d0e	308	irq_set_msi_desc(entry->irq, NULL);
ce21b3c9 ME	309	irq_dispose_mapping(entry->irq);
	310	}
	311	}
	312
	313	static struct irq_chip msic_irq_chip = {
1c9db525 TG	314	.irq_mask = mask_msi_irq,
	315	.irq_unmask = unmask_msi_irq,
	316	.irq_shutdown = mask_msi_irq,
b27df672	317	.name = "AXON-MSI",
ce21b3c9 ME	318	};
	319
	320	static int msic_host_map(struct irq_host *h, unsigned int virq,
	321	irq_hw_number_t hw)
	322	{
ec775d0e	323	irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
ce21b3c9 ME	324
	325	return 0;
	326	}
	327
ce21b3c9	328	static struct irq_host_ops msic_host_ops = {
ce21b3c9 ME	329	.map = msic_host_map,
	330	};
	331
00006124	332	static void axon_msi_shutdown(struct platform_device *device)
ce21b3c9	333	{
86c27656	334	struct axon_msic *msic = dev_get_drvdata(&device->dev);
ce21b3c9 ME	335	u32 tmp;
ce21b3c9 ME	336
33875f03	337	pr_devel("axon_msi: disabling %s\n",
e4347dfb ME	338	msic->irq_host->of_node->full_name);
	339	tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
	340	tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
	341	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
ce21b3c9 ME	342	}
ce21b3c9 ME	343
00006124	344	static int axon_msi_probe(struct platform_device *device)
ce21b3c9	345	{
61c7a080	346	struct device_node *dn = device->dev.of_node;
ce21b3c9 ME	347	struct axon_msic *msic;
ce21b3c9 ME	348	unsigned int virq;
4acb8896	349	int dcr_base, dcr_len;
ce21b3c9	350
33875f03	351	pr_devel("axon_msi: setting up dn %s\n", dn->full_name);
ce21b3c9 ME	352
	353	msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
	354	if (!msic) {
	355	printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
	356	dn->full_name);
	357	goto out;
	358	}
	359
4acb8896	360	dcr_base = dcr_resource_start(dn, 0);
ce21b3c9 ME	361	dcr_len = dcr_resource_len(dn, 0);
ce21b3c9 ME	362
4acb8896	363	if (dcr_base == 0 \|\| dcr_len == 0) {
ce21b3c9 ME	364	printk(KERN_ERR
	365	"axon_msi: couldn't parse dcr properties on %s\n",
	366	dn->full_name);
aee7a283	367	goto out_free_msic;
ce21b3c9 ME	368	}
ce21b3c9 ME	369
4acb8896	370	msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
ce21b3c9 ME	371	if (!DCR_MAP_OK(msic->dcr_host)) {
	372	printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
	373	dn->full_name);
	374	goto out_free_msic;
	375	}
	376
de4c928b ME	377	msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
	378	&msic->fifo_phys, GFP_KERNEL);
	379	if (!msic->fifo_virt) {
ce21b3c9 ME	380	printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
	381	dn->full_name);
	382	goto out_free_msic;
	383	}
	384
997526db ME	385	virq = irq_of_parse_and_map(dn, 0);
	386	if (virq == NO_IRQ) {
	387	printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
	388	dn->full_name);
	389	goto out_free_fifo;
	390	}
d015fe99	391	memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
997526db	392
19fc65b5	393	msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP,
52964f87	394	NR_IRQS, &msic_host_ops, 0);
ce21b3c9 ME	395	if (!msic->irq_host) {
	396	printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
	397	dn->full_name);
	398	goto out_free_fifo;
	399	}
	400
	401	msic->irq_host->host_data = msic;
	402
ec775d0e TG	403	irq_set_handler_data(virq, msic);
ec775d0e TG	404	irq_set_chained_handler(virq, axon_msi_cascade);
33875f03	405	pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
ce21b3c9 ME	406
ce21b3c9 ME	407	/* Enable the MSIC hardware */
de4c928b	408	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
ce21b3c9	409	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
de4c928b	410	msic->fifo_phys & 0xFFFFFFFF);
ce21b3c9 ME	411	msic_dcr_write(msic, MSIC_CTRL_REG,
	412	MSIC_CTRL_IRQ_ENABLE \| MSIC_CTRL_ENABLE \|
	413	MSIC_CTRL_FIFO_SIZE);
	414
23e0e8af AB	415	msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
	416	& MSIC_FIFO_SIZE_MASK;
	417
86c27656	418	dev_set_drvdata(&device->dev, msic);
e4347dfb ME	419
	420	ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
	421	ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
	422	ppc_md.msi_check_device = axon_msi_check_device;
ce21b3c9	423
72cac213 ME	424	axon_msi_debug_setup(dn, msic);
72cac213 ME	425
ce21b3c9 ME	426	printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);
	427
	428	return 0;
	429
ce21b3c9	430	out_free_fifo:
de4c928b ME	431	dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
de4c928b ME	432	msic->fifo_phys);
ce21b3c9 ME	433	out_free_msic:
	434	kfree(msic);
	435	out:
	436
	437	return -1;
	438	}
	439
e4347dfb ME	440	static const struct of_device_id axon_msi_device_id[] = {
	441	{
	442	.compatible = "ibm,axon-msic"
	443	},
	444	{}
	445	};
ce21b3c9	446
00006124	447	static struct platform_driver axon_msi_driver = {
e4347dfb ME	448	.probe = axon_msi_probe,
e4347dfb ME	449	.shutdown = axon_msi_shutdown,
4018294b GL	450	.driver = {
	451	.name = "axon-msi",
	452	.owner = THIS_MODULE,
	453	.of_match_table = axon_msi_device_id,
e4347dfb ME	454	},
e4347dfb ME	455	};
ce21b3c9	456
e4347dfb ME	457	static int __init axon_msi_init(void)
e4347dfb ME	458	{
00006124	459	return platform_driver_register(&axon_msi_driver);
ce21b3c9	460	}
e4347dfb	461	subsys_initcall(axon_msi_init);
72cac213 ME	462
	463
	464	#ifdef DEBUG
	465	static int msic_set(void *data, u64 val)
	466	{
	467	struct axon_msic *msic = data;
	468	out_le32(msic->trigger, val);
	469	return 0;
	470	}
	471
	472	static int msic_get(void data, u64 val)
	473	{
	474	*val = 0;
	475	return 0;
	476	}
	477
	478	DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");
	479
	480	void axon_msi_debug_setup(struct device_node dn, struct axon_msic msic)
	481	{
	482	char name[8];
	483	u64 addr;
	484
	485	addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
	486	if (addr == OF_BAD_ADDR) {
33875f03	487	pr_devel("axon_msi: couldn't translate reg property\n");
72cac213 ME	488	return;
	489	}
	490
	491	msic->trigger = ioremap(addr, 0x4);
	492	if (!msic->trigger) {
33875f03	493	pr_devel("axon_msi: ioremap failed\n");
72cac213 ME	494	return;
	495	}
	496
	497	snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));
	498
	499	if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
	500	msic, &fops_msic)) {
33875f03	501	pr_devel("axon_msi: debugfs_create_file failed!\n");
72cac213 ME	502	return;
	503	}
	504	}
	505	#endif /* DEBUG */