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32f39b05 IK |
1 | /* |
2 | * Celleb/Beat Interrupt controller | |
3 | * | |
4 | * (C) Copyright 2006-2007 TOSHIBA CORPORATION | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/percpu.h> | |
25 | #include <linux/types.h> | |
26 | ||
27 | #include <asm/machdep.h> | |
28 | ||
ad2c6987 IK |
29 | #include "beat_interrupt.h" |
30 | #include "beat_wrapper.h" | |
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31 | |
32 | #define MAX_IRQS NR_IRQS | |
5181e790 | 33 | static DEFINE_RAW_SPINLOCK(beatic_irq_mask_lock); |
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34 | static uint64_t beatic_irq_mask_enable[(MAX_IRQS+255)/64]; |
35 | static uint64_t beatic_irq_mask_ack[(MAX_IRQS+255)/64]; | |
36 | ||
2fe37a6e | 37 | static struct irq_host *beatic_host; |
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38 | |
39 | /* | |
40 | * In this implementation, "virq" == "IRQ plug number", | |
41 | * "(irq_hw_number_t)hwirq" == "IRQ outlet number". | |
42 | */ | |
43 | ||
44 | /* assumption: locked */ | |
45 | static inline void beatic_update_irq_mask(unsigned int irq_plug) | |
46 | { | |
47 | int off; | |
48 | unsigned long masks[4]; | |
49 | ||
50 | off = (irq_plug / 256) * 4; | |
51 | masks[0] = beatic_irq_mask_enable[off + 0] | |
2fe37a6e | 52 | & beatic_irq_mask_ack[off + 0]; |
32f39b05 | 53 | masks[1] = beatic_irq_mask_enable[off + 1] |
2fe37a6e | 54 | & beatic_irq_mask_ack[off + 1]; |
32f39b05 | 55 | masks[2] = beatic_irq_mask_enable[off + 2] |
2fe37a6e | 56 | & beatic_irq_mask_ack[off + 2]; |
32f39b05 | 57 | masks[3] = beatic_irq_mask_enable[off + 3] |
2fe37a6e | 58 | & beatic_irq_mask_ack[off + 3]; |
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59 | if (beat_set_interrupt_mask(irq_plug&~255UL, |
60 | masks[0], masks[1], masks[2], masks[3]) != 0) | |
61 | panic("Failed to set mask IRQ!"); | |
62 | } | |
63 | ||
d1ae63d4 | 64 | static void beatic_mask_irq(struct irq_data *d) |
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65 | { |
66 | unsigned long flags; | |
67 | ||
5181e790 | 68 | raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags); |
d1ae63d4 LB |
69 | beatic_irq_mask_enable[d->irq/64] &= ~(1UL << (63 - (d->irq%64))); |
70 | beatic_update_irq_mask(d->irq); | |
5181e790 | 71 | raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags); |
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72 | } |
73 | ||
d1ae63d4 | 74 | static void beatic_unmask_irq(struct irq_data *d) |
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75 | { |
76 | unsigned long flags; | |
77 | ||
5181e790 | 78 | raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags); |
d1ae63d4 LB |
79 | beatic_irq_mask_enable[d->irq/64] |= 1UL << (63 - (d->irq%64)); |
80 | beatic_update_irq_mask(d->irq); | |
5181e790 | 81 | raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags); |
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82 | } |
83 | ||
d1ae63d4 | 84 | static void beatic_ack_irq(struct irq_data *d) |
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85 | { |
86 | unsigned long flags; | |
87 | ||
5181e790 | 88 | raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags); |
d1ae63d4 LB |
89 | beatic_irq_mask_ack[d->irq/64] &= ~(1UL << (63 - (d->irq%64))); |
90 | beatic_update_irq_mask(d->irq); | |
5181e790 | 91 | raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags); |
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92 | } |
93 | ||
d1ae63d4 | 94 | static void beatic_end_irq(struct irq_data *d) |
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95 | { |
96 | s64 err; | |
97 | unsigned long flags; | |
98 | ||
d1ae63d4 | 99 | err = beat_downcount_of_interrupt(d->irq); |
2fe37a6e | 100 | if (err != 0) { |
32f39b05 | 101 | if ((err & 0xFFFFFFFF) != 0xFFFFFFF5) /* -11: wrong state */ |
fe333321 | 102 | panic("Failed to downcount IRQ! Error = %16llx", err); |
32f39b05 | 103 | |
d1ae63d4 | 104 | printk(KERN_ERR "IRQ over-downcounted, plug %d\n", d->irq); |
32f39b05 | 105 | } |
5181e790 | 106 | raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags); |
d1ae63d4 LB |
107 | beatic_irq_mask_ack[d->irq/64] |= 1UL << (63 - (d->irq%64)); |
108 | beatic_update_irq_mask(d->irq); | |
5181e790 | 109 | raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags); |
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110 | } |
111 | ||
112 | static struct irq_chip beatic_pic = { | |
fc380c0c | 113 | .name = "CELL-BEAT", |
d1ae63d4 LB |
114 | .irq_unmask = beatic_unmask_irq, |
115 | .irq_mask = beatic_mask_irq, | |
116 | .irq_eoi = beatic_end_irq, | |
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117 | }; |
118 | ||
119 | /* | |
120 | * Dispose binding hardware IRQ number (hw) and Virtuql IRQ number (virq), | |
121 | * update flags. | |
122 | * | |
123 | * Note that the number (virq) is already assigned at upper layer. | |
124 | */ | |
125 | static void beatic_pic_host_unmap(struct irq_host *h, unsigned int virq) | |
126 | { | |
127 | beat_destruct_irq_plug(virq); | |
128 | } | |
129 | ||
130 | /* | |
131 | * Create or update binding hardware IRQ number (hw) and Virtuql | |
132 | * IRQ number (virq). This is called only once for a given mapping. | |
133 | * | |
134 | * Note that the number (virq) is already assigned at upper layer. | |
135 | */ | |
136 | static int beatic_pic_host_map(struct irq_host *h, unsigned int virq, | |
137 | irq_hw_number_t hw) | |
138 | { | |
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139 | int64_t err; |
140 | ||
2fe37a6e IK |
141 | err = beat_construct_and_connect_irq_plug(virq, hw); |
142 | if (err < 0) | |
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143 | return -EIO; |
144 | ||
98488db9 | 145 | irq_set_status_flags(virq, IRQ_LEVEL); |
ec775d0e | 146 | irq_set_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq); |
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147 | return 0; |
148 | } | |
149 | ||
150 | /* | |
151 | * Update binding hardware IRQ number (hw) and Virtuql | |
152 | * IRQ number (virq). This is called only once for a given mapping. | |
153 | */ | |
154 | static void beatic_pic_host_remap(struct irq_host *h, unsigned int virq, | |
155 | irq_hw_number_t hw) | |
156 | { | |
157 | beat_construct_and_connect_irq_plug(virq, hw); | |
158 | } | |
159 | ||
160 | /* | |
161 | * Translate device-tree interrupt spec to irq_hw_number_t style (ulong), | |
162 | * to pass away to irq_create_mapping(). | |
163 | * | |
164 | * Called from irq_create_of_mapping() only. | |
165 | * Note: We have only 1 entry to translate. | |
166 | */ | |
167 | static int beatic_pic_host_xlate(struct irq_host *h, struct device_node *ct, | |
40d50cf7 | 168 | const u32 *intspec, unsigned int intsize, |
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169 | irq_hw_number_t *out_hwirq, |
170 | unsigned int *out_flags) | |
171 | { | |
40d50cf7 | 172 | const u64 *intspec2 = (const u64 *)intspec; |
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173 | |
174 | *out_hwirq = *intspec2; | |
175 | *out_flags |= IRQ_TYPE_LEVEL_LOW; | |
176 | return 0; | |
177 | } | |
178 | ||
8528ab84 ME |
179 | static int beatic_pic_host_match(struct irq_host *h, struct device_node *np) |
180 | { | |
181 | /* Match all */ | |
182 | return 1; | |
183 | } | |
184 | ||
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185 | static struct irq_host_ops beatic_pic_host_ops = { |
186 | .map = beatic_pic_host_map, | |
187 | .remap = beatic_pic_host_remap, | |
188 | .unmap = beatic_pic_host_unmap, | |
189 | .xlate = beatic_pic_host_xlate, | |
8528ab84 | 190 | .match = beatic_pic_host_match, |
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191 | }; |
192 | ||
193 | /* | |
194 | * Get an IRQ number | |
195 | * Note: returns VIRQ | |
196 | */ | |
197 | static inline unsigned int beatic_get_irq_plug(void) | |
198 | { | |
199 | int i; | |
200 | uint64_t pending[4], ub; | |
201 | ||
202 | for (i = 0; i < MAX_IRQS; i += 256) { | |
203 | beat_detect_pending_interrupts(i, pending); | |
204 | __asm__ ("cntlzd %0,%1":"=r"(ub): | |
205 | "r"(pending[0] & beatic_irq_mask_enable[i/64+0] | |
2fe37a6e | 206 | & beatic_irq_mask_ack[i/64+0])); |
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207 | if (ub != 64) |
208 | return i + ub + 0; | |
209 | __asm__ ("cntlzd %0,%1":"=r"(ub): | |
210 | "r"(pending[1] & beatic_irq_mask_enable[i/64+1] | |
2fe37a6e | 211 | & beatic_irq_mask_ack[i/64+1])); |
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212 | if (ub != 64) |
213 | return i + ub + 64; | |
214 | __asm__ ("cntlzd %0,%1":"=r"(ub): | |
215 | "r"(pending[2] & beatic_irq_mask_enable[i/64+2] | |
2fe37a6e | 216 | & beatic_irq_mask_ack[i/64+2])); |
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217 | if (ub != 64) |
218 | return i + ub + 128; | |
219 | __asm__ ("cntlzd %0,%1":"=r"(ub): | |
220 | "r"(pending[3] & beatic_irq_mask_enable[i/64+3] | |
2fe37a6e | 221 | & beatic_irq_mask_ack[i/64+3])); |
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222 | if (ub != 64) |
223 | return i + ub + 192; | |
224 | } | |
225 | ||
226 | return NO_IRQ; | |
227 | } | |
228 | unsigned int beatic_get_irq(void) | |
229 | { | |
230 | unsigned int ret; | |
231 | ||
232 | ret = beatic_get_irq_plug(); | |
233 | if (ret != NO_IRQ) | |
d1ae63d4 | 234 | beatic_ack_irq(irq_get_irq_data(ret)); |
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235 | return ret; |
236 | } | |
237 | ||
238 | /* | |
239 | */ | |
240 | void __init beatic_init_IRQ(void) | |
241 | { | |
242 | int i; | |
243 | ||
244 | memset(beatic_irq_mask_enable, 0, sizeof(beatic_irq_mask_enable)); | |
245 | memset(beatic_irq_mask_ack, 255, sizeof(beatic_irq_mask_ack)); | |
246 | for (i = 0; i < MAX_IRQS; i += 256) | |
247 | beat_set_interrupt_mask(i, 0L, 0L, 0L, 0L); | |
248 | ||
249 | /* Set out get_irq function */ | |
250 | ppc_md.get_irq = beatic_get_irq; | |
251 | ||
252 | /* Allocate an irq host */ | |
52964f87 | 253 | beatic_host = irq_alloc_host(NULL, IRQ_HOST_MAP_NOMAP, 0, |
2fe37a6e | 254 | &beatic_pic_host_ops, |
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255 | 0); |
256 | BUG_ON(beatic_host == NULL); | |
257 | irq_set_default_host(beatic_host); | |
258 | } | |
259 | ||
260 | #ifdef CONFIG_SMP | |
261 | ||
262 | /* Nullified to compile with SMP mode */ | |
263 | void beatic_setup_cpu(int cpu) | |
264 | { | |
265 | } | |
266 | ||
267 | void beatic_cause_IPI(int cpu, int mesg) | |
268 | { | |
269 | } | |
270 | ||
271 | void beatic_request_IPIs(void) | |
272 | { | |
273 | } | |
274 | #endif /* CONFIG_SMP */ | |
275 | ||
276 | void beatic_deinit_IRQ(void) | |
277 | { | |
278 | int i; | |
279 | ||
280 | for (i = 1; i < NR_IRQS; i++) | |
281 | beat_destruct_irq_plug(i); | |
282 | } |