[deliverable/linux.git] / arch / powerpc / platforms / cell / interrupt.c

/*
 * Cell Internal Interrupt Controller
 *
 * Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *                    IBM, Corp.
 *
 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
 *
 * Author: Arnd Bergmann <arndb@de.ibm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * TODO:
 * - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
 *   vs node numbers in the setup code
 * - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
 *   a non-active node to the active node)
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/percpu.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <linux/kernel_stat.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/prom.h>
#include <asm/ptrace.h>
#include <asm/machdep.h>
#include <asm/cell-regs.h>

#include "interrupt.h"

struct iic {
	struct cbe_iic_thread_regs __iomem *regs;
	u8 target_id;
	u8 eoi_stack[16];
	int eoi_ptr;
	struct device_node *node;
};

static DEFINE_PER_CPU(struct iic, cpu_iic);
#define IIC_NODE_COUNT	2
static struct irq_host *iic_host;

/* Convert between "pending" bits and hw irq number */
static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
{
	unsigned char unit = bits.source & 0xf;
	unsigned char node = bits.source >> 4;
	unsigned char class = bits.class & 3;

	/* Decode IPIs */
	if (bits.flags & CBE_IIC_IRQ_IPI)
		return IIC_IRQ_TYPE_IPI | (bits.prio >> 4);
	else
		return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit;
}

static void iic_mask(struct irq_data *d)
{
}

static void iic_unmask(struct irq_data *d)
{
}

static void iic_eoi(struct irq_data *d)
{
	struct iic *iic = &__get_cpu_var(cpu_iic);
	out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
	BUG_ON(iic->eoi_ptr < 0);
}

static struct irq_chip iic_chip = {
	.name = "CELL-IIC",
	.irq_mask = iic_mask,
	.irq_unmask = iic_unmask,
	.irq_eoi = iic_eoi,
};


static void iic_ioexc_eoi(struct irq_data *d)
{
}

static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc)
{
	struct irq_chip *chip = get_irq_desc_chip(desc);
	struct cbe_iic_regs __iomem *node_iic =
		(void __iomem *)get_irq_desc_data(desc);
	unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
	unsigned long bits, ack;
	int cascade;

	for (;;) {
		bits = in_be64(&node_iic->iic_is);
		if (bits == 0)
			break;
		/* pre-ack edge interrupts */
		ack = bits & IIC_ISR_EDGE_MASK;
		if (ack)
			out_be64(&node_iic->iic_is, ack);
		/* handle them */
		for (cascade = 63; cascade >= 0; cascade--)
			if (bits & (0x8000000000000000UL >> cascade)) {
				unsigned int cirq =
					irq_linear_revmap(iic_host,
							  base | cascade);
				if (cirq != NO_IRQ)
					generic_handle_irq(cirq);
			}
		/* post-ack level interrupts */
		ack = bits & ~IIC_ISR_EDGE_MASK;
		if (ack)
			out_be64(&node_iic->iic_is, ack);
	}
	chip->irq_eoi(&desc->irq_data);
}


static struct irq_chip iic_ioexc_chip = {
	.name = "CELL-IOEX",
	.irq_mask = iic_mask,
	.irq_unmask = iic_unmask,
	.irq_eoi = iic_ioexc_eoi,
};

/* Get an IRQ number from the pending state register of the IIC */
static unsigned int iic_get_irq(void)
{
	struct cbe_iic_pending_bits pending;
	struct iic *iic;
	unsigned int virq;

	iic = &__get_cpu_var(cpu_iic);
	*(unsigned long *) &pending =
		in_be64((u64 __iomem *) &iic->regs->pending_destr);
	if (!(pending.flags & CBE_IIC_IRQ_VALID))
		return NO_IRQ;
	virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
	if (virq == NO_IRQ)
		return NO_IRQ;
	iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
	BUG_ON(iic->eoi_ptr > 15);
	return virq;
}

void iic_setup_cpu(void)
{
	out_be64(&__get_cpu_var(cpu_iic).regs->prio, 0xff);
}

u8 iic_get_target_id(int cpu)
{
	return per_cpu(cpu_iic, cpu).target_id;
}

EXPORT_SYMBOL_GPL(iic_get_target_id);

#ifdef CONFIG_SMP

/* Use the highest interrupt priorities for IPI */
static inline int iic_ipi_to_irq(int ipi)
{
	return IIC_IRQ_TYPE_IPI + 0xf - ipi;
}

void iic_cause_IPI(int cpu, int mesg)
{
	out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - mesg) << 4);
}

struct irq_host *iic_get_irq_host(int node)
{
	return iic_host;
}
EXPORT_SYMBOL_GPL(iic_get_irq_host);

static irqreturn_t iic_ipi_action(int irq, void *dev_id)
{
	int ipi = (int)(long)dev_id;

	smp_message_recv(ipi);

	return IRQ_HANDLED;
}
static void iic_request_ipi(int ipi, const char *name)
{
	int virq;

	virq = irq_create_mapping(iic_host, iic_ipi_to_irq(ipi));
	if (virq == NO_IRQ) {
		printk(KERN_ERR
		       "iic: failed to map IPI %s\n", name);
		return;
	}
	if (request_irq(virq, iic_ipi_action, IRQF_DISABLED, name,
			(void *)(long)ipi))
		printk(KERN_ERR
		       "iic: failed to request IPI %s\n", name);
}

void iic_request_IPIs(void)
{
	iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call");
	iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched");
	iic_request_ipi(PPC_MSG_CALL_FUNC_SINGLE, "IPI-call-single");
#ifdef CONFIG_DEBUGGER
	iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
#endif /* CONFIG_DEBUGGER */
}

#endif /* CONFIG_SMP */


static int iic_host_match(struct irq_host *h, struct device_node *node)
{
	return of_device_is_compatible(node,
				    "IBM,CBEA-Internal-Interrupt-Controller");
}

static int iic_host_map(struct irq_host *h, unsigned int virq,
			irq_hw_number_t hw)
{
	switch (hw & IIC_IRQ_TYPE_MASK) {
	case IIC_IRQ_TYPE_IPI:
		set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
		break;
	case IIC_IRQ_TYPE_IOEXC:
		set_irq_chip_and_handler(virq, &iic_ioexc_chip,
					 handle_iic_irq);
		break;
	default:
		set_irq_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq);
	}
	return 0;
}

static int iic_host_xlate(struct irq_host *h, struct device_node *ct,
			   const u32 *intspec, unsigned int intsize,
			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)

{
	unsigned int node, ext, unit, class;
	const u32 *val;

	if (!of_device_is_compatible(ct,
				     "IBM,CBEA-Internal-Interrupt-Controller"))
		return -ENODEV;
	if (intsize != 1)
		return -ENODEV;
	val = of_get_property(ct, "#interrupt-cells", NULL);
	if (val == NULL || *val != 1)
		return -ENODEV;

	node = intspec[0] >> 24;
	ext = (intspec[0] >> 16) & 0xff;
	class = (intspec[0] >> 8) & 0xff;
	unit = intspec[0] & 0xff;

	/* Check if node is in supported range */
	if (node > 1)
		return -EINVAL;

	/* Build up interrupt number, special case for IO exceptions */
	*out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
	if (unit == IIC_UNIT_IIC && class == 1)
		*out_hwirq |= IIC_IRQ_TYPE_IOEXC | ext;
	else
		*out_hwirq |= IIC_IRQ_TYPE_NORMAL |
			(class << IIC_IRQ_CLASS_SHIFT) | unit;

	/* Dummy flags, ignored by iic code */
	*out_flags = IRQ_TYPE_EDGE_RISING;

	return 0;
}

static struct irq_host_ops iic_host_ops = {
	.match = iic_host_match,
	.map = iic_host_map,
	.xlate = iic_host_xlate,
};

static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
				struct device_node *node)
{
	/* XXX FIXME: should locate the linux CPU number from the HW cpu
	 * number properly. We are lucky for now
	 */
	struct iic *iic = &per_cpu(cpu_iic, hw_cpu);

	iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
	BUG_ON(iic->regs == NULL);

	iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe);
	iic->eoi_stack[0] = 0xff;
	iic->node = of_node_get(node);
	out_be64(&iic->regs->prio, 0);

	printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n",
	       hw_cpu, iic->target_id, node->full_name);
}

static int __init setup_iic(void)
{
	struct device_node *dn;
	struct resource r0, r1;
	unsigned int node, cascade, found = 0;
	struct cbe_iic_regs __iomem *node_iic;
	const u32 *np;

	for (dn = NULL;
	     (dn = of_find_node_by_name(dn,"interrupt-controller")) != NULL;) {
		if (!of_device_is_compatible(dn,
				     "IBM,CBEA-Internal-Interrupt-Controller"))
			continue;
		np = of_get_property(dn, "ibm,interrupt-server-ranges", NULL);
		if (np == NULL) {
			printk(KERN_WARNING "IIC: CPU association not found\n");
			of_node_put(dn);
			return -ENODEV;
		}
		if (of_address_to_resource(dn, 0, &r0) ||
		    of_address_to_resource(dn, 1, &r1)) {
			printk(KERN_WARNING "IIC: Can't resolve addresses\n");
			of_node_put(dn);
			return -ENODEV;
		}
		found++;
		init_one_iic(np[0], r0.start, dn);
		init_one_iic(np[1], r1.start, dn);

		/* Setup cascade for IO exceptions. XXX cleanup tricks to get
		 * node vs CPU etc...
		 * Note that we configure the IIC_IRR here with a hard coded
		 * priority of 1. We might want to improve that later.
		 */
		node = np[0] >> 1;
		node_iic = cbe_get_cpu_iic_regs(np[0]);
		cascade = node << IIC_IRQ_NODE_SHIFT;
		cascade |= 1 << IIC_IRQ_CLASS_SHIFT;
		cascade |= IIC_UNIT_IIC;
		cascade = irq_create_mapping(iic_host, cascade);
		if (cascade == NO_IRQ)
			continue;
		/*
		 * irq_data is a generic pointer that gets passed back
		 * to us later, so the forced cast is fine.
		 */
		set_irq_data(cascade, (void __force *)node_iic);
		set_irq_chained_handler(cascade , iic_ioexc_cascade);
		out_be64(&node_iic->iic_ir,
			 (1 << 12)		/* priority */ |
			 (node << 4)		/* dest node */ |
			 IIC_UNIT_THREAD_0	/* route them to thread 0 */);
		/* Flush pending (make sure it triggers if there is
		 * anything pending
		 */
		out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
	}

	if (found)
		return 0;
	else
		return -ENODEV;
}

void __init iic_init_IRQ(void)
{
	/* Setup an irq host data structure */
	iic_host = irq_alloc_host(NULL, IRQ_HOST_MAP_LINEAR, IIC_SOURCE_COUNT,
				  &iic_host_ops, IIC_IRQ_INVALID);
	BUG_ON(iic_host == NULL);
	irq_set_default_host(iic_host);

	/* Discover and initialize iics */
	if (setup_iic() < 0)
		panic("IIC: Failed to initialize !\n");

	/* Set master interrupt handling function */
	ppc_md.get_irq = iic_get_irq;

	/* Enable on current CPU */
	iic_setup_cpu();
}

void iic_set_interrupt_routing(int cpu, int thread, int priority)
{
	struct cbe_iic_regs __iomem *iic_regs = cbe_get_cpu_iic_regs(cpu);
	u64 iic_ir = 0;
	int node = cpu >> 1;

	/* Set which node and thread will handle the next interrupt */
	iic_ir |= CBE_IIC_IR_PRIO(priority) |
		  CBE_IIC_IR_DEST_NODE(node);
	if (thread == 0)
		iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0);
	else
		iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1);
	out_be64(&iic_regs->iic_ir, iic_ir);
}
Commit	Line	Data
cebf589c	1	/*
f3f66f59	2	* Cell Internal Interrupt Controller
cebf589c	3	*
0ebfff14 BH	4	* Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	5	* IBM, Corp.
	6	*
cebf589c AB	7	* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
	8	*
	9	* Author: Arnd Bergmann <arndb@de.ibm.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2, or (at your option)
	14	* any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
2e194583 BH	24	*
	25	* TODO:
	26	* - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
	27	* vs node numbers in the setup code
	28	* - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
	29	* a non-active node to the active node)
cebf589c AB	30	*/
cebf589c AB	31
cebf589c AB	32	#include <linux/interrupt.h>
cebf589c AB	33	#include <linux/irq.h>
2fb9d206	34	#include <linux/module.h>
cebf589c AB	35	#include <linux/percpu.h>
cebf589c AB	36	#include <linux/types.h>
0ebfff14	37	#include <linux/ioport.h>
5711fe90	38	#include <linux/kernel_stat.h>
cebf589c AB	39
	40	#include <asm/io.h>
	41	#include <asm/pgtable.h>
	42	#include <asm/prom.h>
	43	#include <asm/ptrace.h>
0ebfff14	44	#include <asm/machdep.h>
eef686a0	45	#include <asm/cell-regs.h>
cebf589c	46
f3f66f59	47	#include "interrupt.h"
cebf589c AB	48
cebf589c AB	49	struct iic {
acf7d768	50	struct cbe_iic_thread_regs __iomem *regs;
2fb9d206	51	u8 target_id;
b9e5b4e6 BH	52	u8 eoi_stack[16];
b9e5b4e6 BH	53	int eoi_ptr;
2e194583	54	struct device_node *node;
cebf589c AB	55	};
cebf589c AB	56
6b7487fc	57	static DEFINE_PER_CPU(struct iic, cpu_iic);
0ebfff14	58	#define IIC_NODE_COUNT 2
2e194583	59	static struct irq_host *iic_host;
0ebfff14 BH	60
	61	/* Convert between "pending" bits and hw irq number */
	62	static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
	63	{
	64	unsigned char unit = bits.source & 0xf;
2e194583 BH	65	unsigned char node = bits.source >> 4;
2e194583 BH	66	unsigned char class = bits.class & 3;
0ebfff14	67
2e194583	68	/* Decode IPIs */
0ebfff14	69	if (bits.flags & CBE_IIC_IRQ_IPI)
2e194583	70	return IIC_IRQ_TYPE_IPI \| (bits.prio >> 4);
0ebfff14	71	else
2e194583	72	return (node << IIC_IRQ_NODE_SHIFT) \| (class << 4) \| unit;
0ebfff14	73	}
cebf589c	74
d1ae63d4	75	static void iic_mask(struct irq_data *d)
cebf589c	76	{
cebf589c AB	77	}
cebf589c AB	78
d1ae63d4	79	static void iic_unmask(struct irq_data *d)
cebf589c AB	80	{
	81	}
	82
d1ae63d4	83	static void iic_eoi(struct irq_data *d)
cebf589c	84	{
6b7487fc	85	struct iic *iic = &__get_cpu_var(cpu_iic);
b9e5b4e6 BH	86	out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
b9e5b4e6 BH	87	BUG_ON(iic->eoi_ptr < 0);
cebf589c AB	88	}
cebf589c AB	89
b9e5b4e6	90	static struct irq_chip iic_chip = {
fc380c0c	91	.name = "CELL-IIC",
d1ae63d4 LB	92	.irq_mask = iic_mask,
	93	.irq_unmask = iic_unmask,
	94	.irq_eoi = iic_eoi,
cebf589c AB	95	};
cebf589c AB	96
2e194583	97
d1ae63d4	98	static void iic_ioexc_eoi(struct irq_data *d)
2e194583 BH	99	{
	100	}
	101
35a84c2f	102	static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc)
2e194583	103	{
d1ae63d4 LB	104	struct irq_chip *chip = get_irq_desc_chip(desc);
	105	struct cbe_iic_regs __iomem *node_iic =
	106	(void __iomem *)get_irq_desc_data(desc);
2e194583 BH	107	unsigned int base = (irq & 0xffffff00) \| IIC_IRQ_TYPE_IOEXC;
	108	unsigned long bits, ack;
	109	int cascade;
	110
	111	for (;;) {
	112	bits = in_be64(&node_iic->iic_is);
	113	if (bits == 0)
	114	break;
	115	/* pre-ack edge interrupts */
	116	ack = bits & IIC_ISR_EDGE_MASK;
	117	if (ack)
	118	out_be64(&node_iic->iic_is, ack);
	119	/* handle them */
	120	for (cascade = 63; cascade >= 0; cascade--)
	121	if (bits & (0x8000000000000000UL >> cascade)) {
	122	unsigned int cirq =
	123	irq_linear_revmap(iic_host,
	124	base \| cascade);
	125	if (cirq != NO_IRQ)
49f19ce4	126	generic_handle_irq(cirq);
2e194583 BH	127	}
	128	/* post-ack level interrupts */
	129	ack = bits & ~IIC_ISR_EDGE_MASK;
	130	if (ack)
	131	out_be64(&node_iic->iic_is, ack);
	132	}
d1ae63d4	133	chip->irq_eoi(&desc->irq_data);
2e194583 BH	134	}
	135
	136
	137	static struct irq_chip iic_ioexc_chip = {
fc380c0c	138	.name = "CELL-IOEX",
d1ae63d4 LB	139	.irq_mask = iic_mask,
	140	.irq_unmask = iic_unmask,
	141	.irq_eoi = iic_ioexc_eoi,
2e194583 BH	142	};
2e194583 BH	143
cebf589c	144	/* Get an IRQ number from the pending state register of the IIC */
35a84c2f	145	static unsigned int iic_get_irq(void)
d0e57c68	146	{
9e6ee340 GL	147	struct cbe_iic_pending_bits pending;
9e6ee340 GL	148	struct iic *iic;
2e194583	149	unsigned int virq;
9e6ee340	150
6b7487fc	151	iic = &__get_cpu_var(cpu_iic);
9e6ee340	152	(unsigned long ) &pending =
b36ac9e8	153	in_be64((u64 __iomem *) &iic->regs->pending_destr);
2e194583 BH	154	if (!(pending.flags & CBE_IIC_IRQ_VALID))
	155	return NO_IRQ;
	156	virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
	157	if (virq == NO_IRQ)
	158	return NO_IRQ;
9e6ee340 GL	159	iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
9e6ee340 GL	160	BUG_ON(iic->eoi_ptr > 15);
2e194583	161	return virq;
cebf589c AB	162	}
cebf589c AB	163
4bfac368 OJ	164	void iic_setup_cpu(void)
4bfac368 OJ	165	{
6b7487fc	166	out_be64(&__get_cpu_var(cpu_iic).regs->prio, 0xff);
4bfac368 OJ	167	}
	168
	169	u8 iic_get_target_id(int cpu)
	170	{
6b7487fc	171	return per_cpu(cpu_iic, cpu).target_id;
4bfac368 OJ	172	}
	173
	174	EXPORT_SYMBOL_GPL(iic_get_target_id);
	175
cebf589c	176	#ifdef CONFIG_SMP
a84195f3 AB	177
	178	/* Use the highest interrupt priorities for IPI */
	179	static inline int iic_ipi_to_irq(int ipi)
	180	{
2e194583	181	return IIC_IRQ_TYPE_IPI + 0xf - ipi;
a84195f3 AB	182	}
a84195f3 AB	183
cebf589c AB	184	void iic_cause_IPI(int cpu, int mesg)
cebf589c AB	185	{
6b7487fc	186	out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - mesg) << 4);
cebf589c AB	187	}
cebf589c AB	188
0ebfff14 BH	189	struct irq_host *iic_get_irq_host(int node)
0ebfff14 BH	190	{
2e194583	191	return iic_host;
0ebfff14 BH	192	}
	193	EXPORT_SYMBOL_GPL(iic_get_irq_host);
	194
7d12e780	195	static irqreturn_t iic_ipi_action(int irq, void *dev_id)
cebf589c	196	{
0ebfff14 BH	197	int ipi = (int)(long)dev_id;
0ebfff14 BH	198
7d12e780	199	smp_message_recv(ipi);
0ebfff14	200
cebf589c AB	201	return IRQ_HANDLED;
cebf589c AB	202	}
a84195f3	203	static void iic_request_ipi(int ipi, const char *name)
cebf589c	204	{
2e194583	205	int virq;
a84195f3	206
2e194583 BH	207	virq = irq_create_mapping(iic_host, iic_ipi_to_irq(ipi));
	208	if (virq == NO_IRQ) {
	209	printk(KERN_ERR
	210	"iic: failed to map IPI %s\n", name);
	211	return;
0ebfff14	212	}
2e194583 BH	213	if (request_irq(virq, iic_ipi_action, IRQF_DISABLED, name,
	214	(void *)(long)ipi))
	215	printk(KERN_ERR
	216	"iic: failed to request IPI %s\n", name);
cebf589c AB	217	}
	218
	219	void iic_request_IPIs(void)
	220	{
a84195f3 AB	221	iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call");
a84195f3 AB	222	iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched");
b7d7a240	223	iic_request_ipi(PPC_MSG_CALL_FUNC_SINGLE, "IPI-call-single");
cebf589c	224	#ifdef CONFIG_DEBUGGER
a84195f3	225	iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
cebf589c AB	226	#endif /* CONFIG_DEBUGGER */
cebf589c AB	227	}
0ebfff14	228
cebf589c AB	229	#endif /* CONFIG_SMP */
cebf589c AB	230
0ebfff14 BH	231
	232	static int iic_host_match(struct irq_host h, struct device_node node)
	233	{
55b61fec	234	return of_device_is_compatible(node,
2e194583	235	"IBM,CBEA-Internal-Interrupt-Controller");
0ebfff14 BH	236	}
	237
	238	static int iic_host_map(struct irq_host *h, unsigned int virq,
6e99e458	239	irq_hw_number_t hw)
0ebfff14	240	{
2e194583 BH	241	switch (hw & IIC_IRQ_TYPE_MASK) {
2e194583 BH	242	case IIC_IRQ_TYPE_IPI:
0ebfff14	243	set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
2e194583 BH	244	break;
	245	case IIC_IRQ_TYPE_IOEXC:
	246	set_irq_chip_and_handler(virq, &iic_ioexc_chip,
5711fe90	247	handle_iic_irq);
2e194583 BH	248	break;
2e194583 BH	249	default:
f9ba4475	250	set_irq_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq);
2e194583	251	}
0ebfff14 BH	252	return 0;
	253	}
	254
	255	static int iic_host_xlate(struct irq_host h, struct device_node ct,
40d50cf7	256	const u32 *intspec, unsigned int intsize,
0ebfff14 BH	257	irq_hw_number_t out_hwirq, unsigned int out_flags)
0ebfff14 BH	258
cebf589c	259	{
2e194583 BH	260	unsigned int node, ext, unit, class;
	261	const u32 *val;
	262
55b61fec	263	if (!of_device_is_compatible(ct,
2e194583 BH	264	"IBM,CBEA-Internal-Interrupt-Controller"))
	265	return -ENODEV;
	266	if (intsize != 1)
	267	return -ENODEV;
e2eb6392	268	val = of_get_property(ct, "#interrupt-cells", NULL);
2e194583 BH	269	if (val == NULL \|\| *val != 1)
	270	return -ENODEV;
	271
	272	node = intspec[0] >> 24;
	273	ext = (intspec[0] >> 16) & 0xff;
	274	class = (intspec[0] >> 8) & 0xff;
	275	unit = intspec[0] & 0xff;
	276
	277	/* Check if node is in supported range */
	278	if (node > 1)
	279	return -EINVAL;
	280
	281	/* Build up interrupt number, special case for IO exceptions */
	282	*out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
	283	if (unit == IIC_UNIT_IIC && class == 1)
	284	*out_hwirq \|= IIC_IRQ_TYPE_IOEXC \| ext;
	285	else
	286	*out_hwirq \|= IIC_IRQ_TYPE_NORMAL \|
	287	(class << IIC_IRQ_CLASS_SHIFT) \| unit;
	288
	289	/* Dummy flags, ignored by iic code */
	290	*out_flags = IRQ_TYPE_EDGE_RISING;
	291
	292	return 0;
0ebfff14 BH	293	}
	294
	295	static struct irq_host_ops iic_host_ops = {
	296	.match = iic_host_match,
	297	.map = iic_host_map,
	298	.xlate = iic_host_xlate,
	299	};
	300
	301	static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
2e194583	302	struct device_node *node)
0ebfff14 BH	303	{
	304	/* XXX FIXME: should locate the linux CPU number from the HW cpu
	305	* number properly. We are lucky for now
	306	*/
6b7487fc	307	struct iic *iic = &per_cpu(cpu_iic, hw_cpu);
cebf589c	308
0ebfff14 BH	309	iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
0ebfff14 BH	310	BUG_ON(iic->regs == NULL);
b9e5b4e6	311
0ebfff14 BH	312	iic->target_id = ((hw_cpu & 2) << 3) \| ((hw_cpu & 1) ? 0xf : 0xe);
0ebfff14 BH	313	iic->eoi_stack[0] = 0xff;
2e194583	314	iic->node = of_node_get(node);
0ebfff14 BH	315	out_be64(&iic->regs->prio, 0);
0ebfff14 BH	316
2e194583 BH	317	printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n",
2e194583 BH	318	hw_cpu, iic->target_id, node->full_name);
0ebfff14 BH	319	}
	320
	321	static int __init setup_iic(void)
	322	{
	323	struct device_node *dn;
	324	struct resource r0, r1;
2e194583	325	unsigned int node, cascade, found = 0;
43b4f406	326	struct cbe_iic_regs __iomem *node_iic;
9e6ee340	327	const u32 *np;
0ebfff14 BH	328
	329	for (dn = NULL;
	330	(dn = of_find_node_by_name(dn,"interrupt-controller")) != NULL;) {
55b61fec	331	if (!of_device_is_compatible(dn,
0ebfff14 BH	332	"IBM,CBEA-Internal-Interrupt-Controller"))
0ebfff14 BH	333	continue;
e2eb6392	334	np = of_get_property(dn, "ibm,interrupt-server-ranges", NULL);
9e6ee340	335	if (np == NULL) {
0ebfff14 BH	336	printk(KERN_WARNING "IIC: CPU association not found\n");
	337	of_node_put(dn);
	338	return -ENODEV;
cebf589c	339	}
0ebfff14 BH	340	if (of_address_to_resource(dn, 0, &r0) \|\|
	341	of_address_to_resource(dn, 1, &r1)) {
	342	printk(KERN_WARNING "IIC: Can't resolve addresses\n");
	343	of_node_put(dn);
	344	return -ENODEV;
	345	}
2e194583 BH	346	found++;
	347	init_one_iic(np[0], r0.start, dn);
	348	init_one_iic(np[1], r1.start, dn);
	349
	350	/* Setup cascade for IO exceptions. XXX cleanup tricks to get
	351	* node vs CPU etc...
	352	* Note that we configure the IIC_IRR here with a hard coded
	353	* priority of 1. We might want to improve that later.
	354	*/
	355	node = np[0] >> 1;
	356	node_iic = cbe_get_cpu_iic_regs(np[0]);
	357	cascade = node << IIC_IRQ_NODE_SHIFT;
	358	cascade \|= 1 << IIC_IRQ_CLASS_SHIFT;
	359	cascade \|= IIC_UNIT_IIC;
	360	cascade = irq_create_mapping(iic_host, cascade);
	361	if (cascade == NO_IRQ)
	362	continue;
43b4f406 AB	363	/*
	364	* irq_data is a generic pointer that gets passed back
	365	* to us later, so the forced cast is fine.
	366	*/
	367	set_irq_data(cascade, (void __force *)node_iic);
2e194583 BH	368	set_irq_chained_handler(cascade , iic_ioexc_cascade);
	369	out_be64(&node_iic->iic_ir,
	370	(1 << 12) /* priority */ \|
	371	(node << 4) /* dest node */ \|
	372	IIC_UNIT_THREAD_0 /* route them to thread 0 */);
	373	/* Flush pending (make sure it triggers if there is
	374	* anything pending
	375	*/
	376	out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
cebf589c	377	}
0ebfff14 BH	378
	379	if (found)
	380	return 0;
	381	else
	382	return -ENODEV;
cebf589c AB	383	}
cebf589c AB	384
b9e5b4e6	385	void __init iic_init_IRQ(void)
cebf589c	386	{
2e194583	387	/* Setup an irq host data structure */
52964f87	388	iic_host = irq_alloc_host(NULL, IRQ_HOST_MAP_LINEAR, IIC_SOURCE_COUNT,
2e194583 BH	389	&iic_host_ops, IIC_IRQ_INVALID);
	390	BUG_ON(iic_host == NULL);
	391	irq_set_default_host(iic_host);
	392
0ebfff14	393	/* Discover and initialize iics */
d0e57c68	394	if (setup_iic() < 0)
0ebfff14	395	panic("IIC: Failed to initialize !\n");
d0e57c68	396
0ebfff14 BH	397	/* Set master interrupt handling function */
0ebfff14 BH	398	ppc_md.get_irq = iic_get_irq;
b9e5b4e6	399
0ebfff14 BH	400	/* Enable on current CPU */
0ebfff14 BH	401	iic_setup_cpu();
cebf589c	402	}
0443bbd3 KC	403
	404	void iic_set_interrupt_routing(int cpu, int thread, int priority)
	405	{
	406	struct cbe_iic_regs __iomem *iic_regs = cbe_get_cpu_iic_regs(cpu);
	407	u64 iic_ir = 0;
	408	int node = cpu >> 1;
	409
	410	/* Set which node and thread will handle the next interrupt */
	411	iic_ir \|= CBE_IIC_IR_PRIO(priority) \|
	412	CBE_IIC_IR_DEST_NODE(node);
	413	if (thread == 0)
	414	iic_ir \|= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0);
	415	else
	416	iic_ir \|= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1);
	417	out_be64(&iic_regs->iic_ir, iic_ir);
	418	}