[deliverable/linux.git] / arch / powerpc / platforms / cell / interrupt.c

/*
 * Cell Internal Interrupt Controller
 *
 * Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *                    IBM, Corp.
 *
 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
 *
 * Author: Arnd Bergmann <arndb@de.ibm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * TODO:
 * - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
 *   vs node numbers in the setup code
 * - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
 *   a non-active node to the active node)
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/percpu.h>
#include <linux/types.h>
#include <linux/ioport.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/prom.h>
#include <asm/ptrace.h>
#include <asm/machdep.h>
#include <asm/cell-regs.h>

#include "interrupt.h"

struct iic {
	struct cbe_iic_thread_regs __iomem *regs;
	u8 target_id;
	u8 eoi_stack[16];
	int eoi_ptr;
	struct device_node *node;
};

static DEFINE_PER_CPU(struct iic, iic);
#define IIC_NODE_COUNT	2
static struct irq_host *iic_host;

/* Convert between "pending" bits and hw irq number */
static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
{
	unsigned char unit = bits.source & 0xf;
	unsigned char node = bits.source >> 4;
	unsigned char class = bits.class & 3;

	/* Decode IPIs */
	if (bits.flags & CBE_IIC_IRQ_IPI)
		return IIC_IRQ_TYPE_IPI | (bits.prio >> 4);
	else
		return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit;
}

static void iic_mask(unsigned int irq)
{
}

static void iic_unmask(unsigned int irq)
{
}

static void iic_eoi(unsigned int irq)
{
	struct iic *iic = &__get_cpu_var(iic);
	out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
	BUG_ON(iic->eoi_ptr < 0);
}

static struct irq_chip iic_chip = {
	.typename = " CELL-IIC ",
	.mask = iic_mask,
	.unmask = iic_unmask,
	.eoi = iic_eoi,
};


static void iic_ioexc_eoi(unsigned int irq)
{
}

static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc)
{
	struct cbe_iic_regs __iomem *node_iic = (void __iomem *)desc->handler_data;
	unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
	unsigned long bits, ack;
	int cascade;

	for (;;) {
		bits = in_be64(&node_iic->iic_is);
		if (bits == 0)
			break;
		/* pre-ack edge interrupts */
		ack = bits & IIC_ISR_EDGE_MASK;
		if (ack)
			out_be64(&node_iic->iic_is, ack);
		/* handle them */
		for (cascade = 63; cascade >= 0; cascade--)
			if (bits & (0x8000000000000000UL >> cascade)) {
				unsigned int cirq =
					irq_linear_revmap(iic_host,
							  base | cascade);
				if (cirq != NO_IRQ)
					generic_handle_irq(cirq);
			}
		/* post-ack level interrupts */
		ack = bits & ~IIC_ISR_EDGE_MASK;
		if (ack)
			out_be64(&node_iic->iic_is, ack);
	}
	desc->chip->eoi(irq);
}


static struct irq_chip iic_ioexc_chip = {
	.typename = " CELL-IOEX",
	.mask = iic_mask,
	.unmask = iic_unmask,
	.eoi = iic_ioexc_eoi,
};

/* Get an IRQ number from the pending state register of the IIC */
static unsigned int iic_get_irq(void)
{
	struct cbe_iic_pending_bits pending;
	struct iic *iic;
	unsigned int virq;

	iic = &__get_cpu_var(iic);
	*(unsigned long *) &pending =
		in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
	if (!(pending.flags & CBE_IIC_IRQ_VALID))
		return NO_IRQ;
	virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
	if (virq == NO_IRQ)
		return NO_IRQ;
	iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
	BUG_ON(iic->eoi_ptr > 15);
	return virq;
}

#ifdef CONFIG_SMP

/* Use the highest interrupt priorities for IPI */
static inline int iic_ipi_to_irq(int ipi)
{
	return IIC_IRQ_TYPE_IPI + 0xf - ipi;
}

void iic_setup_cpu(void)
{
	out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
}

void iic_cause_IPI(int cpu, int mesg)
{
	out_be64(&per_cpu(iic, cpu).regs->generate, (0xf - mesg) << 4);
}

u8 iic_get_target_id(int cpu)
{
	return per_cpu(iic, cpu).target_id;
}
EXPORT_SYMBOL_GPL(iic_get_target_id);

struct irq_host *iic_get_irq_host(int node)
{
	return iic_host;
}
EXPORT_SYMBOL_GPL(iic_get_irq_host);


static irqreturn_t iic_ipi_action(int irq, void *dev_id)
{
	int ipi = (int)(long)dev_id;

	smp_message_recv(ipi);

	return IRQ_HANDLED;
}
static void iic_request_ipi(int ipi, const char *name)
{
	int virq;

	virq = irq_create_mapping(iic_host, iic_ipi_to_irq(ipi));
	if (virq == NO_IRQ) {
		printk(KERN_ERR
		       "iic: failed to map IPI %s\n", name);
		return;
	}
	if (request_irq(virq, iic_ipi_action, IRQF_DISABLED, name,
			(void *)(long)ipi))
		printk(KERN_ERR
		       "iic: failed to request IPI %s\n", name);
}

void iic_request_IPIs(void)
{
	iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call");
	iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched");
#ifdef CONFIG_DEBUGGER
	iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
#endif /* CONFIG_DEBUGGER */
}

#endif /* CONFIG_SMP */


static int iic_host_match(struct irq_host *h, struct device_node *node)
{
	return of_device_is_compatible(node,
				    "IBM,CBEA-Internal-Interrupt-Controller");
}

static int iic_host_map(struct irq_host *h, unsigned int virq,
			irq_hw_number_t hw)
{
	switch (hw & IIC_IRQ_TYPE_MASK) {
	case IIC_IRQ_TYPE_IPI:
		set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
		break;
	case IIC_IRQ_TYPE_IOEXC:
		set_irq_chip_and_handler(virq, &iic_ioexc_chip,
					 handle_fasteoi_irq);
		break;
	default:
		set_irq_chip_and_handler(virq, &iic_chip, handle_fasteoi_irq);
	}
	return 0;
}

static int iic_host_xlate(struct irq_host *h, struct device_node *ct,
			   u32 *intspec, unsigned int intsize,
			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)

{
	unsigned int node, ext, unit, class;
	const u32 *val;

	if (!of_device_is_compatible(ct,
				     "IBM,CBEA-Internal-Interrupt-Controller"))
		return -ENODEV;
	if (intsize != 1)
		return -ENODEV;
	val = of_get_property(ct, "#interrupt-cells", NULL);
	if (val == NULL || *val != 1)
		return -ENODEV;

	node = intspec[0] >> 24;
	ext = (intspec[0] >> 16) & 0xff;
	class = (intspec[0] >> 8) & 0xff;
	unit = intspec[0] & 0xff;

	/* Check if node is in supported range */
	if (node > 1)
		return -EINVAL;

	/* Build up interrupt number, special case for IO exceptions */
	*out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
	if (unit == IIC_UNIT_IIC && class == 1)
		*out_hwirq |= IIC_IRQ_TYPE_IOEXC | ext;
	else
		*out_hwirq |= IIC_IRQ_TYPE_NORMAL |
			(class << IIC_IRQ_CLASS_SHIFT) | unit;

	/* Dummy flags, ignored by iic code */
	*out_flags = IRQ_TYPE_EDGE_RISING;

	return 0;
}

static struct irq_host_ops iic_host_ops = {
	.match = iic_host_match,
	.map = iic_host_map,
	.xlate = iic_host_xlate,
};

static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
				struct device_node *node)
{
	/* XXX FIXME: should locate the linux CPU number from the HW cpu
	 * number properly. We are lucky for now
	 */
	struct iic *iic = &per_cpu(iic, hw_cpu);

	iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
	BUG_ON(iic->regs == NULL);

	iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe);
	iic->eoi_stack[0] = 0xff;
	iic->node = of_node_get(node);
	out_be64(&iic->regs->prio, 0);

	printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n",
	       hw_cpu, iic->target_id, node->full_name);
}

static int __init setup_iic(void)
{
	struct device_node *dn;
	struct resource r0, r1;
	unsigned int node, cascade, found = 0;
	struct cbe_iic_regs __iomem *node_iic;
	const u32 *np;

	for (dn = NULL;
	     (dn = of_find_node_by_name(dn,"interrupt-controller")) != NULL;) {
		if (!of_device_is_compatible(dn,
				     "IBM,CBEA-Internal-Interrupt-Controller"))
			continue;
		np = of_get_property(dn, "ibm,interrupt-server-ranges", NULL);
		if (np == NULL) {
			printk(KERN_WARNING "IIC: CPU association not found\n");
			of_node_put(dn);
			return -ENODEV;
		}
		if (of_address_to_resource(dn, 0, &r0) ||
		    of_address_to_resource(dn, 1, &r1)) {
			printk(KERN_WARNING "IIC: Can't resolve addresses\n");
			of_node_put(dn);
			return -ENODEV;
		}
		found++;
		init_one_iic(np[0], r0.start, dn);
		init_one_iic(np[1], r1.start, dn);

		/* Setup cascade for IO exceptions. XXX cleanup tricks to get
		 * node vs CPU etc...
		 * Note that we configure the IIC_IRR here with a hard coded
		 * priority of 1. We might want to improve that later.
		 */
		node = np[0] >> 1;
		node_iic = cbe_get_cpu_iic_regs(np[0]);
		cascade = node << IIC_IRQ_NODE_SHIFT;
		cascade |= 1 << IIC_IRQ_CLASS_SHIFT;
		cascade |= IIC_UNIT_IIC;
		cascade = irq_create_mapping(iic_host, cascade);
		if (cascade == NO_IRQ)
			continue;
		/*
		 * irq_data is a generic pointer that gets passed back
		 * to us later, so the forced cast is fine.
		 */
		set_irq_data(cascade, (void __force *)node_iic);
		set_irq_chained_handler(cascade , iic_ioexc_cascade);
		out_be64(&node_iic->iic_ir,
			 (1 << 12)		/* priority */ |
			 (node << 4)		/* dest node */ |
			 IIC_UNIT_THREAD_0	/* route them to thread 0 */);
		/* Flush pending (make sure it triggers if there is
		 * anything pending
		 */
		out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
	}

	if (found)
		return 0;
	else
		return -ENODEV;
}

void __init iic_init_IRQ(void)
{
	/* Setup an irq host data structure */
	iic_host = irq_alloc_host(NULL, IRQ_HOST_MAP_LINEAR, IIC_SOURCE_COUNT,
				  &iic_host_ops, IIC_IRQ_INVALID);
	BUG_ON(iic_host == NULL);
	irq_set_default_host(iic_host);

	/* Discover and initialize iics */
	if (setup_iic() < 0)
		panic("IIC: Failed to initialize !\n");

	/* Set master interrupt handling function */
	ppc_md.get_irq = iic_get_irq;

	/* Enable on current CPU */
	iic_setup_cpu();
}

void iic_set_interrupt_routing(int cpu, int thread, int priority)
{
	struct cbe_iic_regs __iomem *iic_regs = cbe_get_cpu_iic_regs(cpu);
	u64 iic_ir = 0;
	int node = cpu >> 1;

	/* Set which node and thread will handle the next interrupt */
	iic_ir |= CBE_IIC_IR_PRIO(priority) |
		  CBE_IIC_IR_DEST_NODE(node);
	if (thread == 0)
		iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0);
	else
		iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1);
	out_be64(&iic_regs->iic_ir, iic_ir);
}
Commit	Line	Data
cebf589c	1	/*
f3f66f59	2	* Cell Internal Interrupt Controller
cebf589c	3	*
0ebfff14 BH	4	* Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	5	* IBM, Corp.
	6	*
cebf589c AB	7	* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
	8	*
	9	* Author: Arnd Bergmann <arndb@de.ibm.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2, or (at your option)
	14	* any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
2e194583 BH	24	*
	25	* TODO:
	26	* - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
	27	* vs node numbers in the setup code
	28	* - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
	29	* a non-active node to the active node)
cebf589c AB	30	*/
cebf589c AB	31
cebf589c AB	32	#include <linux/interrupt.h>
cebf589c AB	33	#include <linux/irq.h>
2fb9d206	34	#include <linux/module.h>
cebf589c AB	35	#include <linux/percpu.h>
cebf589c AB	36	#include <linux/types.h>
0ebfff14	37	#include <linux/ioport.h>
cebf589c AB	38
	39	#include <asm/io.h>
	40	#include <asm/pgtable.h>
	41	#include <asm/prom.h>
	42	#include <asm/ptrace.h>
0ebfff14	43	#include <asm/machdep.h>
eef686a0	44	#include <asm/cell-regs.h>
cebf589c	45
f3f66f59	46	#include "interrupt.h"
cebf589c AB	47
cebf589c AB	48	struct iic {
acf7d768	49	struct cbe_iic_thread_regs __iomem *regs;
2fb9d206	50	u8 target_id;
b9e5b4e6 BH	51	u8 eoi_stack[16];
b9e5b4e6 BH	52	int eoi_ptr;
2e194583	53	struct device_node *node;
cebf589c AB	54	};
	55
	56	static DEFINE_PER_CPU(struct iic, iic);
0ebfff14	57	#define IIC_NODE_COUNT 2
2e194583	58	static struct irq_host *iic_host;
0ebfff14 BH	59
	60	/* Convert between "pending" bits and hw irq number */
	61	static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
	62	{
	63	unsigned char unit = bits.source & 0xf;
2e194583 BH	64	unsigned char node = bits.source >> 4;
2e194583 BH	65	unsigned char class = bits.class & 3;
0ebfff14	66
2e194583	67	/* Decode IPIs */
0ebfff14	68	if (bits.flags & CBE_IIC_IRQ_IPI)
2e194583	69	return IIC_IRQ_TYPE_IPI \| (bits.prio >> 4);
0ebfff14	70	else
2e194583	71	return (node << IIC_IRQ_NODE_SHIFT) \| (class << 4) \| unit;
0ebfff14	72	}
cebf589c	73
b9e5b4e6	74	static void iic_mask(unsigned int irq)
cebf589c	75	{
cebf589c AB	76	}
cebf589c AB	77
b9e5b4e6	78	static void iic_unmask(unsigned int irq)
cebf589c AB	79	{
	80	}
	81
b9e5b4e6	82	static void iic_eoi(unsigned int irq)
cebf589c	83	{
b9e5b4e6 BH	84	struct iic *iic = &__get_cpu_var(iic);
	85	out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
	86	BUG_ON(iic->eoi_ptr < 0);
cebf589c AB	87	}
cebf589c AB	88
b9e5b4e6	89	static struct irq_chip iic_chip = {
f3f66f59	90	.typename = " CELL-IIC ",
b9e5b4e6 BH	91	.mask = iic_mask,
	92	.unmask = iic_unmask,
	93	.eoi = iic_eoi,
cebf589c AB	94	};
cebf589c AB	95
2e194583 BH	96
	97	static void iic_ioexc_eoi(unsigned int irq)
	98	{
	99	}
	100
35a84c2f	101	static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc)
2e194583	102	{
43b4f406	103	struct cbe_iic_regs __iomem node_iic = (void __iomem )desc->handler_data;
2e194583 BH	104	unsigned int base = (irq & 0xffffff00) \| IIC_IRQ_TYPE_IOEXC;
	105	unsigned long bits, ack;
	106	int cascade;
	107
	108	for (;;) {
	109	bits = in_be64(&node_iic->iic_is);
	110	if (bits == 0)
	111	break;
	112	/* pre-ack edge interrupts */
	113	ack = bits & IIC_ISR_EDGE_MASK;
	114	if (ack)
	115	out_be64(&node_iic->iic_is, ack);
	116	/* handle them */
	117	for (cascade = 63; cascade >= 0; cascade--)
	118	if (bits & (0x8000000000000000UL >> cascade)) {
	119	unsigned int cirq =
	120	irq_linear_revmap(iic_host,
	121	base \| cascade);
	122	if (cirq != NO_IRQ)
49f19ce4	123	generic_handle_irq(cirq);
2e194583 BH	124	}
	125	/* post-ack level interrupts */
	126	ack = bits & ~IIC_ISR_EDGE_MASK;
	127	if (ack)
	128	out_be64(&node_iic->iic_is, ack);
	129	}
	130	desc->chip->eoi(irq);
	131	}
	132
	133
	134	static struct irq_chip iic_ioexc_chip = {
	135	.typename = " CELL-IOEX",
	136	.mask = iic_mask,
	137	.unmask = iic_unmask,
	138	.eoi = iic_ioexc_eoi,
	139	};
	140
cebf589c	141	/* Get an IRQ number from the pending state register of the IIC */
35a84c2f	142	static unsigned int iic_get_irq(void)
d0e57c68	143	{
9e6ee340 GL	144	struct cbe_iic_pending_bits pending;
9e6ee340 GL	145	struct iic *iic;
2e194583	146	unsigned int virq;
9e6ee340 GL	147
	148	iic = &__get_cpu_var(iic);
	149	(unsigned long ) &pending =
	150	in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
2e194583 BH	151	if (!(pending.flags & CBE_IIC_IRQ_VALID))
	152	return NO_IRQ;
	153	virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
	154	if (virq == NO_IRQ)
	155	return NO_IRQ;
9e6ee340 GL	156	iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
9e6ee340 GL	157	BUG_ON(iic->eoi_ptr > 15);
2e194583	158	return virq;
cebf589c AB	159	}
	160
	161	#ifdef CONFIG_SMP
a84195f3 AB	162
	163	/* Use the highest interrupt priorities for IPI */
	164	static inline int iic_ipi_to_irq(int ipi)
	165	{
2e194583	166	return IIC_IRQ_TYPE_IPI + 0xf - ipi;
a84195f3 AB	167	}
a84195f3 AB	168
cebf589c AB	169	void iic_setup_cpu(void)
	170	{
	171	out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
	172	}
	173
	174	void iic_cause_IPI(int cpu, int mesg)
	175	{
2e194583	176	out_be64(&per_cpu(iic, cpu).regs->generate, (0xf - mesg) << 4);
cebf589c AB	177	}
cebf589c AB	178
2fb9d206 AB	179	u8 iic_get_target_id(int cpu)
	180	{
	181	return per_cpu(iic, cpu).target_id;
	182	}
	183	EXPORT_SYMBOL_GPL(iic_get_target_id);
	184
0ebfff14 BH	185	struct irq_host *iic_get_irq_host(int node)
0ebfff14 BH	186	{
2e194583	187	return iic_host;
0ebfff14 BH	188	}
	189	EXPORT_SYMBOL_GPL(iic_get_irq_host);
	190
	191
7d12e780	192	static irqreturn_t iic_ipi_action(int irq, void *dev_id)
cebf589c	193	{
0ebfff14 BH	194	int ipi = (int)(long)dev_id;
0ebfff14 BH	195
7d12e780	196	smp_message_recv(ipi);
0ebfff14	197
cebf589c AB	198	return IRQ_HANDLED;
cebf589c AB	199	}
a84195f3	200	static void iic_request_ipi(int ipi, const char *name)
cebf589c	201	{
2e194583	202	int virq;
a84195f3	203
2e194583 BH	204	virq = irq_create_mapping(iic_host, iic_ipi_to_irq(ipi));
	205	if (virq == NO_IRQ) {
	206	printk(KERN_ERR
	207	"iic: failed to map IPI %s\n", name);
	208	return;
0ebfff14	209	}
2e194583 BH	210	if (request_irq(virq, iic_ipi_action, IRQF_DISABLED, name,
	211	(void *)(long)ipi))
	212	printk(KERN_ERR
	213	"iic: failed to request IPI %s\n", name);
cebf589c AB	214	}
	215
	216	void iic_request_IPIs(void)
	217	{
a84195f3 AB	218	iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call");
a84195f3 AB	219	iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched");
cebf589c	220	#ifdef CONFIG_DEBUGGER
a84195f3	221	iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
cebf589c AB	222	#endif /* CONFIG_DEBUGGER */
cebf589c AB	223	}
0ebfff14	224
cebf589c AB	225	#endif /* CONFIG_SMP */
cebf589c AB	226
0ebfff14 BH	227
	228	static int iic_host_match(struct irq_host h, struct device_node node)
	229	{
55b61fec	230	return of_device_is_compatible(node,
2e194583	231	"IBM,CBEA-Internal-Interrupt-Controller");
0ebfff14 BH	232	}
	233
	234	static int iic_host_map(struct irq_host *h, unsigned int virq,
6e99e458	235	irq_hw_number_t hw)
0ebfff14	236	{
2e194583 BH	237	switch (hw & IIC_IRQ_TYPE_MASK) {
2e194583 BH	238	case IIC_IRQ_TYPE_IPI:
0ebfff14	239	set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
2e194583 BH	240	break;
	241	case IIC_IRQ_TYPE_IOEXC:
	242	set_irq_chip_and_handler(virq, &iic_ioexc_chip,
	243	handle_fasteoi_irq);
	244	break;
	245	default:
	246	set_irq_chip_and_handler(virq, &iic_chip, handle_fasteoi_irq);
	247	}
0ebfff14 BH	248	return 0;
	249	}
	250
	251	static int iic_host_xlate(struct irq_host h, struct device_node ct,
	252	u32 *intspec, unsigned int intsize,
	253	irq_hw_number_t out_hwirq, unsigned int out_flags)
	254
cebf589c	255	{
2e194583 BH	256	unsigned int node, ext, unit, class;
	257	const u32 *val;
	258
55b61fec	259	if (!of_device_is_compatible(ct,
2e194583 BH	260	"IBM,CBEA-Internal-Interrupt-Controller"))
	261	return -ENODEV;
	262	if (intsize != 1)
	263	return -ENODEV;
e2eb6392	264	val = of_get_property(ct, "#interrupt-cells", NULL);
2e194583 BH	265	if (val == NULL \|\| *val != 1)
	266	return -ENODEV;
	267
	268	node = intspec[0] >> 24;
	269	ext = (intspec[0] >> 16) & 0xff;
	270	class = (intspec[0] >> 8) & 0xff;
	271	unit = intspec[0] & 0xff;
	272
	273	/* Check if node is in supported range */
	274	if (node > 1)
	275	return -EINVAL;
	276
	277	/* Build up interrupt number, special case for IO exceptions */
	278	*out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
	279	if (unit == IIC_UNIT_IIC && class == 1)
	280	*out_hwirq \|= IIC_IRQ_TYPE_IOEXC \| ext;
	281	else
	282	*out_hwirq \|= IIC_IRQ_TYPE_NORMAL \|
	283	(class << IIC_IRQ_CLASS_SHIFT) \| unit;
	284
	285	/* Dummy flags, ignored by iic code */
	286	*out_flags = IRQ_TYPE_EDGE_RISING;
	287
	288	return 0;
0ebfff14 BH	289	}
	290
	291	static struct irq_host_ops iic_host_ops = {
	292	.match = iic_host_match,
	293	.map = iic_host_map,
	294	.xlate = iic_host_xlate,
	295	};
	296
	297	static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
2e194583	298	struct device_node *node)
0ebfff14 BH	299	{
	300	/* XXX FIXME: should locate the linux CPU number from the HW cpu
	301	* number properly. We are lucky for now
	302	*/
	303	struct iic *iic = &per_cpu(iic, hw_cpu);
cebf589c	304
0ebfff14 BH	305	iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
0ebfff14 BH	306	BUG_ON(iic->regs == NULL);
b9e5b4e6	307
0ebfff14 BH	308	iic->target_id = ((hw_cpu & 2) << 3) \| ((hw_cpu & 1) ? 0xf : 0xe);
0ebfff14 BH	309	iic->eoi_stack[0] = 0xff;
2e194583	310	iic->node = of_node_get(node);
0ebfff14 BH	311	out_be64(&iic->regs->prio, 0);
0ebfff14 BH	312
2e194583 BH	313	printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n",
2e194583 BH	314	hw_cpu, iic->target_id, node->full_name);
0ebfff14 BH	315	}
	316
	317	static int __init setup_iic(void)
	318	{
	319	struct device_node *dn;
	320	struct resource r0, r1;
2e194583	321	unsigned int node, cascade, found = 0;
43b4f406	322	struct cbe_iic_regs __iomem *node_iic;
9e6ee340	323	const u32 *np;
0ebfff14 BH	324
	325	for (dn = NULL;
	326	(dn = of_find_node_by_name(dn,"interrupt-controller")) != NULL;) {
55b61fec	327	if (!of_device_is_compatible(dn,
0ebfff14 BH	328	"IBM,CBEA-Internal-Interrupt-Controller"))
0ebfff14 BH	329	continue;
e2eb6392	330	np = of_get_property(dn, "ibm,interrupt-server-ranges", NULL);
9e6ee340	331	if (np == NULL) {
0ebfff14 BH	332	printk(KERN_WARNING "IIC: CPU association not found\n");
	333	of_node_put(dn);
	334	return -ENODEV;
cebf589c	335	}
0ebfff14 BH	336	if (of_address_to_resource(dn, 0, &r0) \|\|
	337	of_address_to_resource(dn, 1, &r1)) {
	338	printk(KERN_WARNING "IIC: Can't resolve addresses\n");
	339	of_node_put(dn);
	340	return -ENODEV;
	341	}
2e194583 BH	342	found++;
	343	init_one_iic(np[0], r0.start, dn);
	344	init_one_iic(np[1], r1.start, dn);
	345
	346	/* Setup cascade for IO exceptions. XXX cleanup tricks to get
	347	* node vs CPU etc...
	348	* Note that we configure the IIC_IRR here with a hard coded
	349	* priority of 1. We might want to improve that later.
	350	*/
	351	node = np[0] >> 1;
	352	node_iic = cbe_get_cpu_iic_regs(np[0]);
	353	cascade = node << IIC_IRQ_NODE_SHIFT;
	354	cascade \|= 1 << IIC_IRQ_CLASS_SHIFT;
	355	cascade \|= IIC_UNIT_IIC;
	356	cascade = irq_create_mapping(iic_host, cascade);
	357	if (cascade == NO_IRQ)
	358	continue;
43b4f406 AB	359	/*
	360	* irq_data is a generic pointer that gets passed back
	361	* to us later, so the forced cast is fine.
	362	*/
	363	set_irq_data(cascade, (void __force *)node_iic);
2e194583 BH	364	set_irq_chained_handler(cascade , iic_ioexc_cascade);
	365	out_be64(&node_iic->iic_ir,
	366	(1 << 12) /* priority */ \|
	367	(node << 4) /* dest node */ \|
	368	IIC_UNIT_THREAD_0 /* route them to thread 0 */);
	369	/* Flush pending (make sure it triggers if there is
	370	* anything pending
	371	*/
	372	out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
cebf589c	373	}
0ebfff14 BH	374
	375	if (found)
	376	return 0;
	377	else
	378	return -ENODEV;
cebf589c AB	379	}
cebf589c AB	380
b9e5b4e6	381	void __init iic_init_IRQ(void)
cebf589c	382	{
2e194583	383	/* Setup an irq host data structure */
52964f87	384	iic_host = irq_alloc_host(NULL, IRQ_HOST_MAP_LINEAR, IIC_SOURCE_COUNT,
2e194583 BH	385	&iic_host_ops, IIC_IRQ_INVALID);
	386	BUG_ON(iic_host == NULL);
	387	irq_set_default_host(iic_host);
	388
0ebfff14	389	/* Discover and initialize iics */
d0e57c68	390	if (setup_iic() < 0)
0ebfff14	391	panic("IIC: Failed to initialize !\n");
d0e57c68	392
0ebfff14 BH	393	/* Set master interrupt handling function */
0ebfff14 BH	394	ppc_md.get_irq = iic_get_irq;
b9e5b4e6	395
0ebfff14 BH	396	/* Enable on current CPU */
0ebfff14 BH	397	iic_setup_cpu();
cebf589c	398	}
0443bbd3 KC	399
	400	void iic_set_interrupt_routing(int cpu, int thread, int priority)
	401	{
	402	struct cbe_iic_regs __iomem *iic_regs = cbe_get_cpu_iic_regs(cpu);
	403	u64 iic_ir = 0;
	404	int node = cpu >> 1;
	405
	406	/* Set which node and thread will handle the next interrupt */
	407	iic_ir \|= CBE_IIC_IR_PRIO(priority) \|
	408	CBE_IIC_IR_DEST_NODE(node);
	409	if (thread == 0)
	410	iic_ir \|= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0);
	411	else
	412	iic_ir \|= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1);
	413	out_be64(&iic_regs->iic_ir, iic_ir);
	414	}