[deliverable/linux.git] / arch / powerpc / platforms / cell / interrupt.c

/*
 * Cell Internal Interrupt Controller
 *
 * Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *                    IBM, Corp.
 *
 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
 *
 * Author: Arnd Bergmann <arndb@de.ibm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * TODO:
 * - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
 *   vs node numbers in the setup code
 * - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
 *   a non-active node to the active node)
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/export.h>
#include <linux/percpu.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <linux/kernel_stat.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/prom.h>
#include <asm/ptrace.h>
#include <asm/machdep.h>
#include <asm/cell-regs.h>

#include "interrupt.h"

struct iic {
	struct cbe_iic_thread_regs __iomem *regs;
	u8 target_id;
	u8 eoi_stack[16];
	int eoi_ptr;
	struct device_node *node;
};

static DEFINE_PER_CPU(struct iic, cpu_iic);
#define IIC_NODE_COUNT	2
static struct irq_domain *iic_host;

/* Convert between "pending" bits and hw irq number */
static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
{
	unsigned char unit = bits.source & 0xf;
	unsigned char node = bits.source >> 4;
	unsigned char class = bits.class & 3;

	/* Decode IPIs */
	if (bits.flags & CBE_IIC_IRQ_IPI)
		return IIC_IRQ_TYPE_IPI | (bits.prio >> 4);
	else
		return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit;
}

static void iic_mask(struct irq_data *d)
{
}

static void iic_unmask(struct irq_data *d)
{
}

static void iic_eoi(struct irq_data *d)
{
	struct iic *iic = this_cpu_ptr(&cpu_iic);
	out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
	BUG_ON(iic->eoi_ptr < 0);
}

static struct irq_chip iic_chip = {
	.name = "CELL-IIC",
	.irq_mask = iic_mask,
	.irq_unmask = iic_unmask,
	.irq_eoi = iic_eoi,
};


static void iic_ioexc_eoi(struct irq_data *d)
{
}

static void iic_ioexc_cascade(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct cbe_iic_regs __iomem *node_iic =
		(void __iomem *)irq_desc_get_handler_data(desc);
	unsigned int irq = irq_desc_get_irq(desc);
	unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
	unsigned long bits, ack;
	int cascade;

	for (;;) {
		bits = in_be64(&node_iic->iic_is);
		if (bits == 0)
			break;
		/* pre-ack edge interrupts */
		ack = bits & IIC_ISR_EDGE_MASK;
		if (ack)
			out_be64(&node_iic->iic_is, ack);
		/* handle them */
		for (cascade = 63; cascade >= 0; cascade--)
			if (bits & (0x8000000000000000UL >> cascade)) {
				unsigned int cirq =
					irq_linear_revmap(iic_host,
							  base | cascade);
				if (cirq != NO_IRQ)
					generic_handle_irq(cirq);
			}
		/* post-ack level interrupts */
		ack = bits & ~IIC_ISR_EDGE_MASK;
		if (ack)
			out_be64(&node_iic->iic_is, ack);
	}
	chip->irq_eoi(&desc->irq_data);
}


static struct irq_chip iic_ioexc_chip = {
	.name = "CELL-IOEX",
	.irq_mask = iic_mask,
	.irq_unmask = iic_unmask,
	.irq_eoi = iic_ioexc_eoi,
};

/* Get an IRQ number from the pending state register of the IIC */
static unsigned int iic_get_irq(void)
{
	struct cbe_iic_pending_bits pending;
	struct iic *iic;
	unsigned int virq;

	iic = this_cpu_ptr(&cpu_iic);
	*(unsigned long *) &pending =
		in_be64((u64 __iomem *) &iic->regs->pending_destr);
	if (!(pending.flags & CBE_IIC_IRQ_VALID))
		return NO_IRQ;
	virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
	if (virq == NO_IRQ)
		return NO_IRQ;
	iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
	BUG_ON(iic->eoi_ptr > 15);
	return virq;
}

void iic_setup_cpu(void)
{
	out_be64(&this_cpu_ptr(&cpu_iic)->regs->prio, 0xff);
}

u8 iic_get_target_id(int cpu)
{
	return per_cpu(cpu_iic, cpu).target_id;
}

EXPORT_SYMBOL_GPL(iic_get_target_id);

#ifdef CONFIG_SMP

/* Use the highest interrupt priorities for IPI */
static inline int iic_msg_to_irq(int msg)
{
	return IIC_IRQ_TYPE_IPI + 0xf - msg;
}

void iic_message_pass(int cpu, int msg)
{
	out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - msg) << 4);
}

struct irq_domain *iic_get_irq_host(int node)
{
	return iic_host;
}
EXPORT_SYMBOL_GPL(iic_get_irq_host);

static void iic_request_ipi(int msg)
{
	int virq;

	virq = irq_create_mapping(iic_host, iic_msg_to_irq(msg));
	if (virq == NO_IRQ) {
		printk(KERN_ERR
		       "iic: failed to map IPI %s\n", smp_ipi_name[msg]);
		return;
	}

	/*
	 * If smp_request_message_ipi encounters an error it will notify
	 * the error.  If a message is not needed it will return non-zero.
	 */
	if (smp_request_message_ipi(virq, msg))
		irq_dispose_mapping(virq);
}

void iic_request_IPIs(void)
{
	iic_request_ipi(PPC_MSG_CALL_FUNCTION);
	iic_request_ipi(PPC_MSG_RESCHEDULE);
	iic_request_ipi(PPC_MSG_TICK_BROADCAST);
	iic_request_ipi(PPC_MSG_DEBUGGER_BREAK);
}

#endif /* CONFIG_SMP */


static int iic_host_match(struct irq_domain *h, struct device_node *node,
			  enum irq_domain_bus_token bus_token)
{
	return of_device_is_compatible(node,
				    "IBM,CBEA-Internal-Interrupt-Controller");
}

static int iic_host_map(struct irq_domain *h, unsigned int virq,
			irq_hw_number_t hw)
{
	switch (hw & IIC_IRQ_TYPE_MASK) {
	case IIC_IRQ_TYPE_IPI:
		irq_set_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
		break;
	case IIC_IRQ_TYPE_IOEXC:
		irq_set_chip_and_handler(virq, &iic_ioexc_chip,
					 handle_edge_eoi_irq);
		break;
	default:
		irq_set_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq);
	}
	return 0;
}

static int iic_host_xlate(struct irq_domain *h, struct device_node *ct,
			   const u32 *intspec, unsigned int intsize,
			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)

{
	unsigned int node, ext, unit, class;
	const u32 *val;

	if (!of_device_is_compatible(ct,
				     "IBM,CBEA-Internal-Interrupt-Controller"))
		return -ENODEV;
	if (intsize != 1)
		return -ENODEV;
	val = of_get_property(ct, "#interrupt-cells", NULL);
	if (val == NULL || *val != 1)
		return -ENODEV;

	node = intspec[0] >> 24;
	ext = (intspec[0] >> 16) & 0xff;
	class = (intspec[0] >> 8) & 0xff;
	unit = intspec[0] & 0xff;

	/* Check if node is in supported range */
	if (node > 1)
		return -EINVAL;

	/* Build up interrupt number, special case for IO exceptions */
	*out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
	if (unit == IIC_UNIT_IIC && class == 1)
		*out_hwirq |= IIC_IRQ_TYPE_IOEXC | ext;
	else
		*out_hwirq |= IIC_IRQ_TYPE_NORMAL |
			(class << IIC_IRQ_CLASS_SHIFT) | unit;

	/* Dummy flags, ignored by iic code */
	*out_flags = IRQ_TYPE_EDGE_RISING;

	return 0;
}

static const struct irq_domain_ops iic_host_ops = {
	.match = iic_host_match,
	.map = iic_host_map,
	.xlate = iic_host_xlate,
};

static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
				struct device_node *node)
{
	/* XXX FIXME: should locate the linux CPU number from the HW cpu
	 * number properly. We are lucky for now
	 */
	struct iic *iic = &per_cpu(cpu_iic, hw_cpu);

	iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
	BUG_ON(iic->regs == NULL);

	iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe);
	iic->eoi_stack[0] = 0xff;
	iic->node = of_node_get(node);
	out_be64(&iic->regs->prio, 0);

	printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n",
	       hw_cpu, iic->target_id, node->full_name);
}

static int __init setup_iic(void)
{
	struct device_node *dn;
	struct resource r0, r1;
	unsigned int node, cascade, found = 0;
	struct cbe_iic_regs __iomem *node_iic;
	const u32 *np;

	for (dn = NULL;
	     (dn = of_find_node_by_name(dn,"interrupt-controller")) != NULL;) {
		if (!of_device_is_compatible(dn,
				     "IBM,CBEA-Internal-Interrupt-Controller"))
			continue;
		np = of_get_property(dn, "ibm,interrupt-server-ranges", NULL);
		if (np == NULL) {
			printk(KERN_WARNING "IIC: CPU association not found\n");
			of_node_put(dn);
			return -ENODEV;
		}
		if (of_address_to_resource(dn, 0, &r0) ||
		    of_address_to_resource(dn, 1, &r1)) {
			printk(KERN_WARNING "IIC: Can't resolve addresses\n");
			of_node_put(dn);
			return -ENODEV;
		}
		found++;
		init_one_iic(np[0], r0.start, dn);
		init_one_iic(np[1], r1.start, dn);

		/* Setup cascade for IO exceptions. XXX cleanup tricks to get
		 * node vs CPU etc...
		 * Note that we configure the IIC_IRR here with a hard coded
		 * priority of 1. We might want to improve that later.
		 */
		node = np[0] >> 1;
		node_iic = cbe_get_cpu_iic_regs(np[0]);
		cascade = node << IIC_IRQ_NODE_SHIFT;
		cascade |= 1 << IIC_IRQ_CLASS_SHIFT;
		cascade |= IIC_UNIT_IIC;
		cascade = irq_create_mapping(iic_host, cascade);
		if (cascade == NO_IRQ)
			continue;
		/*
		 * irq_data is a generic pointer that gets passed back
		 * to us later, so the forced cast is fine.
		 */
		irq_set_handler_data(cascade, (void __force *)node_iic);
		irq_set_chained_handler(cascade, iic_ioexc_cascade);
		out_be64(&node_iic->iic_ir,
			 (1 << 12)		/* priority */ |
			 (node << 4)		/* dest node */ |
			 IIC_UNIT_THREAD_0	/* route them to thread 0 */);
		/* Flush pending (make sure it triggers if there is
		 * anything pending
		 */
		out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
	}

	if (found)
		return 0;
	else
		return -ENODEV;
}

void __init iic_init_IRQ(void)
{
	/* Setup an irq host data structure */
	iic_host = irq_domain_add_linear(NULL, IIC_SOURCE_COUNT, &iic_host_ops,
					 NULL);
	BUG_ON(iic_host == NULL);
	irq_set_default_host(iic_host);

	/* Discover and initialize iics */
	if (setup_iic() < 0)
		panic("IIC: Failed to initialize !\n");

	/* Set master interrupt handling function */
	ppc_md.get_irq = iic_get_irq;

	/* Enable on current CPU */
	iic_setup_cpu();
}

void iic_set_interrupt_routing(int cpu, int thread, int priority)
{
	struct cbe_iic_regs __iomem *iic_regs = cbe_get_cpu_iic_regs(cpu);
	u64 iic_ir = 0;
	int node = cpu >> 1;

	/* Set which node and thread will handle the next interrupt */
	iic_ir |= CBE_IIC_IR_PRIO(priority) |
		  CBE_IIC_IR_DEST_NODE(node);
	if (thread == 0)
		iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0);
	else
		iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1);
	out_be64(&iic_regs->iic_ir, iic_ir);
}
Commit	Line	Data
cebf589c	1	/*
f3f66f59	2	* Cell Internal Interrupt Controller
cebf589c	3	*
0ebfff14 BH	4	* Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	5	* IBM, Corp.
	6	*
cebf589c AB	7	* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
	8	*
	9	* Author: Arnd Bergmann <arndb@de.ibm.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2, or (at your option)
	14	* any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
2e194583 BH	24	*
	25	* TODO:
	26	* - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
	27	* vs node numbers in the setup code
	28	* - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
	29	* a non-active node to the active node)
cebf589c AB	30	*/
cebf589c AB	31
cebf589c AB	32	#include <linux/interrupt.h>
cebf589c AB	33	#include <linux/irq.h>
4b16f8e2	34	#include <linux/export.h>
cebf589c AB	35	#include <linux/percpu.h>
cebf589c AB	36	#include <linux/types.h>
0ebfff14	37	#include <linux/ioport.h>
5711fe90	38	#include <linux/kernel_stat.h>
cebf589c AB	39
	40	#include <asm/io.h>
	41	#include <asm/pgtable.h>
	42	#include <asm/prom.h>
	43	#include <asm/ptrace.h>
0ebfff14	44	#include <asm/machdep.h>
eef686a0	45	#include <asm/cell-regs.h>
cebf589c	46
f3f66f59	47	#include "interrupt.h"
cebf589c AB	48
cebf589c AB	49	struct iic {
acf7d768	50	struct cbe_iic_thread_regs __iomem *regs;
2fb9d206	51	u8 target_id;
b9e5b4e6 BH	52	u8 eoi_stack[16];
b9e5b4e6 BH	53	int eoi_ptr;
2e194583	54	struct device_node *node;
cebf589c AB	55	};
cebf589c AB	56
6b7487fc	57	static DEFINE_PER_CPU(struct iic, cpu_iic);
0ebfff14	58	#define IIC_NODE_COUNT 2
bae1d8f1	59	static struct irq_domain *iic_host;
0ebfff14 BH	60
	61	/* Convert between "pending" bits and hw irq number */
	62	static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
	63	{
	64	unsigned char unit = bits.source & 0xf;
2e194583 BH	65	unsigned char node = bits.source >> 4;
2e194583 BH	66	unsigned char class = bits.class & 3;
0ebfff14	67
2e194583	68	/* Decode IPIs */
0ebfff14	69	if (bits.flags & CBE_IIC_IRQ_IPI)
2e194583	70	return IIC_IRQ_TYPE_IPI \| (bits.prio >> 4);
0ebfff14	71	else
2e194583	72	return (node << IIC_IRQ_NODE_SHIFT) \| (class << 4) \| unit;
0ebfff14	73	}
cebf589c	74
d1ae63d4	75	static void iic_mask(struct irq_data *d)
cebf589c	76	{
cebf589c AB	77	}
cebf589c AB	78
d1ae63d4	79	static void iic_unmask(struct irq_data *d)
cebf589c AB	80	{
	81	}
	82
d1ae63d4	83	static void iic_eoi(struct irq_data *d)
cebf589c	84	{
69111bac	85	struct iic *iic = this_cpu_ptr(&cpu_iic);
b9e5b4e6 BH	86	out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
b9e5b4e6 BH	87	BUG_ON(iic->eoi_ptr < 0);
cebf589c AB	88	}
cebf589c AB	89
b9e5b4e6	90	static struct irq_chip iic_chip = {
fc380c0c	91	.name = "CELL-IIC",
d1ae63d4 LB	92	.irq_mask = iic_mask,
	93	.irq_unmask = iic_unmask,
	94	.irq_eoi = iic_eoi,
cebf589c AB	95	};
cebf589c AB	96
2e194583	97
d1ae63d4	98	static void iic_ioexc_eoi(struct irq_data *d)
2e194583 BH	99	{
	100	}
	101
bd0b9ac4	102	static void iic_ioexc_cascade(struct irq_desc *desc)
2e194583	103	{
ec775d0e	104	struct irq_chip *chip = irq_desc_get_chip(desc);
d1ae63d4	105	struct cbe_iic_regs __iomem *node_iic =
ec775d0e	106	(void __iomem *)irq_desc_get_handler_data(desc);
391de7f9	107	unsigned int irq = irq_desc_get_irq(desc);
2e194583 BH	108	unsigned int base = (irq & 0xffffff00) \| IIC_IRQ_TYPE_IOEXC;
	109	unsigned long bits, ack;
	110	int cascade;
	111
	112	for (;;) {
	113	bits = in_be64(&node_iic->iic_is);
	114	if (bits == 0)
	115	break;
	116	/* pre-ack edge interrupts */
	117	ack = bits & IIC_ISR_EDGE_MASK;
	118	if (ack)
	119	out_be64(&node_iic->iic_is, ack);
	120	/* handle them */
	121	for (cascade = 63; cascade >= 0; cascade--)
	122	if (bits & (0x8000000000000000UL >> cascade)) {
	123	unsigned int cirq =
	124	irq_linear_revmap(iic_host,
	125	base \| cascade);
	126	if (cirq != NO_IRQ)
49f19ce4	127	generic_handle_irq(cirq);
2e194583 BH	128	}
	129	/* post-ack level interrupts */
	130	ack = bits & ~IIC_ISR_EDGE_MASK;
	131	if (ack)
	132	out_be64(&node_iic->iic_is, ack);
	133	}
d1ae63d4	134	chip->irq_eoi(&desc->irq_data);
2e194583 BH	135	}
	136
	137
	138	static struct irq_chip iic_ioexc_chip = {
fc380c0c	139	.name = "CELL-IOEX",
d1ae63d4 LB	140	.irq_mask = iic_mask,
	141	.irq_unmask = iic_unmask,
	142	.irq_eoi = iic_ioexc_eoi,
2e194583 BH	143	};
2e194583 BH	144
cebf589c	145	/* Get an IRQ number from the pending state register of the IIC */
35a84c2f	146	static unsigned int iic_get_irq(void)
d0e57c68	147	{
9e6ee340 GL	148	struct cbe_iic_pending_bits pending;
9e6ee340 GL	149	struct iic *iic;
2e194583	150	unsigned int virq;
9e6ee340	151
69111bac	152	iic = this_cpu_ptr(&cpu_iic);
9e6ee340	153	(unsigned long ) &pending =
b36ac9e8	154	in_be64((u64 __iomem *) &iic->regs->pending_destr);
2e194583 BH	155	if (!(pending.flags & CBE_IIC_IRQ_VALID))
	156	return NO_IRQ;
	157	virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
	158	if (virq == NO_IRQ)
	159	return NO_IRQ;
9e6ee340 GL	160	iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
9e6ee340 GL	161	BUG_ON(iic->eoi_ptr > 15);
2e194583	162	return virq;
cebf589c AB	163	}
cebf589c AB	164
4bfac368 OJ	165	void iic_setup_cpu(void)
4bfac368 OJ	166	{
b0dd00ad	167	out_be64(&this_cpu_ptr(&cpu_iic)->regs->prio, 0xff);
4bfac368 OJ	168	}
	169
	170	u8 iic_get_target_id(int cpu)
	171	{
6b7487fc	172	return per_cpu(cpu_iic, cpu).target_id;
4bfac368 OJ	173	}
	174
	175	EXPORT_SYMBOL_GPL(iic_get_target_id);
	176
cebf589c	177	#ifdef CONFIG_SMP
a84195f3 AB	178
a84195f3 AB	179	/* Use the highest interrupt priorities for IPI */
d5a1c193	180	static inline int iic_msg_to_irq(int msg)
a84195f3	181	{
d5a1c193	182	return IIC_IRQ_TYPE_IPI + 0xf - msg;
a84195f3 AB	183	}
a84195f3 AB	184
d5a1c193	185	void iic_message_pass(int cpu, int msg)
cebf589c	186	{
d5a1c193	187	out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - msg) << 4);
cebf589c AB	188	}
cebf589c AB	189
bae1d8f1	190	struct irq_domain *iic_get_irq_host(int node)
0ebfff14	191	{
2e194583	192	return iic_host;
0ebfff14 BH	193	}
	194	EXPORT_SYMBOL_GPL(iic_get_irq_host);
	195
d5a1c193	196	static void iic_request_ipi(int msg)
cebf589c	197	{
2e194583	198	int virq;
a84195f3	199
d5a1c193	200	virq = irq_create_mapping(iic_host, iic_msg_to_irq(msg));
2e194583 BH	201	if (virq == NO_IRQ) {
2e194583 BH	202	printk(KERN_ERR
d5a1c193	203	"iic: failed to map IPI %s\n", smp_ipi_name[msg]);
2e194583	204	return;
0ebfff14	205	}
7ef71d75 MM	206
	207	/*
	208	* If smp_request_message_ipi encounters an error it will notify
	209	* the error. If a message is not needed it will return non-zero.
	210	*/
d5a1c193	211	if (smp_request_message_ipi(virq, msg))
7ef71d75	212	irq_dispose_mapping(virq);
cebf589c AB	213	}
	214
	215	void iic_request_IPIs(void)
	216	{
7ef71d75 MM	217	iic_request_ipi(PPC_MSG_CALL_FUNCTION);
7ef71d75 MM	218	iic_request_ipi(PPC_MSG_RESCHEDULE);
1b67bee1	219	iic_request_ipi(PPC_MSG_TICK_BROADCAST);
7ef71d75	220	iic_request_ipi(PPC_MSG_DEBUGGER_BREAK);
cebf589c	221	}
0ebfff14	222
cebf589c AB	223	#endif /* CONFIG_SMP */
cebf589c AB	224
0ebfff14	225
ad3aedfb MZ	226	static int iic_host_match(struct irq_domain h, struct device_node node,
ad3aedfb MZ	227	enum irq_domain_bus_token bus_token)
0ebfff14	228	{
55b61fec	229	return of_device_is_compatible(node,
2e194583	230	"IBM,CBEA-Internal-Interrupt-Controller");
0ebfff14 BH	231	}
0ebfff14 BH	232
bae1d8f1	233	static int iic_host_map(struct irq_domain *h, unsigned int virq,
6e99e458	234	irq_hw_number_t hw)
0ebfff14	235	{
2e194583 BH	236	switch (hw & IIC_IRQ_TYPE_MASK) {
2e194583 BH	237	case IIC_IRQ_TYPE_IPI:
ec775d0e	238	irq_set_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
2e194583 BH	239	break;
2e194583 BH	240	case IIC_IRQ_TYPE_IOEXC:
ec775d0e	241	irq_set_chip_and_handler(virq, &iic_ioexc_chip,
e122996a	242	handle_edge_eoi_irq);
2e194583 BH	243	break;
2e194583 BH	244	default:
ec775d0e	245	irq_set_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq);
2e194583	246	}
0ebfff14 BH	247	return 0;
	248	}
	249
bae1d8f1	250	static int iic_host_xlate(struct irq_domain h, struct device_node ct,
40d50cf7	251	const u32 *intspec, unsigned int intsize,
0ebfff14 BH	252	irq_hw_number_t out_hwirq, unsigned int out_flags)
0ebfff14 BH	253
cebf589c	254	{
2e194583 BH	255	unsigned int node, ext, unit, class;
	256	const u32 *val;
	257
55b61fec	258	if (!of_device_is_compatible(ct,
2e194583 BH	259	"IBM,CBEA-Internal-Interrupt-Controller"))
	260	return -ENODEV;
	261	if (intsize != 1)
	262	return -ENODEV;
e2eb6392	263	val = of_get_property(ct, "#interrupt-cells", NULL);
2e194583 BH	264	if (val == NULL \|\| *val != 1)
	265	return -ENODEV;
	266
	267	node = intspec[0] >> 24;
	268	ext = (intspec[0] >> 16) & 0xff;
	269	class = (intspec[0] >> 8) & 0xff;
	270	unit = intspec[0] & 0xff;
	271
	272	/* Check if node is in supported range */
	273	if (node > 1)
	274	return -EINVAL;
	275
	276	/* Build up interrupt number, special case for IO exceptions */
	277	*out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
	278	if (unit == IIC_UNIT_IIC && class == 1)
	279	*out_hwirq \|= IIC_IRQ_TYPE_IOEXC \| ext;
	280	else
	281	*out_hwirq \|= IIC_IRQ_TYPE_NORMAL \|
	282	(class << IIC_IRQ_CLASS_SHIFT) \| unit;
	283
	284	/* Dummy flags, ignored by iic code */
	285	*out_flags = IRQ_TYPE_EDGE_RISING;
	286
	287	return 0;
0ebfff14 BH	288	}
0ebfff14 BH	289
9f70b8eb	290	static const struct irq_domain_ops iic_host_ops = {
0ebfff14 BH	291	.match = iic_host_match,
	292	.map = iic_host_map,
	293	.xlate = iic_host_xlate,
	294	};
	295
	296	static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
2e194583	297	struct device_node *node)
0ebfff14 BH	298	{
	299	/* XXX FIXME: should locate the linux CPU number from the HW cpu
	300	* number properly. We are lucky for now
	301	*/
6b7487fc	302	struct iic *iic = &per_cpu(cpu_iic, hw_cpu);
cebf589c	303
0ebfff14 BH	304	iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
0ebfff14 BH	305	BUG_ON(iic->regs == NULL);
b9e5b4e6	306
0ebfff14 BH	307	iic->target_id = ((hw_cpu & 2) << 3) \| ((hw_cpu & 1) ? 0xf : 0xe);
0ebfff14 BH	308	iic->eoi_stack[0] = 0xff;
2e194583	309	iic->node = of_node_get(node);
0ebfff14 BH	310	out_be64(&iic->regs->prio, 0);
0ebfff14 BH	311
2e194583 BH	312	printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n",
2e194583 BH	313	hw_cpu, iic->target_id, node->full_name);
0ebfff14 BH	314	}
	315
	316	static int __init setup_iic(void)
	317	{
	318	struct device_node *dn;
	319	struct resource r0, r1;
2e194583	320	unsigned int node, cascade, found = 0;
43b4f406	321	struct cbe_iic_regs __iomem *node_iic;
9e6ee340	322	const u32 *np;
0ebfff14 BH	323
	324	for (dn = NULL;
	325	(dn = of_find_node_by_name(dn,"interrupt-controller")) != NULL;) {
55b61fec	326	if (!of_device_is_compatible(dn,
0ebfff14 BH	327	"IBM,CBEA-Internal-Interrupt-Controller"))
0ebfff14 BH	328	continue;
e2eb6392	329	np = of_get_property(dn, "ibm,interrupt-server-ranges", NULL);
9e6ee340	330	if (np == NULL) {
0ebfff14 BH	331	printk(KERN_WARNING "IIC: CPU association not found\n");
	332	of_node_put(dn);
	333	return -ENODEV;
cebf589c	334	}
0ebfff14 BH	335	if (of_address_to_resource(dn, 0, &r0) \|\|
	336	of_address_to_resource(dn, 1, &r1)) {
	337	printk(KERN_WARNING "IIC: Can't resolve addresses\n");
	338	of_node_put(dn);
	339	return -ENODEV;
	340	}
2e194583 BH	341	found++;
	342	init_one_iic(np[0], r0.start, dn);
	343	init_one_iic(np[1], r1.start, dn);
	344
	345	/* Setup cascade for IO exceptions. XXX cleanup tricks to get
	346	* node vs CPU etc...
	347	* Note that we configure the IIC_IRR here with a hard coded
	348	* priority of 1. We might want to improve that later.
	349	*/
	350	node = np[0] >> 1;
	351	node_iic = cbe_get_cpu_iic_regs(np[0]);
	352	cascade = node << IIC_IRQ_NODE_SHIFT;
	353	cascade \|= 1 << IIC_IRQ_CLASS_SHIFT;
	354	cascade \|= IIC_UNIT_IIC;
	355	cascade = irq_create_mapping(iic_host, cascade);
	356	if (cascade == NO_IRQ)
	357	continue;
43b4f406 AB	358	/*
	359	* irq_data is a generic pointer that gets passed back
	360	* to us later, so the forced cast is fine.
	361	*/
ec775d0e TG	362	irq_set_handler_data(cascade, (void __force *)node_iic);
ec775d0e TG	363	irq_set_chained_handler(cascade, iic_ioexc_cascade);
2e194583 BH	364	out_be64(&node_iic->iic_ir,
	365	(1 << 12) /* priority */ \|
	366	(node << 4) /* dest node */ \|
	367	IIC_UNIT_THREAD_0 /* route them to thread 0 */);
	368	/* Flush pending (make sure it triggers if there is
	369	* anything pending
	370	*/
	371	out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
cebf589c	372	}
0ebfff14 BH	373
	374	if (found)
	375	return 0;
	376	else
	377	return -ENODEV;
cebf589c AB	378	}
cebf589c AB	379
b9e5b4e6	380	void __init iic_init_IRQ(void)
cebf589c	381	{
2e194583	382	/* Setup an irq host data structure */
a8db8cf0 GL	383	iic_host = irq_domain_add_linear(NULL, IIC_SOURCE_COUNT, &iic_host_ops,
a8db8cf0 GL	384	NULL);
2e194583 BH	385	BUG_ON(iic_host == NULL);
	386	irq_set_default_host(iic_host);
	387
0ebfff14	388	/* Discover and initialize iics */
d0e57c68	389	if (setup_iic() < 0)
0ebfff14	390	panic("IIC: Failed to initialize !\n");
d0e57c68	391
0ebfff14 BH	392	/* Set master interrupt handling function */
0ebfff14 BH	393	ppc_md.get_irq = iic_get_irq;
b9e5b4e6	394
0ebfff14 BH	395	/* Enable on current CPU */
0ebfff14 BH	396	iic_setup_cpu();
cebf589c	397	}
0443bbd3 KC	398
	399	void iic_set_interrupt_routing(int cpu, int thread, int priority)
	400	{
	401	struct cbe_iic_regs __iomem *iic_regs = cbe_get_cpu_iic_regs(cpu);
	402	u64 iic_ir = 0;
	403	int node = cpu >> 1;
	404
	405	/* Set which node and thread will handle the next interrupt */
	406	iic_ir \|= CBE_IIC_IR_PRIO(priority) \|
	407	CBE_IIC_IR_DEST_NODE(node);
	408	if (thread == 0)
	409	iic_ir \|= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0);
	410	else
	411	iic_ir \|= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1);
	412	out_be64(&iic_regs->iic_ir, iic_ir);
	413	}