[deliverable/linux.git] / arch / powerpc / platforms / cell / interrupt.c

/*
 * Cell Internal Interrupt Controller
 *
 * Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *                    IBM, Corp.
 *
 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
 *
 * Author: Arnd Bergmann <arndb@de.ibm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * TODO:
 * - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
 *   vs node numbers in the setup code
 * - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
 *   a non-active node to the active node)
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/percpu.h>
#include <linux/types.h>
#include <linux/ioport.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/prom.h>
#include <asm/ptrace.h>
#include <asm/machdep.h>

#include "interrupt.h"
#include "cbe_regs.h"

struct iic {
	struct cbe_iic_thread_regs __iomem *regs;
	u8 target_id;
	u8 eoi_stack[16];
	int eoi_ptr;
	struct device_node *node;
};

static DEFINE_PER_CPU(struct iic, iic);
#define IIC_NODE_COUNT	2
static struct irq_host *iic_host;

/* Convert between "pending" bits and hw irq number */
static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
{
	unsigned char unit = bits.source & 0xf;
	unsigned char node = bits.source >> 4;
	unsigned char class = bits.class & 3;

	/* Decode IPIs */
	if (bits.flags & CBE_IIC_IRQ_IPI)
		return IIC_IRQ_TYPE_IPI | (bits.prio >> 4);
	else
		return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit;
}

static void iic_mask(unsigned int irq)
{
}

static void iic_unmask(unsigned int irq)
{
}

static void iic_eoi(unsigned int irq)
{
	struct iic *iic = &__get_cpu_var(iic);
	out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
	BUG_ON(iic->eoi_ptr < 0);
}

static struct irq_chip iic_chip = {
	.typename = " CELL-IIC ",
	.mask = iic_mask,
	.unmask = iic_unmask,
	.eoi = iic_eoi,
};


static void iic_ioexc_eoi(unsigned int irq)
{
}

static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc,
			    struct pt_regs *regs)
{
	struct cbe_iic_regs *node_iic = desc->handler_data;
	unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
	unsigned long bits, ack;
	int cascade;

	for (;;) {
		bits = in_be64(&node_iic->iic_is);
		if (bits == 0)
			break;
		/* pre-ack edge interrupts */
		ack = bits & IIC_ISR_EDGE_MASK;
		if (ack)
			out_be64(&node_iic->iic_is, ack);
		/* handle them */
		for (cascade = 63; cascade >= 0; cascade--)
			if (bits & (0x8000000000000000UL >> cascade)) {
				unsigned int cirq =
					irq_linear_revmap(iic_host,
							  base | cascade);
				if (cirq != NO_IRQ)
					generic_handle_irq(cirq, regs);
			}
		/* post-ack level interrupts */
		ack = bits & ~IIC_ISR_EDGE_MASK;
		if (ack)
			out_be64(&node_iic->iic_is, ack);
	}
	desc->chip->eoi(irq);
}


static struct irq_chip iic_ioexc_chip = {
	.typename = " CELL-IOEX",
	.mask = iic_mask,
	.unmask = iic_unmask,
	.eoi = iic_ioexc_eoi,
};

/* Get an IRQ number from the pending state register of the IIC */
static unsigned int iic_get_irq(struct pt_regs *regs)
{
	struct cbe_iic_pending_bits pending;
	struct iic *iic;
	unsigned int virq;

	iic = &__get_cpu_var(iic);
	*(unsigned long *) &pending =
		in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
	if (!(pending.flags & CBE_IIC_IRQ_VALID))
		return NO_IRQ;
	virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
	if (virq == NO_IRQ)
		return NO_IRQ;
	iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
	BUG_ON(iic->eoi_ptr > 15);
	return virq;
}

#ifdef CONFIG_SMP

/* Use the highest interrupt priorities for IPI */
static inline int iic_ipi_to_irq(int ipi)
{
	return IIC_IRQ_TYPE_IPI + 0xf - ipi;
}

void iic_setup_cpu(void)
{
	out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
}

void iic_cause_IPI(int cpu, int mesg)
{
	out_be64(&per_cpu(iic, cpu).regs->generate, (0xf - mesg) << 4);
}

u8 iic_get_target_id(int cpu)
{
	return per_cpu(iic, cpu).target_id;
}
EXPORT_SYMBOL_GPL(iic_get_target_id);

struct irq_host *iic_get_irq_host(int node)
{
	return iic_host;
}
EXPORT_SYMBOL_GPL(iic_get_irq_host);


static irqreturn_t iic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
{
	int ipi = (int)(long)dev_id;

	smp_message_recv(ipi, regs);

	return IRQ_HANDLED;
}
static void iic_request_ipi(int ipi, const char *name)
{
	int virq;

	virq = irq_create_mapping(iic_host, iic_ipi_to_irq(ipi));
	if (virq == NO_IRQ) {
		printk(KERN_ERR
		       "iic: failed to map IPI %s\n", name);
		return;
	}
	if (request_irq(virq, iic_ipi_action, IRQF_DISABLED, name,
			(void *)(long)ipi))
		printk(KERN_ERR
		       "iic: failed to request IPI %s\n", name);
}

void iic_request_IPIs(void)
{
	iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call");
	iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched");
#ifdef CONFIG_DEBUGGER
	iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
#endif /* CONFIG_DEBUGGER */
}

#endif /* CONFIG_SMP */


static int iic_host_match(struct irq_host *h, struct device_node *node)
{
	return device_is_compatible(node,
				    "IBM,CBEA-Internal-Interrupt-Controller");
}

static int iic_host_map(struct irq_host *h, unsigned int virq,
			irq_hw_number_t hw)
{
	switch (hw & IIC_IRQ_TYPE_MASK) {
	case IIC_IRQ_TYPE_IPI:
		set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
		break;
	case IIC_IRQ_TYPE_IOEXC:
		set_irq_chip_and_handler(virq, &iic_ioexc_chip,
					 handle_fasteoi_irq);
		break;
	default:
		set_irq_chip_and_handler(virq, &iic_chip, handle_fasteoi_irq);
	}
	return 0;
}

static int iic_host_xlate(struct irq_host *h, struct device_node *ct,
			   u32 *intspec, unsigned int intsize,
			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)

{
	unsigned int node, ext, unit, class;
	const u32 *val;

	if (!device_is_compatible(ct,
				     "IBM,CBEA-Internal-Interrupt-Controller"))
		return -ENODEV;
	if (intsize != 1)
		return -ENODEV;
	val = get_property(ct, "#interrupt-cells", NULL);
	if (val == NULL || *val != 1)
		return -ENODEV;

	node = intspec[0] >> 24;
	ext = (intspec[0] >> 16) & 0xff;
	class = (intspec[0] >> 8) & 0xff;
	unit = intspec[0] & 0xff;

	/* Check if node is in supported range */
	if (node > 1)
		return -EINVAL;

	/* Build up interrupt number, special case for IO exceptions */
	*out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
	if (unit == IIC_UNIT_IIC && class == 1)
		*out_hwirq |= IIC_IRQ_TYPE_IOEXC | ext;
	else
		*out_hwirq |= IIC_IRQ_TYPE_NORMAL |
			(class << IIC_IRQ_CLASS_SHIFT) | unit;

	/* Dummy flags, ignored by iic code */
	*out_flags = IRQ_TYPE_EDGE_RISING;

	return 0;
}

static struct irq_host_ops iic_host_ops = {
	.match = iic_host_match,
	.map = iic_host_map,
	.xlate = iic_host_xlate,
};

static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
				struct device_node *node)
{
	/* XXX FIXME: should locate the linux CPU number from the HW cpu
	 * number properly. We are lucky for now
	 */
	struct iic *iic = &per_cpu(iic, hw_cpu);

	iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
	BUG_ON(iic->regs == NULL);

	iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe);
	iic->eoi_stack[0] = 0xff;
	iic->node = of_node_get(node);
	out_be64(&iic->regs->prio, 0);

	printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n",
	       hw_cpu, iic->target_id, node->full_name);
}

static int __init setup_iic(void)
{
	struct device_node *dn;
	struct resource r0, r1;
	unsigned int node, cascade, found = 0;
	struct cbe_iic_regs *node_iic;
	const u32 *np;

	for (dn = NULL;
	     (dn = of_find_node_by_name(dn,"interrupt-controller")) != NULL;) {
		if (!device_is_compatible(dn,
				     "IBM,CBEA-Internal-Interrupt-Controller"))
			continue;
		np = get_property(dn, "ibm,interrupt-server-ranges", NULL);
		if (np == NULL) {
			printk(KERN_WARNING "IIC: CPU association not found\n");
			of_node_put(dn);
			return -ENODEV;
		}
		if (of_address_to_resource(dn, 0, &r0) ||
		    of_address_to_resource(dn, 1, &r1)) {
			printk(KERN_WARNING "IIC: Can't resolve addresses\n");
			of_node_put(dn);
			return -ENODEV;
		}
		found++;
		init_one_iic(np[0], r0.start, dn);
		init_one_iic(np[1], r1.start, dn);

		/* Setup cascade for IO exceptions. XXX cleanup tricks to get
		 * node vs CPU etc...
		 * Note that we configure the IIC_IRR here with a hard coded
		 * priority of 1. We might want to improve that later.
		 */
		node = np[0] >> 1;
		node_iic = cbe_get_cpu_iic_regs(np[0]);
		cascade = node << IIC_IRQ_NODE_SHIFT;
		cascade |= 1 << IIC_IRQ_CLASS_SHIFT;
		cascade |= IIC_UNIT_IIC;
		cascade = irq_create_mapping(iic_host, cascade);
		if (cascade == NO_IRQ)
			continue;
		set_irq_data(cascade, node_iic);
		set_irq_chained_handler(cascade , iic_ioexc_cascade);
		out_be64(&node_iic->iic_ir,
			 (1 << 12)		/* priority */ |
			 (node << 4)		/* dest node */ |
			 IIC_UNIT_THREAD_0	/* route them to thread 0 */);
		/* Flush pending (make sure it triggers if there is
		 * anything pending
		 */
		out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
	}

	if (found)
		return 0;
	else
		return -ENODEV;
}

void __init iic_init_IRQ(void)
{
	/* Setup an irq host data structure */
	iic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, IIC_SOURCE_COUNT,
				  &iic_host_ops, IIC_IRQ_INVALID);
	BUG_ON(iic_host == NULL);
	irq_set_default_host(iic_host);

	/* Discover and initialize iics */
	if (setup_iic() < 0)
		panic("IIC: Failed to initialize !\n");

	/* Set master interrupt handling function */
	ppc_md.get_irq = iic_get_irq;

	/* Enable on current CPU */
	iic_setup_cpu();
}
Commit	Line	Data
cebf589c	1	/*
f3f66f59	2	* Cell Internal Interrupt Controller
cebf589c	3	*
0ebfff14 BH	4	* Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	5	* IBM, Corp.
	6	*
cebf589c AB	7	* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
	8	*
	9	* Author: Arnd Bergmann <arndb@de.ibm.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2, or (at your option)
	14	* any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
2e194583 BH	24	*
	25	* TODO:
	26	* - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
	27	* vs node numbers in the setup code
	28	* - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
	29	* a non-active node to the active node)
cebf589c AB	30	*/
cebf589c AB	31
cebf589c AB	32	#include <linux/interrupt.h>
cebf589c AB	33	#include <linux/irq.h>
2fb9d206	34	#include <linux/module.h>
cebf589c AB	35	#include <linux/percpu.h>
cebf589c AB	36	#include <linux/types.h>
0ebfff14	37	#include <linux/ioport.h>
cebf589c AB	38
	39	#include <asm/io.h>
	40	#include <asm/pgtable.h>
	41	#include <asm/prom.h>
	42	#include <asm/ptrace.h>
0ebfff14	43	#include <asm/machdep.h>
cebf589c	44
f3f66f59	45	#include "interrupt.h"
acf7d768	46	#include "cbe_regs.h"
cebf589c AB	47
cebf589c AB	48	struct iic {
acf7d768	49	struct cbe_iic_thread_regs __iomem *regs;
2fb9d206	50	u8 target_id;
b9e5b4e6 BH	51	u8 eoi_stack[16];
b9e5b4e6 BH	52	int eoi_ptr;
2e194583	53	struct device_node *node;
cebf589c AB	54	};
	55
	56	static DEFINE_PER_CPU(struct iic, iic);
0ebfff14	57	#define IIC_NODE_COUNT 2
2e194583	58	static struct irq_host *iic_host;
0ebfff14 BH	59
	60	/* Convert between "pending" bits and hw irq number */
	61	static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
	62	{
	63	unsigned char unit = bits.source & 0xf;
2e194583 BH	64	unsigned char node = bits.source >> 4;
2e194583 BH	65	unsigned char class = bits.class & 3;
0ebfff14	66
2e194583	67	/* Decode IPIs */
0ebfff14	68	if (bits.flags & CBE_IIC_IRQ_IPI)
2e194583	69	return IIC_IRQ_TYPE_IPI \| (bits.prio >> 4);
0ebfff14	70	else
2e194583	71	return (node << IIC_IRQ_NODE_SHIFT) \| (class << 4) \| unit;
0ebfff14	72	}
cebf589c	73
b9e5b4e6	74	static void iic_mask(unsigned int irq)
cebf589c	75	{
cebf589c AB	76	}
cebf589c AB	77
b9e5b4e6	78	static void iic_unmask(unsigned int irq)
cebf589c AB	79	{
	80	}
	81
b9e5b4e6	82	static void iic_eoi(unsigned int irq)
cebf589c	83	{
b9e5b4e6 BH	84	struct iic *iic = &__get_cpu_var(iic);
	85	out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
	86	BUG_ON(iic->eoi_ptr < 0);
cebf589c AB	87	}
cebf589c AB	88
b9e5b4e6	89	static struct irq_chip iic_chip = {
f3f66f59	90	.typename = " CELL-IIC ",
b9e5b4e6 BH	91	.mask = iic_mask,
	92	.unmask = iic_unmask,
	93	.eoi = iic_eoi,
cebf589c AB	94	};
cebf589c AB	95
2e194583 BH	96
	97	static void iic_ioexc_eoi(unsigned int irq)
	98	{
	99	}
	100
	101	static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc,
	102	struct pt_regs *regs)
	103	{
	104	struct cbe_iic_regs *node_iic = desc->handler_data;
	105	unsigned int base = (irq & 0xffffff00) \| IIC_IRQ_TYPE_IOEXC;
	106	unsigned long bits, ack;
	107	int cascade;
	108
	109	for (;;) {
	110	bits = in_be64(&node_iic->iic_is);
	111	if (bits == 0)
	112	break;
	113	/* pre-ack edge interrupts */
	114	ack = bits & IIC_ISR_EDGE_MASK;
	115	if (ack)
	116	out_be64(&node_iic->iic_is, ack);
	117	/* handle them */
	118	for (cascade = 63; cascade >= 0; cascade--)
	119	if (bits & (0x8000000000000000UL >> cascade)) {
	120	unsigned int cirq =
	121	irq_linear_revmap(iic_host,
	122	base \| cascade);
	123	if (cirq != NO_IRQ)
	124	generic_handle_irq(cirq, regs);
	125	}
	126	/* post-ack level interrupts */
	127	ack = bits & ~IIC_ISR_EDGE_MASK;
	128	if (ack)
	129	out_be64(&node_iic->iic_is, ack);
	130	}
	131	desc->chip->eoi(irq);
	132	}
	133
	134
	135	static struct irq_chip iic_ioexc_chip = {
	136	.typename = " CELL-IOEX",
	137	.mask = iic_mask,
	138	.unmask = iic_unmask,
	139	.eoi = iic_ioexc_eoi,
	140	};
	141
cebf589c	142	/* Get an IRQ number from the pending state register of the IIC */
0ebfff14	143	static unsigned int iic_get_irq(struct pt_regs *regs)
d0e57c68	144	{
9e6ee340 GL	145	struct cbe_iic_pending_bits pending;
9e6ee340 GL	146	struct iic *iic;
2e194583	147	unsigned int virq;
9e6ee340 GL	148
	149	iic = &__get_cpu_var(iic);
	150	(unsigned long ) &pending =
	151	in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
2e194583 BH	152	if (!(pending.flags & CBE_IIC_IRQ_VALID))
	153	return NO_IRQ;
	154	virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
	155	if (virq == NO_IRQ)
	156	return NO_IRQ;
9e6ee340 GL	157	iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
9e6ee340 GL	158	BUG_ON(iic->eoi_ptr > 15);
2e194583	159	return virq;
cebf589c AB	160	}
	161
	162	#ifdef CONFIG_SMP
a84195f3 AB	163
	164	/* Use the highest interrupt priorities for IPI */
	165	static inline int iic_ipi_to_irq(int ipi)
	166	{
2e194583	167	return IIC_IRQ_TYPE_IPI + 0xf - ipi;
a84195f3 AB	168	}
a84195f3 AB	169
cebf589c AB	170	void iic_setup_cpu(void)
	171	{
	172	out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
	173	}
	174
	175	void iic_cause_IPI(int cpu, int mesg)
	176	{
2e194583	177	out_be64(&per_cpu(iic, cpu).regs->generate, (0xf - mesg) << 4);
cebf589c AB	178	}
cebf589c AB	179
2fb9d206 AB	180	u8 iic_get_target_id(int cpu)
	181	{
	182	return per_cpu(iic, cpu).target_id;
	183	}
	184	EXPORT_SYMBOL_GPL(iic_get_target_id);
	185
0ebfff14 BH	186	struct irq_host *iic_get_irq_host(int node)
0ebfff14 BH	187	{
2e194583	188	return iic_host;
0ebfff14 BH	189	}
	190	EXPORT_SYMBOL_GPL(iic_get_irq_host);
	191
	192
cebf589c AB	193	static irqreturn_t iic_ipi_action(int irq, void dev_id, struct pt_regs regs)
cebf589c AB	194	{
0ebfff14 BH	195	int ipi = (int)(long)dev_id;
	196
	197	smp_message_recv(ipi, regs);
	198
cebf589c AB	199	return IRQ_HANDLED;
cebf589c AB	200	}
a84195f3	201	static void iic_request_ipi(int ipi, const char *name)
cebf589c	202	{
2e194583	203	int virq;
a84195f3	204
2e194583 BH	205	virq = irq_create_mapping(iic_host, iic_ipi_to_irq(ipi));
	206	if (virq == NO_IRQ) {
	207	printk(KERN_ERR
	208	"iic: failed to map IPI %s\n", name);
	209	return;
0ebfff14	210	}
2e194583 BH	211	if (request_irq(virq, iic_ipi_action, IRQF_DISABLED, name,
	212	(void *)(long)ipi))
	213	printk(KERN_ERR
	214	"iic: failed to request IPI %s\n", name);
cebf589c AB	215	}
	216
	217	void iic_request_IPIs(void)
	218	{
a84195f3 AB	219	iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call");
a84195f3 AB	220	iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched");
cebf589c	221	#ifdef CONFIG_DEBUGGER
a84195f3	222	iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
cebf589c AB	223	#endif /* CONFIG_DEBUGGER */
cebf589c AB	224	}
0ebfff14	225
cebf589c AB	226	#endif /* CONFIG_SMP */
cebf589c AB	227
0ebfff14 BH	228
	229	static int iic_host_match(struct irq_host h, struct device_node node)
	230	{
2e194583 BH	231	return device_is_compatible(node,
2e194583 BH	232	"IBM,CBEA-Internal-Interrupt-Controller");
0ebfff14 BH	233	}
	234
	235	static int iic_host_map(struct irq_host *h, unsigned int virq,
6e99e458	236	irq_hw_number_t hw)
0ebfff14	237	{
2e194583 BH	238	switch (hw & IIC_IRQ_TYPE_MASK) {
2e194583 BH	239	case IIC_IRQ_TYPE_IPI:
0ebfff14	240	set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
2e194583 BH	241	break;
	242	case IIC_IRQ_TYPE_IOEXC:
	243	set_irq_chip_and_handler(virq, &iic_ioexc_chip,
	244	handle_fasteoi_irq);
	245	break;
	246	default:
	247	set_irq_chip_and_handler(virq, &iic_chip, handle_fasteoi_irq);
	248	}
0ebfff14 BH	249	return 0;
	250	}
	251
	252	static int iic_host_xlate(struct irq_host h, struct device_node ct,
	253	u32 *intspec, unsigned int intsize,
	254	irq_hw_number_t out_hwirq, unsigned int out_flags)
	255
cebf589c	256	{
2e194583 BH	257	unsigned int node, ext, unit, class;
	258	const u32 *val;
	259
	260	if (!device_is_compatible(ct,
	261	"IBM,CBEA-Internal-Interrupt-Controller"))
	262	return -ENODEV;
	263	if (intsize != 1)
	264	return -ENODEV;
	265	val = get_property(ct, "#interrupt-cells", NULL);
	266	if (val == NULL \|\| *val != 1)
	267	return -ENODEV;
	268
	269	node = intspec[0] >> 24;
	270	ext = (intspec[0] >> 16) & 0xff;
	271	class = (intspec[0] >> 8) & 0xff;
	272	unit = intspec[0] & 0xff;
	273
	274	/* Check if node is in supported range */
	275	if (node > 1)
	276	return -EINVAL;
	277
	278	/* Build up interrupt number, special case for IO exceptions */
	279	*out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
	280	if (unit == IIC_UNIT_IIC && class == 1)
	281	*out_hwirq \|= IIC_IRQ_TYPE_IOEXC \| ext;
	282	else
	283	*out_hwirq \|= IIC_IRQ_TYPE_NORMAL \|
	284	(class << IIC_IRQ_CLASS_SHIFT) \| unit;
	285
	286	/* Dummy flags, ignored by iic code */
	287	*out_flags = IRQ_TYPE_EDGE_RISING;
	288
	289	return 0;
0ebfff14 BH	290	}
	291
	292	static struct irq_host_ops iic_host_ops = {
	293	.match = iic_host_match,
	294	.map = iic_host_map,
	295	.xlate = iic_host_xlate,
	296	};
	297
	298	static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
2e194583	299	struct device_node *node)
0ebfff14 BH	300	{
	301	/* XXX FIXME: should locate the linux CPU number from the HW cpu
	302	* number properly. We are lucky for now
	303	*/
	304	struct iic *iic = &per_cpu(iic, hw_cpu);
cebf589c	305
0ebfff14 BH	306	iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
0ebfff14 BH	307	BUG_ON(iic->regs == NULL);
b9e5b4e6	308
0ebfff14 BH	309	iic->target_id = ((hw_cpu & 2) << 3) \| ((hw_cpu & 1) ? 0xf : 0xe);
0ebfff14 BH	310	iic->eoi_stack[0] = 0xff;
2e194583	311	iic->node = of_node_get(node);
0ebfff14 BH	312	out_be64(&iic->regs->prio, 0);
0ebfff14 BH	313
2e194583 BH	314	printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n",
2e194583 BH	315	hw_cpu, iic->target_id, node->full_name);
0ebfff14 BH	316	}
	317
	318	static int __init setup_iic(void)
	319	{
	320	struct device_node *dn;
	321	struct resource r0, r1;
2e194583 BH	322	unsigned int node, cascade, found = 0;
2e194583 BH	323	struct cbe_iic_regs *node_iic;
9e6ee340	324	const u32 *np;
0ebfff14 BH	325
	326	for (dn = NULL;
	327	(dn = of_find_node_by_name(dn,"interrupt-controller")) != NULL;) {
	328	if (!device_is_compatible(dn,
	329	"IBM,CBEA-Internal-Interrupt-Controller"))
	330	continue;
c61c27d5	331	np = get_property(dn, "ibm,interrupt-server-ranges", NULL);
9e6ee340	332	if (np == NULL) {
0ebfff14 BH	333	printk(KERN_WARNING "IIC: CPU association not found\n");
	334	of_node_put(dn);
	335	return -ENODEV;
cebf589c	336	}
0ebfff14 BH	337	if (of_address_to_resource(dn, 0, &r0) \|\|
	338	of_address_to_resource(dn, 1, &r1)) {
	339	printk(KERN_WARNING "IIC: Can't resolve addresses\n");
	340	of_node_put(dn);
	341	return -ENODEV;
	342	}
2e194583 BH	343	found++;
	344	init_one_iic(np[0], r0.start, dn);
	345	init_one_iic(np[1], r1.start, dn);
	346
	347	/* Setup cascade for IO exceptions. XXX cleanup tricks to get
	348	* node vs CPU etc...
	349	* Note that we configure the IIC_IRR here with a hard coded
	350	* priority of 1. We might want to improve that later.
	351	*/
	352	node = np[0] >> 1;
	353	node_iic = cbe_get_cpu_iic_regs(np[0]);
	354	cascade = node << IIC_IRQ_NODE_SHIFT;
	355	cascade \|= 1 << IIC_IRQ_CLASS_SHIFT;
	356	cascade \|= IIC_UNIT_IIC;
	357	cascade = irq_create_mapping(iic_host, cascade);
	358	if (cascade == NO_IRQ)
	359	continue;
	360	set_irq_data(cascade, node_iic);
	361	set_irq_chained_handler(cascade , iic_ioexc_cascade);
	362	out_be64(&node_iic->iic_ir,
	363	(1 << 12) /* priority */ \|
	364	(node << 4) /* dest node */ \|
	365	IIC_UNIT_THREAD_0 /* route them to thread 0 */);
	366	/* Flush pending (make sure it triggers if there is
	367	* anything pending
	368	*/
	369	out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
cebf589c	370	}
0ebfff14 BH	371
	372	if (found)
	373	return 0;
	374	else
	375	return -ENODEV;
cebf589c AB	376	}
cebf589c AB	377
b9e5b4e6	378	void __init iic_init_IRQ(void)
cebf589c	379	{
2e194583 BH	380	/* Setup an irq host data structure */
	381	iic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, IIC_SOURCE_COUNT,
	382	&iic_host_ops, IIC_IRQ_INVALID);
	383	BUG_ON(iic_host == NULL);
	384	irq_set_default_host(iic_host);
	385
0ebfff14	386	/* Discover and initialize iics */
d0e57c68	387	if (setup_iic() < 0)
0ebfff14	388	panic("IIC: Failed to initialize !\n");
d0e57c68	389
0ebfff14 BH	390	/* Set master interrupt handling function */
0ebfff14 BH	391	ppc_md.get_irq = iic_get_irq;
b9e5b4e6	392
0ebfff14 BH	393	/* Enable on current CPU */
0ebfff14 BH	394	iic_setup_cpu();
cebf589c	395	}