Commit | Line | Data |
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ae209cf1 | 1 | /* |
f3f66f59 | 2 | * IOMMU implementation for Cell Broadband Processor Architecture |
ae209cf1 | 3 | * |
99e13912 | 4 | * (C) Copyright IBM Corporation 2006-2008 |
ae209cf1 | 5 | * |
165785e5 | 6 | * Author: Jeremy Kerr <jk@ozlabs.org> |
ae209cf1 | 7 | * |
165785e5 JK |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
ae209cf1 AB |
21 | */ |
22 | ||
23 | #undef DEBUG | |
24 | ||
25 | #include <linux/kernel.h> | |
ae209cf1 | 26 | #include <linux/init.h> |
165785e5 JK |
27 | #include <linux/interrupt.h> |
28 | #include <linux/notifier.h> | |
ccd05d08 | 29 | #include <linux/of.h> |
d8caf74f | 30 | #include <linux/of_platform.h> |
ae209cf1 | 31 | |
ae209cf1 | 32 | #include <asm/prom.h> |
165785e5 | 33 | #include <asm/iommu.h> |
ae209cf1 | 34 | #include <asm/machdep.h> |
165785e5 | 35 | #include <asm/pci-bridge.h> |
49d65b3a | 36 | #include <asm/udbg.h> |
165785e5 | 37 | #include <asm/lmb.h> |
9858ee8a | 38 | #include <asm/firmware.h> |
eef686a0 | 39 | #include <asm/cell-regs.h> |
ae209cf1 | 40 | |
165785e5 | 41 | #include "interrupt.h" |
ae209cf1 | 42 | |
165785e5 JK |
43 | /* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages |
44 | * instead of leaving them mapped to some dummy page. This can be | |
45 | * enabled once the appropriate workarounds for spider bugs have | |
46 | * been enabled | |
47 | */ | |
48 | #define CELL_IOMMU_REAL_UNMAP | |
49 | ||
50 | /* Define CELL_IOMMU_STRICT_PROTECTION to enforce protection of | |
51 | * IO PTEs based on the transfer direction. That can be enabled | |
52 | * once spider-net has been fixed to pass the correct direction | |
53 | * to the DMA mapping functions | |
54 | */ | |
55 | #define CELL_IOMMU_STRICT_PROTECTION | |
56 | ||
57 | ||
58 | #define NR_IOMMUS 2 | |
59 | ||
60 | /* IOC mmap registers */ | |
61 | #define IOC_Reg_Size 0x2000 | |
62 | ||
63 | #define IOC_IOPT_CacheInvd 0x908 | |
64 | #define IOC_IOPT_CacheInvd_NE_Mask 0xffe0000000000000ul | |
65 | #define IOC_IOPT_CacheInvd_IOPTE_Mask 0x000003fffffffff8ul | |
66 | #define IOC_IOPT_CacheInvd_Busy 0x0000000000000001ul | |
67 | ||
68 | #define IOC_IOST_Origin 0x918 | |
69 | #define IOC_IOST_Origin_E 0x8000000000000000ul | |
70 | #define IOC_IOST_Origin_HW 0x0000000000000800ul | |
71 | #define IOC_IOST_Origin_HL 0x0000000000000400ul | |
72 | ||
73 | #define IOC_IO_ExcpStat 0x920 | |
74 | #define IOC_IO_ExcpStat_V 0x8000000000000000ul | |
75 | #define IOC_IO_ExcpStat_SPF_Mask 0x6000000000000000ul | |
76 | #define IOC_IO_ExcpStat_SPF_S 0x6000000000000000ul | |
77 | #define IOC_IO_ExcpStat_SPF_P 0x4000000000000000ul | |
78 | #define IOC_IO_ExcpStat_ADDR_Mask 0x00000007fffff000ul | |
79 | #define IOC_IO_ExcpStat_RW_Mask 0x0000000000000800ul | |
80 | #define IOC_IO_ExcpStat_IOID_Mask 0x00000000000007fful | |
81 | ||
82 | #define IOC_IO_ExcpMask 0x928 | |
83 | #define IOC_IO_ExcpMask_SFE 0x4000000000000000ul | |
84 | #define IOC_IO_ExcpMask_PFE 0x2000000000000000ul | |
85 | ||
86 | #define IOC_IOCmd_Offset 0x1000 | |
87 | ||
88 | #define IOC_IOCmd_Cfg 0xc00 | |
89 | #define IOC_IOCmd_Cfg_TE 0x0000800000000000ul | |
90 | ||
91 | ||
92 | /* Segment table entries */ | |
93 | #define IOSTE_V 0x8000000000000000ul /* valid */ | |
94 | #define IOSTE_H 0x4000000000000000ul /* cache hint */ | |
95 | #define IOSTE_PT_Base_RPN_Mask 0x3ffffffffffff000ul /* base RPN of IOPT */ | |
96 | #define IOSTE_NPPT_Mask 0x0000000000000fe0ul /* no. pages in IOPT */ | |
97 | #define IOSTE_PS_Mask 0x0000000000000007ul /* page size */ | |
98 | #define IOSTE_PS_4K 0x0000000000000001ul /* - 4kB */ | |
99 | #define IOSTE_PS_64K 0x0000000000000003ul /* - 64kB */ | |
100 | #define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */ | |
101 | #define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */ | |
102 | ||
103 | /* Page table entries */ | |
104 | #define IOPTE_PP_W 0x8000000000000000ul /* protection: write */ | |
105 | #define IOPTE_PP_R 0x4000000000000000ul /* protection: read */ | |
106 | #define IOPTE_M 0x2000000000000000ul /* coherency required */ | |
107 | #define IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */ | |
108 | #define IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */ | |
109 | #define IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */ | |
110 | #define IOPTE_H 0x0000000000000800ul /* cache hint */ | |
111 | #define IOPTE_IOID_Mask 0x00000000000007fful /* ioid */ | |
112 | ||
113 | ||
114 | /* IOMMU sizing */ | |
115 | #define IO_SEGMENT_SHIFT 28 | |
116 | #define IO_PAGENO_BITS (IO_SEGMENT_SHIFT - IOMMU_PAGE_SHIFT) | |
117 | ||
118 | /* The high bit needs to be set on every DMA address */ | |
119 | #define SPIDER_DMA_OFFSET 0x80000000ul | |
120 | ||
121 | struct iommu_window { | |
122 | struct list_head list; | |
123 | struct cbe_iommu *iommu; | |
124 | unsigned long offset; | |
125 | unsigned long size; | |
165785e5 JK |
126 | unsigned int ioid; |
127 | struct iommu_table table; | |
128 | }; | |
ae209cf1 | 129 | |
165785e5 JK |
130 | #define NAMESIZE 8 |
131 | struct cbe_iommu { | |
132 | int nid; | |
133 | char name[NAMESIZE]; | |
134 | void __iomem *xlate_regs; | |
135 | void __iomem *cmd_regs; | |
136 | unsigned long *stab; | |
137 | unsigned long *ptab; | |
138 | void *pad_page; | |
139 | struct list_head windows; | |
140 | }; | |
ae209cf1 | 141 | |
165785e5 JK |
142 | /* Static array of iommus, one per node |
143 | * each contains a list of windows, keyed from dma_window property | |
144 | * - on bus setup, look for a matching window, or create one | |
145 | * - on dev setup, assign iommu_table ptr | |
146 | */ | |
147 | static struct cbe_iommu iommus[NR_IOMMUS]; | |
148 | static int cbe_nr_iommus; | |
ae209cf1 | 149 | |
165785e5 JK |
150 | static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte, |
151 | long n_ptes) | |
ae209cf1 | 152 | { |
9340b0d3 AV |
153 | unsigned long __iomem *reg; |
154 | unsigned long val; | |
165785e5 | 155 | long n; |
ae209cf1 | 156 | |
165785e5 | 157 | reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; |
ae209cf1 | 158 | |
165785e5 JK |
159 | while (n_ptes > 0) { |
160 | /* we can invalidate up to 1 << 11 PTEs at once */ | |
161 | n = min(n_ptes, 1l << 11); | |
162 | val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask) | |
163 | | (__pa(pte) & IOC_IOPT_CacheInvd_IOPTE_Mask) | |
164 | | IOC_IOPT_CacheInvd_Busy; | |
ae209cf1 | 165 | |
165785e5 JK |
166 | out_be64(reg, val); |
167 | while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy) | |
168 | ; | |
ae209cf1 | 169 | |
165785e5 JK |
170 | n_ptes -= n; |
171 | pte += n; | |
172 | } | |
ae209cf1 AB |
173 | } |
174 | ||
165785e5 JK |
175 | static void tce_build_cell(struct iommu_table *tbl, long index, long npages, |
176 | unsigned long uaddr, enum dma_data_direction direction) | |
ae209cf1 | 177 | { |
165785e5 JK |
178 | int i; |
179 | unsigned long *io_pte, base_pte; | |
180 | struct iommu_window *window = | |
181 | container_of(tbl, struct iommu_window, table); | |
182 | ||
183 | /* implementing proper protection causes problems with the spidernet | |
184 | * driver - check mapping directions later, but allow read & write by | |
185 | * default for now.*/ | |
186 | #ifdef CELL_IOMMU_STRICT_PROTECTION | |
187 | /* to avoid referencing a global, we use a trick here to setup the | |
188 | * protection bit. "prot" is setup to be 3 fields of 4 bits apprended | |
189 | * together for each of the 3 supported direction values. It is then | |
190 | * shifted left so that the fields matching the desired direction | |
191 | * lands on the appropriate bits, and other bits are masked out. | |
192 | */ | |
193 | const unsigned long prot = 0xc48; | |
194 | base_pte = | |
195 | ((prot << (52 + 4 * direction)) & (IOPTE_PP_W | IOPTE_PP_R)) | |
196 | | IOPTE_M | IOPTE_SO_RW | (window->ioid & IOPTE_IOID_Mask); | |
197 | #else | |
198 | base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | | |
199 | (window->ioid & IOPTE_IOID_Mask); | |
200 | #endif | |
201 | ||
0d7386eb | 202 | io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); |
165785e5 JK |
203 | |
204 | for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE) | |
205 | io_pte[i] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask); | |
206 | ||
207 | mb(); | |
208 | ||
209 | invalidate_tce_cache(window->iommu, io_pte, npages); | |
210 | ||
211 | pr_debug("tce_build_cell(index=%lx,n=%lx,dir=%d,base_pte=%lx)\n", | |
212 | index, npages, direction, base_pte); | |
ae209cf1 AB |
213 | } |
214 | ||
165785e5 | 215 | static void tce_free_cell(struct iommu_table *tbl, long index, long npages) |
ae209cf1 | 216 | { |
ae209cf1 | 217 | |
165785e5 JK |
218 | int i; |
219 | unsigned long *io_pte, pte; | |
220 | struct iommu_window *window = | |
221 | container_of(tbl, struct iommu_window, table); | |
ae209cf1 | 222 | |
165785e5 | 223 | pr_debug("tce_free_cell(index=%lx,n=%lx)\n", index, npages); |
ae209cf1 | 224 | |
165785e5 JK |
225 | #ifdef CELL_IOMMU_REAL_UNMAP |
226 | pte = 0; | |
227 | #else | |
228 | /* spider bridge does PCI reads after freeing - insert a mapping | |
229 | * to a scratch page instead of an invalid entry */ | |
230 | pte = IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | __pa(window->iommu->pad_page) | |
231 | | (window->ioid & IOPTE_IOID_Mask); | |
232 | #endif | |
ae209cf1 | 233 | |
0d7386eb | 234 | io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); |
ae209cf1 | 235 | |
165785e5 JK |
236 | for (i = 0; i < npages; i++) |
237 | io_pte[i] = pte; | |
238 | ||
239 | mb(); | |
ae209cf1 | 240 | |
165785e5 | 241 | invalidate_tce_cache(window->iommu, io_pte, npages); |
ae209cf1 AB |
242 | } |
243 | ||
165785e5 | 244 | static irqreturn_t ioc_interrupt(int irq, void *data) |
ae209cf1 | 245 | { |
165785e5 JK |
246 | unsigned long stat; |
247 | struct cbe_iommu *iommu = data; | |
248 | ||
249 | stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); | |
250 | ||
251 | /* Might want to rate limit it */ | |
252 | printk(KERN_ERR "iommu: DMA exception 0x%016lx\n", stat); | |
253 | printk(KERN_ERR " V=%d, SPF=[%c%c], RW=%s, IOID=0x%04x\n", | |
254 | !!(stat & IOC_IO_ExcpStat_V), | |
255 | (stat & IOC_IO_ExcpStat_SPF_S) ? 'S' : ' ', | |
256 | (stat & IOC_IO_ExcpStat_SPF_P) ? 'P' : ' ', | |
257 | (stat & IOC_IO_ExcpStat_RW_Mask) ? "Read" : "Write", | |
258 | (unsigned int)(stat & IOC_IO_ExcpStat_IOID_Mask)); | |
259 | printk(KERN_ERR " page=0x%016lx\n", | |
260 | stat & IOC_IO_ExcpStat_ADDR_Mask); | |
261 | ||
262 | /* clear interrupt */ | |
263 | stat &= ~IOC_IO_ExcpStat_V; | |
264 | out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat); | |
265 | ||
266 | return IRQ_HANDLED; | |
ae209cf1 AB |
267 | } |
268 | ||
165785e5 | 269 | static int cell_iommu_find_ioc(int nid, unsigned long *base) |
ae209cf1 | 270 | { |
165785e5 JK |
271 | struct device_node *np; |
272 | struct resource r; | |
273 | ||
274 | *base = 0; | |
275 | ||
276 | /* First look for new style /be nodes */ | |
277 | for_each_node_by_name(np, "ioc") { | |
278 | if (of_node_to_nid(np) != nid) | |
279 | continue; | |
280 | if (of_address_to_resource(np, 0, &r)) { | |
281 | printk(KERN_ERR "iommu: can't get address for %s\n", | |
282 | np->full_name); | |
283 | continue; | |
284 | } | |
285 | *base = r.start; | |
286 | of_node_put(np); | |
287 | return 0; | |
288 | } | |
289 | ||
290 | /* Ok, let's try the old way */ | |
291 | for_each_node_by_type(np, "cpu") { | |
292 | const unsigned int *nidp; | |
293 | const unsigned long *tmp; | |
294 | ||
e2eb6392 | 295 | nidp = of_get_property(np, "node-id", NULL); |
165785e5 | 296 | if (nidp && *nidp == nid) { |
e2eb6392 | 297 | tmp = of_get_property(np, "ioc-translation", NULL); |
165785e5 JK |
298 | if (tmp) { |
299 | *base = *tmp; | |
300 | of_node_put(np); | |
301 | return 0; | |
302 | } | |
303 | } | |
304 | } | |
ae209cf1 | 305 | |
165785e5 | 306 | return -ENODEV; |
ae209cf1 AB |
307 | } |
308 | ||
7d432ff1 | 309 | static void cell_iommu_setup_stab(struct cbe_iommu *iommu, |
41347917 ME |
310 | unsigned long dbase, unsigned long dsize, |
311 | unsigned long fbase, unsigned long fsize) | |
ae209cf1 | 312 | { |
165785e5 | 313 | struct page *page; |
7d432ff1 | 314 | unsigned long segments, stab_size; |
41347917 ME |
315 | |
316 | segments = max(dbase + dsize, fbase + fsize) >> IO_SEGMENT_SHIFT; | |
165785e5 | 317 | |
7d432ff1 ME |
318 | pr_debug("%s: iommu[%d]: segments: %lu\n", |
319 | __FUNCTION__, iommu->nid, segments); | |
165785e5 JK |
320 | |
321 | /* set up the segment table */ | |
3ca6644e ME |
322 | stab_size = segments * sizeof(unsigned long); |
323 | page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(stab_size)); | |
165785e5 JK |
324 | BUG_ON(!page); |
325 | iommu->stab = page_address(page); | |
7d432ff1 ME |
326 | memset(iommu->stab, 0, stab_size); |
327 | } | |
328 | ||
329 | static unsigned long *cell_iommu_alloc_ptab(struct cbe_iommu *iommu, | |
330 | unsigned long base, unsigned long size, unsigned long gap_base, | |
331 | unsigned long gap_size) | |
332 | { | |
333 | struct page *page; | |
334 | int i; | |
335 | unsigned long reg, segments, pages_per_segment, ptab_size, | |
336 | n_pte_pages, start_seg, *ptab; | |
337 | ||
338 | start_seg = base >> IO_SEGMENT_SHIFT; | |
339 | segments = size >> IO_SEGMENT_SHIFT; | |
340 | pages_per_segment = 1ull << IO_PAGENO_BITS; | |
165785e5 | 341 | |
165785e5 JK |
342 | ptab_size = segments * pages_per_segment * sizeof(unsigned long); |
343 | pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __FUNCTION__, | |
344 | iommu->nid, ptab_size, get_order(ptab_size)); | |
345 | page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size)); | |
346 | BUG_ON(!page); | |
347 | ||
7d432ff1 ME |
348 | ptab = page_address(page); |
349 | memset(ptab, 0, ptab_size); | |
165785e5 | 350 | |
165785e5 JK |
351 | /* number of pages needed for a page table */ |
352 | n_pte_pages = (pages_per_segment * | |
353 | sizeof(unsigned long)) >> IOMMU_PAGE_SHIFT; | |
354 | ||
355 | pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n", | |
7d432ff1 | 356 | __FUNCTION__, iommu->nid, iommu->stab, ptab, |
165785e5 JK |
357 | n_pte_pages); |
358 | ||
359 | /* initialise the STEs */ | |
360 | reg = IOSTE_V | ((n_pte_pages - 1) << 5); | |
361 | ||
362 | if (IOMMU_PAGE_SIZE == 0x1000) | |
363 | reg |= IOSTE_PS_4K; | |
364 | else if (IOMMU_PAGE_SIZE == 0x10000) | |
365 | reg |= IOSTE_PS_64K; | |
366 | else { | |
367 | extern void __unknown_page_size_error(void); | |
368 | __unknown_page_size_error(); | |
369 | } | |
ae209cf1 | 370 | |
7d432ff1 ME |
371 | gap_base = gap_base >> IO_SEGMENT_SHIFT; |
372 | gap_size = gap_size >> IO_SEGMENT_SHIFT; | |
373 | ||
165785e5 | 374 | pr_debug("Setting up IOMMU stab:\n"); |
7d432ff1 ME |
375 | for (i = start_seg; i < (start_seg + segments); i++) { |
376 | if (i >= gap_base && i < (gap_base + gap_size)) { | |
377 | pr_debug("\toverlap at %d, skipping\n", i); | |
378 | continue; | |
379 | } | |
380 | iommu->stab[i] = reg | (__pa(ptab) + n_pte_pages * | |
381 | IOMMU_PAGE_SIZE * (i - start_seg)); | |
165785e5 JK |
382 | pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]); |
383 | } | |
7d432ff1 ME |
384 | |
385 | return ptab; | |
7fc67afc ME |
386 | } |
387 | ||
388 | static void cell_iommu_enable_hardware(struct cbe_iommu *iommu) | |
389 | { | |
390 | int ret; | |
391 | unsigned long reg, xlate_base; | |
392 | unsigned int virq; | |
393 | ||
394 | if (cell_iommu_find_ioc(iommu->nid, &xlate_base)) | |
395 | panic("%s: missing IOC register mappings for node %d\n", | |
396 | __FUNCTION__, iommu->nid); | |
397 | ||
398 | iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size); | |
399 | iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset; | |
165785e5 JK |
400 | |
401 | /* ensure that the STEs have updated */ | |
402 | mb(); | |
403 | ||
404 | /* setup interrupts for the iommu. */ | |
405 | reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); | |
406 | out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, | |
407 | reg & ~IOC_IO_ExcpStat_V); | |
408 | out_be64(iommu->xlate_regs + IOC_IO_ExcpMask, | |
409 | IOC_IO_ExcpMask_PFE | IOC_IO_ExcpMask_SFE); | |
410 | ||
411 | virq = irq_create_mapping(NULL, | |
412 | IIC_IRQ_IOEX_ATI | (iommu->nid << IIC_IRQ_NODE_SHIFT)); | |
413 | BUG_ON(virq == NO_IRQ); | |
414 | ||
415 | ret = request_irq(virq, ioc_interrupt, IRQF_DISABLED, | |
416 | iommu->name, iommu); | |
417 | BUG_ON(ret); | |
49d65b3a | 418 | |
165785e5 JK |
419 | /* set the IOC segment table origin register (and turn on the iommu) */ |
420 | reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW; | |
421 | out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg); | |
422 | in_be64(iommu->xlate_regs + IOC_IOST_Origin); | |
ae209cf1 | 423 | |
165785e5 JK |
424 | /* turn on IO translation */ |
425 | reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE; | |
426 | out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg); | |
427 | } | |
428 | ||
7fc67afc ME |
429 | static void cell_iommu_setup_hardware(struct cbe_iommu *iommu, |
430 | unsigned long base, unsigned long size) | |
431 | { | |
7d432ff1 ME |
432 | cell_iommu_setup_stab(iommu, base, size, 0, 0); |
433 | iommu->ptab = cell_iommu_alloc_ptab(iommu, base, size, 0, 0); | |
7fc67afc ME |
434 | cell_iommu_enable_hardware(iommu); |
435 | } | |
436 | ||
165785e5 JK |
437 | #if 0/* Unused for now */ |
438 | static struct iommu_window *find_window(struct cbe_iommu *iommu, | |
439 | unsigned long offset, unsigned long size) | |
ae209cf1 | 440 | { |
165785e5 | 441 | struct iommu_window *window; |
ae209cf1 | 442 | |
165785e5 JK |
443 | /* todo: check for overlapping (but not equal) windows) */ |
444 | ||
445 | list_for_each_entry(window, &(iommu->windows), list) { | |
446 | if (window->offset == offset && window->size == size) | |
447 | return window; | |
49d65b3a | 448 | } |
165785e5 JK |
449 | |
450 | return NULL; | |
49d65b3a | 451 | } |
165785e5 | 452 | #endif |
ae209cf1 | 453 | |
c96b5126 ME |
454 | static inline u32 cell_iommu_get_ioid(struct device_node *np) |
455 | { | |
456 | const u32 *ioid; | |
457 | ||
458 | ioid = of_get_property(np, "ioid", NULL); | |
459 | if (ioid == NULL) { | |
460 | printk(KERN_WARNING "iommu: missing ioid for %s using 0\n", | |
461 | np->full_name); | |
462 | return 0; | |
463 | } | |
464 | ||
465 | return *ioid; | |
466 | } | |
467 | ||
165785e5 JK |
468 | static struct iommu_window * __init |
469 | cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np, | |
470 | unsigned long offset, unsigned long size, | |
471 | unsigned long pte_offset) | |
49d65b3a | 472 | { |
165785e5 | 473 | struct iommu_window *window; |
edf441fb | 474 | struct page *page; |
c96b5126 | 475 | u32 ioid; |
ae209cf1 | 476 | |
c96b5126 | 477 | ioid = cell_iommu_get_ioid(np); |
165785e5 JK |
478 | |
479 | window = kmalloc_node(sizeof(*window), GFP_KERNEL, iommu->nid); | |
480 | BUG_ON(window == NULL); | |
481 | ||
482 | window->offset = offset; | |
483 | window->size = size; | |
c96b5126 | 484 | window->ioid = ioid; |
165785e5 | 485 | window->iommu = iommu; |
165785e5 JK |
486 | |
487 | window->table.it_blocksize = 16; | |
488 | window->table.it_base = (unsigned long)iommu->ptab; | |
489 | window->table.it_index = iommu->nid; | |
08e02427 | 490 | window->table.it_offset = (offset >> IOMMU_PAGE_SHIFT) + pte_offset; |
165785e5 JK |
491 | window->table.it_size = size >> IOMMU_PAGE_SHIFT; |
492 | ||
493 | iommu_init_table(&window->table, iommu->nid); | |
494 | ||
495 | pr_debug("\tioid %d\n", window->ioid); | |
496 | pr_debug("\tblocksize %ld\n", window->table.it_blocksize); | |
497 | pr_debug("\tbase 0x%016lx\n", window->table.it_base); | |
498 | pr_debug("\toffset 0x%lx\n", window->table.it_offset); | |
499 | pr_debug("\tsize %ld\n", window->table.it_size); | |
500 | ||
501 | list_add(&window->list, &iommu->windows); | |
502 | ||
503 | if (offset != 0) | |
504 | return window; | |
505 | ||
506 | /* We need to map and reserve the first IOMMU page since it's used | |
507 | * by the spider workaround. In theory, we only need to do that when | |
508 | * running on spider but it doesn't really matter. | |
509 | * | |
510 | * This code also assumes that we have a window that starts at 0, | |
511 | * which is the case on all spider based blades. | |
512 | */ | |
edf441fb ME |
513 | page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0); |
514 | BUG_ON(!page); | |
515 | iommu->pad_page = page_address(page); | |
516 | clear_page(iommu->pad_page); | |
517 | ||
165785e5 JK |
518 | __set_bit(0, window->table.it_map); |
519 | tce_build_cell(&window->table, window->table.it_offset, 1, | |
520 | (unsigned long)iommu->pad_page, DMA_TO_DEVICE); | |
521 | window->table.it_hint = window->table.it_blocksize; | |
522 | ||
523 | return window; | |
524 | } | |
ae209cf1 | 525 | |
165785e5 JK |
526 | static struct cbe_iommu *cell_iommu_for_node(int nid) |
527 | { | |
528 | int i; | |
49d65b3a | 529 | |
165785e5 JK |
530 | for (i = 0; i < cbe_nr_iommus; i++) |
531 | if (iommus[i].nid == nid) | |
532 | return &iommus[i]; | |
533 | return NULL; | |
534 | } | |
49d65b3a | 535 | |
f5d67bd5 ME |
536 | static unsigned long cell_dma_direct_offset; |
537 | ||
99e13912 ME |
538 | static unsigned long dma_iommu_fixed_base; |
539 | struct dma_mapping_ops dma_iommu_fixed_ops; | |
540 | ||
86865771 | 541 | static void cell_dma_dev_setup_iommu(struct device *dev) |
165785e5 JK |
542 | { |
543 | struct iommu_window *window; | |
544 | struct cbe_iommu *iommu; | |
545 | struct dev_archdata *archdata = &dev->archdata; | |
546 | ||
165785e5 JK |
547 | /* Current implementation uses the first window available in that |
548 | * node's iommu. We -might- do something smarter later though it may | |
549 | * never be necessary | |
550 | */ | |
551 | iommu = cell_iommu_for_node(archdata->numa_node); | |
552 | if (iommu == NULL || list_empty(&iommu->windows)) { | |
553 | printk(KERN_ERR "iommu: missing iommu for %s (node %d)\n", | |
554 | archdata->of_node ? archdata->of_node->full_name : "?", | |
555 | archdata->numa_node); | |
556 | return; | |
557 | } | |
558 | window = list_entry(iommu->windows.next, struct iommu_window, list); | |
49d65b3a | 559 | |
165785e5 | 560 | archdata->dma_data = &window->table; |
49d65b3a JO |
561 | } |
562 | ||
f9660e8a | 563 | static void cell_dma_dev_setup_fixed(struct device *dev); |
99e13912 | 564 | |
86865771 ME |
565 | static void cell_dma_dev_setup(struct device *dev) |
566 | { | |
567 | struct dev_archdata *archdata = &dev->archdata; | |
568 | ||
99e13912 ME |
569 | /* Order is important here, these are not mutually exclusive */ |
570 | if (get_dma_ops(dev) == &dma_iommu_fixed_ops) | |
f9660e8a | 571 | cell_dma_dev_setup_fixed(dev); |
99e13912 | 572 | else if (get_pci_dma_ops() == &dma_iommu_ops) |
86865771 ME |
573 | cell_dma_dev_setup_iommu(dev); |
574 | else if (get_pci_dma_ops() == &dma_direct_ops) | |
575 | archdata->dma_data = (void *)cell_dma_direct_offset; | |
576 | else | |
577 | BUG(); | |
578 | } | |
579 | ||
165785e5 | 580 | static void cell_pci_dma_dev_setup(struct pci_dev *dev) |
49d65b3a | 581 | { |
165785e5 JK |
582 | cell_dma_dev_setup(&dev->dev); |
583 | } | |
49d65b3a | 584 | |
165785e5 JK |
585 | static int cell_of_bus_notify(struct notifier_block *nb, unsigned long action, |
586 | void *data) | |
587 | { | |
588 | struct device *dev = data; | |
49d65b3a | 589 | |
165785e5 JK |
590 | /* We are only intereted in device addition */ |
591 | if (action != BUS_NOTIFY_ADD_DEVICE) | |
592 | return 0; | |
49d65b3a | 593 | |
165785e5 | 594 | /* We use the PCI DMA ops */ |
57190708 | 595 | dev->archdata.dma_ops = get_pci_dma_ops(); |
49d65b3a | 596 | |
165785e5 | 597 | cell_dma_dev_setup(dev); |
49d65b3a | 598 | |
165785e5 JK |
599 | return 0; |
600 | } | |
49d65b3a | 601 | |
165785e5 JK |
602 | static struct notifier_block cell_of_bus_notifier = { |
603 | .notifier_call = cell_of_bus_notify | |
604 | }; | |
49d65b3a | 605 | |
165785e5 JK |
606 | static int __init cell_iommu_get_window(struct device_node *np, |
607 | unsigned long *base, | |
608 | unsigned long *size) | |
609 | { | |
610 | const void *dma_window; | |
611 | unsigned long index; | |
49d65b3a | 612 | |
165785e5 | 613 | /* Use ibm,dma-window if available, else, hard code ! */ |
e2eb6392 | 614 | dma_window = of_get_property(np, "ibm,dma-window", NULL); |
165785e5 JK |
615 | if (dma_window == NULL) { |
616 | *base = 0; | |
617 | *size = 0x80000000u; | |
618 | return -ENODEV; | |
619 | } | |
49d65b3a | 620 | |
165785e5 | 621 | of_parse_dma_window(np, dma_window, &index, base, size); |
49d65b3a | 622 | return 0; |
ae209cf1 AB |
623 | } |
624 | ||
209bfbb4 | 625 | static struct cbe_iommu * __init cell_iommu_alloc(struct device_node *np) |
49d65b3a | 626 | { |
165785e5 | 627 | struct cbe_iommu *iommu; |
165785e5 JK |
628 | int nid, i; |
629 | ||
630 | /* Get node ID */ | |
631 | nid = of_node_to_nid(np); | |
632 | if (nid < 0) { | |
633 | printk(KERN_ERR "iommu: failed to get node for %s\n", | |
634 | np->full_name); | |
209bfbb4 | 635 | return NULL; |
165785e5 JK |
636 | } |
637 | pr_debug("iommu: setting up iommu for node %d (%s)\n", | |
638 | nid, np->full_name); | |
639 | ||
640 | /* XXX todo: If we can have multiple windows on the same IOMMU, which | |
641 | * isn't the case today, we probably want here to check wether the | |
642 | * iommu for that node is already setup. | |
643 | * However, there might be issue with getting the size right so let's | |
644 | * ignore that for now. We might want to completely get rid of the | |
645 | * multiple window support since the cell iommu supports per-page ioids | |
646 | */ | |
647 | ||
648 | if (cbe_nr_iommus >= NR_IOMMUS) { | |
649 | printk(KERN_ERR "iommu: too many IOMMUs detected ! (%s)\n", | |
650 | np->full_name); | |
209bfbb4 | 651 | return NULL; |
165785e5 JK |
652 | } |
653 | ||
654 | /* Init base fields */ | |
655 | i = cbe_nr_iommus++; | |
656 | iommu = &iommus[i]; | |
9340b0d3 | 657 | iommu->stab = NULL; |
165785e5 JK |
658 | iommu->nid = nid; |
659 | snprintf(iommu->name, sizeof(iommu->name), "iommu%d", i); | |
660 | INIT_LIST_HEAD(&iommu->windows); | |
49d65b3a | 661 | |
209bfbb4 ME |
662 | return iommu; |
663 | } | |
664 | ||
665 | static void __init cell_iommu_init_one(struct device_node *np, | |
666 | unsigned long offset) | |
667 | { | |
668 | struct cbe_iommu *iommu; | |
669 | unsigned long base, size; | |
670 | ||
671 | iommu = cell_iommu_alloc(np); | |
672 | if (!iommu) | |
673 | return; | |
674 | ||
165785e5 JK |
675 | /* Obtain a window for it */ |
676 | cell_iommu_get_window(np, &base, &size); | |
49d65b3a | 677 | |
165785e5 JK |
678 | pr_debug("\ttranslating window 0x%lx...0x%lx\n", |
679 | base, base + size - 1); | |
49d65b3a | 680 | |
165785e5 | 681 | /* Initialize the hardware */ |
7fc67afc | 682 | cell_iommu_setup_hardware(iommu, base, size); |
49d65b3a | 683 | |
165785e5 JK |
684 | /* Setup the iommu_table */ |
685 | cell_iommu_setup_window(iommu, np, base, size, | |
686 | offset >> IOMMU_PAGE_SHIFT); | |
687 | } | |
49d65b3a | 688 | |
165785e5 JK |
689 | static void __init cell_disable_iommus(void) |
690 | { | |
691 | int node; | |
692 | unsigned long base, val; | |
693 | void __iomem *xregs, *cregs; | |
694 | ||
695 | /* Make sure IOC translation is disabled on all nodes */ | |
696 | for_each_online_node(node) { | |
697 | if (cell_iommu_find_ioc(node, &base)) | |
698 | continue; | |
699 | xregs = ioremap(base, IOC_Reg_Size); | |
700 | if (xregs == NULL) | |
701 | continue; | |
702 | cregs = xregs + IOC_IOCmd_Offset; | |
703 | ||
704 | pr_debug("iommu: cleaning up iommu on node %d\n", node); | |
705 | ||
706 | out_be64(xregs + IOC_IOST_Origin, 0); | |
707 | (void)in_be64(xregs + IOC_IOST_Origin); | |
708 | val = in_be64(cregs + IOC_IOCmd_Cfg); | |
709 | val &= ~IOC_IOCmd_Cfg_TE; | |
710 | out_be64(cregs + IOC_IOCmd_Cfg, val); | |
711 | (void)in_be64(cregs + IOC_IOCmd_Cfg); | |
712 | ||
713 | iounmap(xregs); | |
714 | } | |
715 | } | |
49d65b3a | 716 | |
165785e5 JK |
717 | static int __init cell_iommu_init_disabled(void) |
718 | { | |
719 | struct device_node *np = NULL; | |
720 | unsigned long base = 0, size; | |
49d65b3a | 721 | |
165785e5 | 722 | /* When no iommu is present, we use direct DMA ops */ |
98747770 | 723 | set_pci_dma_ops(&dma_direct_ops); |
49d65b3a | 724 | |
165785e5 JK |
725 | /* First make sure all IOC translation is turned off */ |
726 | cell_disable_iommus(); | |
727 | ||
728 | /* If we have no Axon, we set up the spider DMA magic offset */ | |
729 | if (of_find_node_by_name(NULL, "axon") == NULL) | |
f5d67bd5 | 730 | cell_dma_direct_offset = SPIDER_DMA_OFFSET; |
165785e5 JK |
731 | |
732 | /* Now we need to check to see where the memory is mapped | |
733 | * in PCI space. We assume that all busses use the same dma | |
734 | * window which is always the case so far on Cell, thus we | |
735 | * pick up the first pci-internal node we can find and check | |
736 | * the DMA window from there. | |
737 | */ | |
738 | for_each_node_by_name(np, "axon") { | |
739 | if (np->parent == NULL || np->parent->parent != NULL) | |
740 | continue; | |
741 | if (cell_iommu_get_window(np, &base, &size) == 0) | |
742 | break; | |
743 | } | |
744 | if (np == NULL) { | |
745 | for_each_node_by_name(np, "pci-internal") { | |
746 | if (np->parent == NULL || np->parent->parent != NULL) | |
747 | continue; | |
748 | if (cell_iommu_get_window(np, &base, &size) == 0) | |
749 | break; | |
750 | } | |
751 | } | |
752 | of_node_put(np); | |
753 | ||
754 | /* If we found a DMA window, we check if it's big enough to enclose | |
755 | * all of physical memory. If not, we force enable IOMMU | |
756 | */ | |
757 | if (np && size < lmb_end_of_DRAM()) { | |
758 | printk(KERN_WARNING "iommu: force-enabled, dma window" | |
759 | " (%ldMB) smaller than total memory (%ldMB)\n", | |
760 | size >> 20, lmb_end_of_DRAM() >> 20); | |
761 | return -ENODEV; | |
49d65b3a JO |
762 | } |
763 | ||
f5d67bd5 | 764 | cell_dma_direct_offset += base; |
165785e5 | 765 | |
f5d67bd5 | 766 | if (cell_dma_direct_offset != 0) |
110f95c9 ME |
767 | ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup; |
768 | ||
165785e5 | 769 | printk("iommu: disabled, direct DMA offset is 0x%lx\n", |
f5d67bd5 | 770 | cell_dma_direct_offset); |
165785e5 JK |
771 | |
772 | return 0; | |
49d65b3a JO |
773 | } |
774 | ||
99e13912 ME |
775 | /* |
776 | * Fixed IOMMU mapping support | |
777 | * | |
778 | * This code adds support for setting up a fixed IOMMU mapping on certain | |
779 | * cell machines. For 64-bit devices this avoids the performance overhead of | |
780 | * mapping and unmapping pages at runtime. 32-bit devices are unable to use | |
781 | * the fixed mapping. | |
782 | * | |
783 | * The fixed mapping is established at boot, and maps all of physical memory | |
784 | * 1:1 into device space at some offset. On machines with < 30 GB of memory | |
785 | * we setup the fixed mapping immediately above the normal IOMMU window. | |
786 | * | |
787 | * For example a machine with 4GB of memory would end up with the normal | |
788 | * IOMMU window from 0-2GB and the fixed mapping window from 2GB to 6GB. In | |
789 | * this case a 64-bit device wishing to DMA to 1GB would be told to DMA to | |
790 | * 3GB, plus any offset required by firmware. The firmware offset is encoded | |
791 | * in the "dma-ranges" property. | |
792 | * | |
793 | * On machines with 30GB or more of memory, we are unable to place the fixed | |
794 | * mapping above the normal IOMMU window as we would run out of address space. | |
795 | * Instead we move the normal IOMMU window to coincide with the hash page | |
796 | * table, this region does not need to be part of the fixed mapping as no | |
797 | * device should ever be DMA'ing to it. We then setup the fixed mapping | |
798 | * from 0 to 32GB. | |
799 | */ | |
800 | ||
801 | static u64 cell_iommu_get_fixed_address(struct device *dev) | |
802 | { | |
803 | u64 cpu_addr, size, best_size, pci_addr = OF_BAD_ADDR; | |
ccd05d08 | 804 | struct device_node *np; |
99e13912 ME |
805 | const u32 *ranges = NULL; |
806 | int i, len, best; | |
807 | ||
ccd05d08 ME |
808 | np = of_node_get(dev->archdata.of_node); |
809 | while (np) { | |
99e13912 | 810 | ranges = of_get_property(np, "dma-ranges", &len); |
ccd05d08 ME |
811 | if (ranges) |
812 | break; | |
813 | np = of_get_next_parent(np); | |
99e13912 ME |
814 | } |
815 | ||
816 | if (!ranges) { | |
817 | dev_dbg(dev, "iommu: no dma-ranges found\n"); | |
818 | goto out; | |
819 | } | |
820 | ||
821 | len /= sizeof(u32); | |
822 | ||
823 | /* dma-ranges format: | |
824 | * 1 cell: pci space | |
825 | * 2 cells: pci address | |
826 | * 2 cells: parent address | |
827 | * 2 cells: size | |
828 | */ | |
829 | for (i = 0, best = -1, best_size = 0; i < len; i += 7) { | |
830 | cpu_addr = of_translate_dma_address(np, ranges +i + 3); | |
831 | size = of_read_number(ranges + i + 5, 2); | |
832 | ||
833 | if (cpu_addr == 0 && size > best_size) { | |
834 | best = i; | |
835 | best_size = size; | |
836 | } | |
837 | } | |
838 | ||
839 | if (best >= 0) | |
840 | pci_addr = of_read_number(ranges + best + 1, 2); | |
841 | else | |
842 | dev_dbg(dev, "iommu: no suitable range found!\n"); | |
843 | ||
844 | out: | |
845 | of_node_put(np); | |
846 | ||
847 | return pci_addr; | |
848 | } | |
849 | ||
850 | static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask) | |
851 | { | |
852 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
853 | return -EIO; | |
854 | ||
4a8df150 ME |
855 | if (dma_mask == DMA_BIT_MASK(64) && |
856 | cell_iommu_get_fixed_address(dev) != OF_BAD_ADDR) | |
857 | { | |
858 | dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n"); | |
859 | set_dma_ops(dev, &dma_iommu_fixed_ops); | |
99e13912 ME |
860 | } else { |
861 | dev_dbg(dev, "iommu: not 64-bit, using default ops\n"); | |
862 | set_dma_ops(dev, get_pci_dma_ops()); | |
863 | } | |
864 | ||
4a8df150 ME |
865 | cell_dma_dev_setup(dev); |
866 | ||
99e13912 ME |
867 | *dev->dma_mask = dma_mask; |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
f9660e8a | 872 | static void cell_dma_dev_setup_fixed(struct device *dev) |
99e13912 ME |
873 | { |
874 | struct dev_archdata *archdata = &dev->archdata; | |
875 | u64 addr; | |
876 | ||
877 | addr = cell_iommu_get_fixed_address(dev) + dma_iommu_fixed_base; | |
878 | archdata->dma_data = (void *)addr; | |
879 | ||
880 | dev_dbg(dev, "iommu: fixed addr = %lx\n", addr); | |
881 | } | |
882 | ||
883 | static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu, | |
884 | struct device_node *np, unsigned long dbase, unsigned long dsize, | |
885 | unsigned long fbase, unsigned long fsize) | |
886 | { | |
99e13912 | 887 | int i; |
7d432ff1 ME |
888 | unsigned long base_pte, uaddr, *io_pte, *ptab; |
889 | ||
890 | ptab = cell_iommu_alloc_ptab(iommu, fbase, fsize, dbase, dsize); | |
99e13912 ME |
891 | |
892 | dma_iommu_fixed_base = fbase; | |
893 | ||
894 | /* convert from bytes into page table indices */ | |
895 | dbase = dbase >> IOMMU_PAGE_SHIFT; | |
896 | dsize = dsize >> IOMMU_PAGE_SHIFT; | |
897 | fbase = fbase >> IOMMU_PAGE_SHIFT; | |
898 | fsize = fsize >> IOMMU_PAGE_SHIFT; | |
899 | ||
900 | pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase); | |
901 | ||
7d432ff1 | 902 | io_pte = ptab; |
99e13912 ME |
903 | base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW |
904 | | (cell_iommu_get_ioid(np) & IOPTE_IOID_Mask); | |
905 | ||
906 | uaddr = 0; | |
907 | for (i = fbase; i < fbase + fsize; i++, uaddr += IOMMU_PAGE_SIZE) { | |
908 | /* Don't touch the dynamic region */ | |
909 | if (i >= dbase && i < (dbase + dsize)) { | |
f9660e8a | 910 | pr_debug("iommu: fixed/dynamic overlap, skipping\n"); |
99e13912 ME |
911 | continue; |
912 | } | |
7d432ff1 | 913 | io_pte[i - fbase] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask); |
99e13912 ME |
914 | } |
915 | ||
916 | mb(); | |
917 | } | |
918 | ||
919 | static int __init cell_iommu_fixed_mapping_init(void) | |
920 | { | |
921 | unsigned long dbase, dsize, fbase, fsize, hbase, hend; | |
922 | struct cbe_iommu *iommu; | |
923 | struct device_node *np; | |
924 | ||
925 | /* The fixed mapping is only supported on axon machines */ | |
926 | np = of_find_node_by_name(NULL, "axon"); | |
927 | if (!np) { | |
928 | pr_debug("iommu: fixed mapping disabled, no axons found\n"); | |
929 | return -1; | |
930 | } | |
931 | ||
0e0b47ab ME |
932 | /* We must have dma-ranges properties for fixed mapping to work */ |
933 | for (np = NULL; (np = of_find_all_nodes(np));) { | |
934 | if (of_find_property(np, "dma-ranges", NULL)) | |
935 | break; | |
936 | } | |
937 | of_node_put(np); | |
938 | ||
939 | if (!np) { | |
940 | pr_debug("iommu: no dma-ranges found, no fixed mapping\n"); | |
941 | return -1; | |
942 | } | |
943 | ||
99e13912 ME |
944 | /* The default setup is to have the fixed mapping sit after the |
945 | * dynamic region, so find the top of the largest IOMMU window | |
946 | * on any axon, then add the size of RAM and that's our max value. | |
947 | * If that is > 32GB we have to do other shennanigans. | |
948 | */ | |
949 | fbase = 0; | |
950 | for_each_node_by_name(np, "axon") { | |
951 | cell_iommu_get_window(np, &dbase, &dsize); | |
952 | fbase = max(fbase, dbase + dsize); | |
953 | } | |
954 | ||
955 | fbase = _ALIGN_UP(fbase, 1 << IO_SEGMENT_SHIFT); | |
956 | fsize = lmb_phys_mem_size(); | |
957 | ||
958 | if ((fbase + fsize) <= 0x800000000) | |
959 | hbase = 0; /* use the device tree window */ | |
960 | else { | |
961 | /* If we're over 32 GB we need to cheat. We can't map all of | |
962 | * RAM with the fixed mapping, and also fit the dynamic | |
963 | * region. So try to place the dynamic region where the hash | |
964 | * table sits, drivers never need to DMA to it, we don't | |
965 | * need a fixed mapping for that area. | |
966 | */ | |
967 | if (!htab_address) { | |
968 | pr_debug("iommu: htab is NULL, on LPAR? Huh?\n"); | |
969 | return -1; | |
970 | } | |
971 | hbase = __pa(htab_address); | |
972 | hend = hbase + htab_size_bytes; | |
973 | ||
974 | /* The window must start and end on a segment boundary */ | |
975 | if ((hbase != _ALIGN_UP(hbase, 1 << IO_SEGMENT_SHIFT)) || | |
976 | (hend != _ALIGN_UP(hend, 1 << IO_SEGMENT_SHIFT))) { | |
977 | pr_debug("iommu: hash window not segment aligned\n"); | |
978 | return -1; | |
979 | } | |
980 | ||
981 | /* Check the hash window fits inside the real DMA window */ | |
982 | for_each_node_by_name(np, "axon") { | |
983 | cell_iommu_get_window(np, &dbase, &dsize); | |
984 | ||
985 | if (hbase < dbase || (hend > (dbase + dsize))) { | |
986 | pr_debug("iommu: hash window doesn't fit in" | |
987 | "real DMA window\n"); | |
988 | return -1; | |
989 | } | |
990 | } | |
991 | ||
992 | fbase = 0; | |
993 | } | |
994 | ||
995 | /* Setup the dynamic regions */ | |
996 | for_each_node_by_name(np, "axon") { | |
997 | iommu = cell_iommu_alloc(np); | |
998 | BUG_ON(!iommu); | |
999 | ||
1000 | if (hbase == 0) | |
1001 | cell_iommu_get_window(np, &dbase, &dsize); | |
1002 | else { | |
1003 | dbase = hbase; | |
1004 | dsize = htab_size_bytes; | |
1005 | } | |
1006 | ||
44621be4 ME |
1007 | printk(KERN_DEBUG "iommu: node %d, dynamic window 0x%lx-0x%lx " |
1008 | "fixed window 0x%lx-0x%lx\n", iommu->nid, dbase, | |
99e13912 ME |
1009 | dbase + dsize, fbase, fbase + fsize); |
1010 | ||
7d432ff1 ME |
1011 | cell_iommu_setup_stab(iommu, dbase, dsize, fbase, fsize); |
1012 | iommu->ptab = cell_iommu_alloc_ptab(iommu, dbase, dsize, 0, 0); | |
99e13912 ME |
1013 | cell_iommu_setup_fixed_ptab(iommu, np, dbase, dsize, |
1014 | fbase, fsize); | |
1015 | cell_iommu_enable_hardware(iommu); | |
1016 | cell_iommu_setup_window(iommu, np, dbase, dsize, 0); | |
1017 | } | |
1018 | ||
1019 | dma_iommu_fixed_ops = dma_direct_ops; | |
1020 | dma_iommu_fixed_ops.set_dma_mask = dma_set_mask_and_switch; | |
1021 | ||
1022 | dma_iommu_ops.set_dma_mask = dma_set_mask_and_switch; | |
1023 | set_pci_dma_ops(&dma_iommu_ops); | |
1024 | ||
99e13912 ME |
1025 | return 0; |
1026 | } | |
1027 | ||
1028 | static int iommu_fixed_disabled; | |
1029 | ||
1030 | static int __init setup_iommu_fixed(char *str) | |
1031 | { | |
1032 | if (strcmp(str, "off") == 0) | |
1033 | iommu_fixed_disabled = 1; | |
1034 | ||
1035 | return 1; | |
1036 | } | |
1037 | __setup("iommu_fixed=", setup_iommu_fixed); | |
1038 | ||
165785e5 | 1039 | static int __init cell_iommu_init(void) |
ae209cf1 | 1040 | { |
165785e5 JK |
1041 | struct device_node *np; |
1042 | ||
165785e5 JK |
1043 | /* If IOMMU is disabled or we have little enough RAM to not need |
1044 | * to enable it, we setup a direct mapping. | |
1045 | * | |
1046 | * Note: should we make sure we have the IOMMU actually disabled ? | |
1047 | */ | |
1048 | if (iommu_is_off || | |
1049 | (!iommu_force_on && lmb_end_of_DRAM() <= 0x80000000ull)) | |
1050 | if (cell_iommu_init_disabled() == 0) | |
1051 | goto bail; | |
1052 | ||
1053 | /* Setup various ppc_md. callbacks */ | |
1054 | ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup; | |
1055 | ppc_md.tce_build = tce_build_cell; | |
1056 | ppc_md.tce_free = tce_free_cell; | |
1057 | ||
99e13912 ME |
1058 | if (!iommu_fixed_disabled && cell_iommu_fixed_mapping_init() == 0) |
1059 | goto bail; | |
1060 | ||
165785e5 JK |
1061 | /* Create an iommu for each /axon node. */ |
1062 | for_each_node_by_name(np, "axon") { | |
1063 | if (np->parent == NULL || np->parent->parent != NULL) | |
1064 | continue; | |
1065 | cell_iommu_init_one(np, 0); | |
49d65b3a | 1066 | } |
ae209cf1 | 1067 | |
165785e5 JK |
1068 | /* Create an iommu for each toplevel /pci-internal node for |
1069 | * old hardware/firmware | |
1070 | */ | |
1071 | for_each_node_by_name(np, "pci-internal") { | |
1072 | if (np->parent == NULL || np->parent->parent != NULL) | |
1073 | continue; | |
1074 | cell_iommu_init_one(np, SPIDER_DMA_OFFSET); | |
1075 | } | |
1076 | ||
1077 | /* Setup default PCI iommu ops */ | |
98747770 | 1078 | set_pci_dma_ops(&dma_iommu_ops); |
165785e5 JK |
1079 | |
1080 | bail: | |
1081 | /* Register callbacks on OF platform device addition/removal | |
1082 | * to handle linking them to the right DMA operations | |
1083 | */ | |
1084 | bus_register_notifier(&of_platform_bus_type, &cell_of_bus_notifier); | |
1085 | ||
1086 | return 0; | |
ae209cf1 | 1087 | } |
e25c47ff GL |
1088 | machine_arch_initcall(cell, cell_iommu_init); |
1089 | machine_arch_initcall(celleb_native, cell_iommu_init); | |
165785e5 | 1090 |