Commit | Line | Data |
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ae209cf1 | 1 | /* |
f3f66f59 | 2 | * IOMMU implementation for Cell Broadband Processor Architecture |
ae209cf1 | 3 | * |
99e13912 | 4 | * (C) Copyright IBM Corporation 2006-2008 |
ae209cf1 | 5 | * |
165785e5 | 6 | * Author: Jeremy Kerr <jk@ozlabs.org> |
ae209cf1 | 7 | * |
165785e5 JK |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
ae209cf1 AB |
21 | */ |
22 | ||
23 | #undef DEBUG | |
24 | ||
25 | #include <linux/kernel.h> | |
ae209cf1 | 26 | #include <linux/init.h> |
165785e5 JK |
27 | #include <linux/interrupt.h> |
28 | #include <linux/notifier.h> | |
ccd05d08 | 29 | #include <linux/of.h> |
d8caf74f | 30 | #include <linux/of_platform.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
95f72d1e | 32 | #include <linux/memblock.h> |
ae209cf1 | 33 | |
ae209cf1 | 34 | #include <asm/prom.h> |
165785e5 | 35 | #include <asm/iommu.h> |
ae209cf1 | 36 | #include <asm/machdep.h> |
165785e5 | 37 | #include <asm/pci-bridge.h> |
49d65b3a | 38 | #include <asm/udbg.h> |
9858ee8a | 39 | #include <asm/firmware.h> |
eef686a0 | 40 | #include <asm/cell-regs.h> |
ae209cf1 | 41 | |
165785e5 | 42 | #include "interrupt.h" |
ae209cf1 | 43 | |
165785e5 JK |
44 | /* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages |
45 | * instead of leaving them mapped to some dummy page. This can be | |
46 | * enabled once the appropriate workarounds for spider bugs have | |
47 | * been enabled | |
48 | */ | |
49 | #define CELL_IOMMU_REAL_UNMAP | |
50 | ||
51 | /* Define CELL_IOMMU_STRICT_PROTECTION to enforce protection of | |
52 | * IO PTEs based on the transfer direction. That can be enabled | |
53 | * once spider-net has been fixed to pass the correct direction | |
54 | * to the DMA mapping functions | |
55 | */ | |
56 | #define CELL_IOMMU_STRICT_PROTECTION | |
57 | ||
58 | ||
59 | #define NR_IOMMUS 2 | |
60 | ||
61 | /* IOC mmap registers */ | |
62 | #define IOC_Reg_Size 0x2000 | |
63 | ||
64 | #define IOC_IOPT_CacheInvd 0x908 | |
65 | #define IOC_IOPT_CacheInvd_NE_Mask 0xffe0000000000000ul | |
66 | #define IOC_IOPT_CacheInvd_IOPTE_Mask 0x000003fffffffff8ul | |
67 | #define IOC_IOPT_CacheInvd_Busy 0x0000000000000001ul | |
68 | ||
69 | #define IOC_IOST_Origin 0x918 | |
70 | #define IOC_IOST_Origin_E 0x8000000000000000ul | |
71 | #define IOC_IOST_Origin_HW 0x0000000000000800ul | |
72 | #define IOC_IOST_Origin_HL 0x0000000000000400ul | |
73 | ||
74 | #define IOC_IO_ExcpStat 0x920 | |
75 | #define IOC_IO_ExcpStat_V 0x8000000000000000ul | |
76 | #define IOC_IO_ExcpStat_SPF_Mask 0x6000000000000000ul | |
77 | #define IOC_IO_ExcpStat_SPF_S 0x6000000000000000ul | |
2a7d55fd | 78 | #define IOC_IO_ExcpStat_SPF_P 0x2000000000000000ul |
165785e5 JK |
79 | #define IOC_IO_ExcpStat_ADDR_Mask 0x00000007fffff000ul |
80 | #define IOC_IO_ExcpStat_RW_Mask 0x0000000000000800ul | |
81 | #define IOC_IO_ExcpStat_IOID_Mask 0x00000000000007fful | |
82 | ||
83 | #define IOC_IO_ExcpMask 0x928 | |
84 | #define IOC_IO_ExcpMask_SFE 0x4000000000000000ul | |
85 | #define IOC_IO_ExcpMask_PFE 0x2000000000000000ul | |
86 | ||
87 | #define IOC_IOCmd_Offset 0x1000 | |
88 | ||
89 | #define IOC_IOCmd_Cfg 0xc00 | |
90 | #define IOC_IOCmd_Cfg_TE 0x0000800000000000ul | |
91 | ||
92 | ||
93 | /* Segment table entries */ | |
94 | #define IOSTE_V 0x8000000000000000ul /* valid */ | |
95 | #define IOSTE_H 0x4000000000000000ul /* cache hint */ | |
96 | #define IOSTE_PT_Base_RPN_Mask 0x3ffffffffffff000ul /* base RPN of IOPT */ | |
97 | #define IOSTE_NPPT_Mask 0x0000000000000fe0ul /* no. pages in IOPT */ | |
98 | #define IOSTE_PS_Mask 0x0000000000000007ul /* page size */ | |
99 | #define IOSTE_PS_4K 0x0000000000000001ul /* - 4kB */ | |
100 | #define IOSTE_PS_64K 0x0000000000000003ul /* - 64kB */ | |
101 | #define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */ | |
102 | #define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */ | |
103 | ||
165785e5 JK |
104 | |
105 | /* IOMMU sizing */ | |
106 | #define IO_SEGMENT_SHIFT 28 | |
225d4905 | 107 | #define IO_PAGENO_BITS(shift) (IO_SEGMENT_SHIFT - (shift)) |
165785e5 JK |
108 | |
109 | /* The high bit needs to be set on every DMA address */ | |
110 | #define SPIDER_DMA_OFFSET 0x80000000ul | |
111 | ||
112 | struct iommu_window { | |
113 | struct list_head list; | |
114 | struct cbe_iommu *iommu; | |
115 | unsigned long offset; | |
116 | unsigned long size; | |
165785e5 JK |
117 | unsigned int ioid; |
118 | struct iommu_table table; | |
119 | }; | |
ae209cf1 | 120 | |
165785e5 JK |
121 | #define NAMESIZE 8 |
122 | struct cbe_iommu { | |
123 | int nid; | |
124 | char name[NAMESIZE]; | |
125 | void __iomem *xlate_regs; | |
126 | void __iomem *cmd_regs; | |
127 | unsigned long *stab; | |
128 | unsigned long *ptab; | |
129 | void *pad_page; | |
130 | struct list_head windows; | |
131 | }; | |
ae209cf1 | 132 | |
165785e5 JK |
133 | /* Static array of iommus, one per node |
134 | * each contains a list of windows, keyed from dma_window property | |
135 | * - on bus setup, look for a matching window, or create one | |
136 | * - on dev setup, assign iommu_table ptr | |
137 | */ | |
138 | static struct cbe_iommu iommus[NR_IOMMUS]; | |
139 | static int cbe_nr_iommus; | |
ae209cf1 | 140 | |
165785e5 JK |
141 | static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte, |
142 | long n_ptes) | |
ae209cf1 | 143 | { |
b36ac9e8 IM |
144 | u64 __iomem *reg; |
145 | u64 val; | |
165785e5 | 146 | long n; |
ae209cf1 | 147 | |
165785e5 | 148 | reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; |
ae209cf1 | 149 | |
165785e5 JK |
150 | while (n_ptes > 0) { |
151 | /* we can invalidate up to 1 << 11 PTEs at once */ | |
152 | n = min(n_ptes, 1l << 11); | |
153 | val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask) | |
154 | | (__pa(pte) & IOC_IOPT_CacheInvd_IOPTE_Mask) | |
155 | | IOC_IOPT_CacheInvd_Busy; | |
ae209cf1 | 156 | |
165785e5 JK |
157 | out_be64(reg, val); |
158 | while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy) | |
159 | ; | |
ae209cf1 | 160 | |
165785e5 JK |
161 | n_ptes -= n; |
162 | pte += n; | |
163 | } | |
ae209cf1 AB |
164 | } |
165 | ||
6490c490 | 166 | static int tce_build_cell(struct iommu_table *tbl, long index, long npages, |
4f3dd8a0 MN |
167 | unsigned long uaddr, enum dma_data_direction direction, |
168 | struct dma_attrs *attrs) | |
ae209cf1 | 169 | { |
165785e5 JK |
170 | int i; |
171 | unsigned long *io_pte, base_pte; | |
172 | struct iommu_window *window = | |
173 | container_of(tbl, struct iommu_window, table); | |
174 | ||
175 | /* implementing proper protection causes problems with the spidernet | |
176 | * driver - check mapping directions later, but allow read & write by | |
177 | * default for now.*/ | |
178 | #ifdef CELL_IOMMU_STRICT_PROTECTION | |
179 | /* to avoid referencing a global, we use a trick here to setup the | |
180 | * protection bit. "prot" is setup to be 3 fields of 4 bits apprended | |
181 | * together for each of the 3 supported direction values. It is then | |
182 | * shifted left so that the fields matching the desired direction | |
183 | * lands on the appropriate bits, and other bits are masked out. | |
184 | */ | |
185 | const unsigned long prot = 0xc48; | |
186 | base_pte = | |
5c6fc8db GU |
187 | ((prot << (52 + 4 * direction)) & |
188 | (CBE_IOPTE_PP_W | CBE_IOPTE_PP_R)) | | |
189 | CBE_IOPTE_M | CBE_IOPTE_SO_RW | | |
190 | (window->ioid & CBE_IOPTE_IOID_Mask); | |
165785e5 | 191 | #else |
5c6fc8db GU |
192 | base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M | |
193 | CBE_IOPTE_SO_RW | (window->ioid & CBE_IOPTE_IOID_Mask); | |
165785e5 | 194 | #endif |
1ed6af73 | 195 | if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))) |
5c6fc8db | 196 | base_pte &= ~CBE_IOPTE_SO_RW; |
165785e5 | 197 | |
0d7386eb | 198 | io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); |
165785e5 JK |
199 | |
200 | for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE) | |
5c6fc8db | 201 | io_pte[i] = base_pte | (__pa(uaddr) & CBE_IOPTE_RPN_Mask); |
165785e5 JK |
202 | |
203 | mb(); | |
204 | ||
205 | invalidate_tce_cache(window->iommu, io_pte, npages); | |
206 | ||
207 | pr_debug("tce_build_cell(index=%lx,n=%lx,dir=%d,base_pte=%lx)\n", | |
208 | index, npages, direction, base_pte); | |
6490c490 | 209 | return 0; |
ae209cf1 AB |
210 | } |
211 | ||
165785e5 | 212 | static void tce_free_cell(struct iommu_table *tbl, long index, long npages) |
ae209cf1 | 213 | { |
ae209cf1 | 214 | |
165785e5 JK |
215 | int i; |
216 | unsigned long *io_pte, pte; | |
217 | struct iommu_window *window = | |
218 | container_of(tbl, struct iommu_window, table); | |
ae209cf1 | 219 | |
165785e5 | 220 | pr_debug("tce_free_cell(index=%lx,n=%lx)\n", index, npages); |
ae209cf1 | 221 | |
165785e5 JK |
222 | #ifdef CELL_IOMMU_REAL_UNMAP |
223 | pte = 0; | |
224 | #else | |
225 | /* spider bridge does PCI reads after freeing - insert a mapping | |
226 | * to a scratch page instead of an invalid entry */ | |
5c6fc8db GU |
227 | pte = CBE_IOPTE_PP_R | CBE_IOPTE_M | CBE_IOPTE_SO_RW | |
228 | __pa(window->iommu->pad_page) | | |
229 | (window->ioid & CBE_IOPTE_IOID_Mask); | |
165785e5 | 230 | #endif |
ae209cf1 | 231 | |
0d7386eb | 232 | io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); |
ae209cf1 | 233 | |
165785e5 JK |
234 | for (i = 0; i < npages; i++) |
235 | io_pte[i] = pte; | |
236 | ||
237 | mb(); | |
ae209cf1 | 238 | |
165785e5 | 239 | invalidate_tce_cache(window->iommu, io_pte, npages); |
ae209cf1 AB |
240 | } |
241 | ||
165785e5 | 242 | static irqreturn_t ioc_interrupt(int irq, void *data) |
ae209cf1 | 243 | { |
2a7d55fd | 244 | unsigned long stat, spf; |
165785e5 JK |
245 | struct cbe_iommu *iommu = data; |
246 | ||
247 | stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); | |
2a7d55fd | 248 | spf = stat & IOC_IO_ExcpStat_SPF_Mask; |
165785e5 JK |
249 | |
250 | /* Might want to rate limit it */ | |
251 | printk(KERN_ERR "iommu: DMA exception 0x%016lx\n", stat); | |
252 | printk(KERN_ERR " V=%d, SPF=[%c%c], RW=%s, IOID=0x%04x\n", | |
253 | !!(stat & IOC_IO_ExcpStat_V), | |
2a7d55fd JK |
254 | (spf == IOC_IO_ExcpStat_SPF_S) ? 'S' : ' ', |
255 | (spf == IOC_IO_ExcpStat_SPF_P) ? 'P' : ' ', | |
165785e5 JK |
256 | (stat & IOC_IO_ExcpStat_RW_Mask) ? "Read" : "Write", |
257 | (unsigned int)(stat & IOC_IO_ExcpStat_IOID_Mask)); | |
258 | printk(KERN_ERR " page=0x%016lx\n", | |
259 | stat & IOC_IO_ExcpStat_ADDR_Mask); | |
260 | ||
261 | /* clear interrupt */ | |
262 | stat &= ~IOC_IO_ExcpStat_V; | |
263 | out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat); | |
264 | ||
265 | return IRQ_HANDLED; | |
ae209cf1 AB |
266 | } |
267 | ||
165785e5 | 268 | static int cell_iommu_find_ioc(int nid, unsigned long *base) |
ae209cf1 | 269 | { |
165785e5 JK |
270 | struct device_node *np; |
271 | struct resource r; | |
272 | ||
273 | *base = 0; | |
274 | ||
275 | /* First look for new style /be nodes */ | |
276 | for_each_node_by_name(np, "ioc") { | |
277 | if (of_node_to_nid(np) != nid) | |
278 | continue; | |
279 | if (of_address_to_resource(np, 0, &r)) { | |
280 | printk(KERN_ERR "iommu: can't get address for %s\n", | |
281 | np->full_name); | |
282 | continue; | |
283 | } | |
284 | *base = r.start; | |
285 | of_node_put(np); | |
286 | return 0; | |
287 | } | |
288 | ||
289 | /* Ok, let's try the old way */ | |
290 | for_each_node_by_type(np, "cpu") { | |
291 | const unsigned int *nidp; | |
292 | const unsigned long *tmp; | |
293 | ||
e2eb6392 | 294 | nidp = of_get_property(np, "node-id", NULL); |
165785e5 | 295 | if (nidp && *nidp == nid) { |
e2eb6392 | 296 | tmp = of_get_property(np, "ioc-translation", NULL); |
165785e5 JK |
297 | if (tmp) { |
298 | *base = *tmp; | |
299 | of_node_put(np); | |
300 | return 0; | |
301 | } | |
302 | } | |
303 | } | |
ae209cf1 | 304 | |
165785e5 | 305 | return -ENODEV; |
ae209cf1 AB |
306 | } |
307 | ||
7d432ff1 | 308 | static void cell_iommu_setup_stab(struct cbe_iommu *iommu, |
41347917 ME |
309 | unsigned long dbase, unsigned long dsize, |
310 | unsigned long fbase, unsigned long fsize) | |
ae209cf1 | 311 | { |
165785e5 | 312 | struct page *page; |
7d432ff1 | 313 | unsigned long segments, stab_size; |
41347917 ME |
314 | |
315 | segments = max(dbase + dsize, fbase + fsize) >> IO_SEGMENT_SHIFT; | |
165785e5 | 316 | |
7d432ff1 | 317 | pr_debug("%s: iommu[%d]: segments: %lu\n", |
e48b1b45 | 318 | __func__, iommu->nid, segments); |
165785e5 JK |
319 | |
320 | /* set up the segment table */ | |
3ca6644e ME |
321 | stab_size = segments * sizeof(unsigned long); |
322 | page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(stab_size)); | |
165785e5 JK |
323 | BUG_ON(!page); |
324 | iommu->stab = page_address(page); | |
7d432ff1 ME |
325 | memset(iommu->stab, 0, stab_size); |
326 | } | |
327 | ||
328 | static unsigned long *cell_iommu_alloc_ptab(struct cbe_iommu *iommu, | |
329 | unsigned long base, unsigned long size, unsigned long gap_base, | |
225d4905 | 330 | unsigned long gap_size, unsigned long page_shift) |
7d432ff1 ME |
331 | { |
332 | struct page *page; | |
333 | int i; | |
334 | unsigned long reg, segments, pages_per_segment, ptab_size, | |
335 | n_pte_pages, start_seg, *ptab; | |
336 | ||
337 | start_seg = base >> IO_SEGMENT_SHIFT; | |
338 | segments = size >> IO_SEGMENT_SHIFT; | |
225d4905 ME |
339 | pages_per_segment = 1ull << IO_PAGENO_BITS(page_shift); |
340 | /* PTEs for each segment must start on a 4K bounday */ | |
341 | pages_per_segment = max(pages_per_segment, | |
342 | (1 << 12) / sizeof(unsigned long)); | |
165785e5 | 343 | |
165785e5 | 344 | ptab_size = segments * pages_per_segment * sizeof(unsigned long); |
e48b1b45 | 345 | pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __func__, |
165785e5 JK |
346 | iommu->nid, ptab_size, get_order(ptab_size)); |
347 | page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size)); | |
348 | BUG_ON(!page); | |
349 | ||
7d432ff1 ME |
350 | ptab = page_address(page); |
351 | memset(ptab, 0, ptab_size); | |
165785e5 | 352 | |
3d3e6da1 ME |
353 | /* number of 4K pages needed for a page table */ |
354 | n_pte_pages = (pages_per_segment * sizeof(unsigned long)) >> 12; | |
165785e5 JK |
355 | |
356 | pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n", | |
e48b1b45 | 357 | __func__, iommu->nid, iommu->stab, ptab, |
165785e5 JK |
358 | n_pte_pages); |
359 | ||
360 | /* initialise the STEs */ | |
361 | reg = IOSTE_V | ((n_pte_pages - 1) << 5); | |
362 | ||
225d4905 ME |
363 | switch (page_shift) { |
364 | case 12: reg |= IOSTE_PS_4K; break; | |
365 | case 16: reg |= IOSTE_PS_64K; break; | |
366 | case 20: reg |= IOSTE_PS_1M; break; | |
367 | case 24: reg |= IOSTE_PS_16M; break; | |
368 | default: BUG(); | |
165785e5 | 369 | } |
ae209cf1 | 370 | |
7d432ff1 ME |
371 | gap_base = gap_base >> IO_SEGMENT_SHIFT; |
372 | gap_size = gap_size >> IO_SEGMENT_SHIFT; | |
373 | ||
165785e5 | 374 | pr_debug("Setting up IOMMU stab:\n"); |
7d432ff1 ME |
375 | for (i = start_seg; i < (start_seg + segments); i++) { |
376 | if (i >= gap_base && i < (gap_base + gap_size)) { | |
377 | pr_debug("\toverlap at %d, skipping\n", i); | |
378 | continue; | |
379 | } | |
3d3e6da1 ME |
380 | iommu->stab[i] = reg | (__pa(ptab) + (n_pte_pages << 12) * |
381 | (i - start_seg)); | |
165785e5 JK |
382 | pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]); |
383 | } | |
7d432ff1 ME |
384 | |
385 | return ptab; | |
7fc67afc ME |
386 | } |
387 | ||
388 | static void cell_iommu_enable_hardware(struct cbe_iommu *iommu) | |
389 | { | |
390 | int ret; | |
391 | unsigned long reg, xlate_base; | |
392 | unsigned int virq; | |
393 | ||
394 | if (cell_iommu_find_ioc(iommu->nid, &xlate_base)) | |
395 | panic("%s: missing IOC register mappings for node %d\n", | |
e48b1b45 | 396 | __func__, iommu->nid); |
7fc67afc ME |
397 | |
398 | iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size); | |
399 | iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset; | |
165785e5 JK |
400 | |
401 | /* ensure that the STEs have updated */ | |
402 | mb(); | |
403 | ||
404 | /* setup interrupts for the iommu. */ | |
405 | reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); | |
406 | out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, | |
407 | reg & ~IOC_IO_ExcpStat_V); | |
408 | out_be64(iommu->xlate_regs + IOC_IO_ExcpMask, | |
409 | IOC_IO_ExcpMask_PFE | IOC_IO_ExcpMask_SFE); | |
410 | ||
411 | virq = irq_create_mapping(NULL, | |
412 | IIC_IRQ_IOEX_ATI | (iommu->nid << IIC_IRQ_NODE_SHIFT)); | |
413 | BUG_ON(virq == NO_IRQ); | |
414 | ||
a3a9f3b4 | 415 | ret = request_irq(virq, ioc_interrupt, 0, iommu->name, iommu); |
165785e5 | 416 | BUG_ON(ret); |
49d65b3a | 417 | |
165785e5 JK |
418 | /* set the IOC segment table origin register (and turn on the iommu) */ |
419 | reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW; | |
420 | out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg); | |
421 | in_be64(iommu->xlate_regs + IOC_IOST_Origin); | |
ae209cf1 | 422 | |
165785e5 JK |
423 | /* turn on IO translation */ |
424 | reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE; | |
425 | out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg); | |
426 | } | |
427 | ||
7fc67afc ME |
428 | static void cell_iommu_setup_hardware(struct cbe_iommu *iommu, |
429 | unsigned long base, unsigned long size) | |
430 | { | |
7d432ff1 | 431 | cell_iommu_setup_stab(iommu, base, size, 0, 0); |
225d4905 ME |
432 | iommu->ptab = cell_iommu_alloc_ptab(iommu, base, size, 0, 0, |
433 | IOMMU_PAGE_SHIFT); | |
7fc67afc ME |
434 | cell_iommu_enable_hardware(iommu); |
435 | } | |
436 | ||
165785e5 JK |
437 | #if 0/* Unused for now */ |
438 | static struct iommu_window *find_window(struct cbe_iommu *iommu, | |
439 | unsigned long offset, unsigned long size) | |
ae209cf1 | 440 | { |
165785e5 | 441 | struct iommu_window *window; |
ae209cf1 | 442 | |
165785e5 JK |
443 | /* todo: check for overlapping (but not equal) windows) */ |
444 | ||
445 | list_for_each_entry(window, &(iommu->windows), list) { | |
446 | if (window->offset == offset && window->size == size) | |
447 | return window; | |
49d65b3a | 448 | } |
165785e5 JK |
449 | |
450 | return NULL; | |
49d65b3a | 451 | } |
165785e5 | 452 | #endif |
ae209cf1 | 453 | |
c96b5126 ME |
454 | static inline u32 cell_iommu_get_ioid(struct device_node *np) |
455 | { | |
456 | const u32 *ioid; | |
457 | ||
458 | ioid = of_get_property(np, "ioid", NULL); | |
459 | if (ioid == NULL) { | |
460 | printk(KERN_WARNING "iommu: missing ioid for %s using 0\n", | |
461 | np->full_name); | |
462 | return 0; | |
463 | } | |
464 | ||
465 | return *ioid; | |
466 | } | |
467 | ||
165785e5 JK |
468 | static struct iommu_window * __init |
469 | cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np, | |
470 | unsigned long offset, unsigned long size, | |
471 | unsigned long pte_offset) | |
49d65b3a | 472 | { |
165785e5 | 473 | struct iommu_window *window; |
edf441fb | 474 | struct page *page; |
c96b5126 | 475 | u32 ioid; |
ae209cf1 | 476 | |
c96b5126 | 477 | ioid = cell_iommu_get_ioid(np); |
165785e5 | 478 | |
7aa241fd | 479 | window = kzalloc_node(sizeof(*window), GFP_KERNEL, iommu->nid); |
165785e5 JK |
480 | BUG_ON(window == NULL); |
481 | ||
482 | window->offset = offset; | |
483 | window->size = size; | |
c96b5126 | 484 | window->ioid = ioid; |
165785e5 | 485 | window->iommu = iommu; |
165785e5 JK |
486 | |
487 | window->table.it_blocksize = 16; | |
488 | window->table.it_base = (unsigned long)iommu->ptab; | |
489 | window->table.it_index = iommu->nid; | |
08e02427 | 490 | window->table.it_offset = (offset >> IOMMU_PAGE_SHIFT) + pte_offset; |
165785e5 JK |
491 | window->table.it_size = size >> IOMMU_PAGE_SHIFT; |
492 | ||
493 | iommu_init_table(&window->table, iommu->nid); | |
494 | ||
495 | pr_debug("\tioid %d\n", window->ioid); | |
496 | pr_debug("\tblocksize %ld\n", window->table.it_blocksize); | |
497 | pr_debug("\tbase 0x%016lx\n", window->table.it_base); | |
498 | pr_debug("\toffset 0x%lx\n", window->table.it_offset); | |
499 | pr_debug("\tsize %ld\n", window->table.it_size); | |
500 | ||
501 | list_add(&window->list, &iommu->windows); | |
502 | ||
503 | if (offset != 0) | |
504 | return window; | |
505 | ||
506 | /* We need to map and reserve the first IOMMU page since it's used | |
507 | * by the spider workaround. In theory, we only need to do that when | |
508 | * running on spider but it doesn't really matter. | |
509 | * | |
510 | * This code also assumes that we have a window that starts at 0, | |
511 | * which is the case on all spider based blades. | |
512 | */ | |
edf441fb ME |
513 | page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0); |
514 | BUG_ON(!page); | |
515 | iommu->pad_page = page_address(page); | |
516 | clear_page(iommu->pad_page); | |
517 | ||
165785e5 JK |
518 | __set_bit(0, window->table.it_map); |
519 | tce_build_cell(&window->table, window->table.it_offset, 1, | |
4f3dd8a0 | 520 | (unsigned long)iommu->pad_page, DMA_TO_DEVICE, NULL); |
165785e5 JK |
521 | window->table.it_hint = window->table.it_blocksize; |
522 | ||
523 | return window; | |
524 | } | |
ae209cf1 | 525 | |
165785e5 JK |
526 | static struct cbe_iommu *cell_iommu_for_node(int nid) |
527 | { | |
528 | int i; | |
49d65b3a | 529 | |
165785e5 JK |
530 | for (i = 0; i < cbe_nr_iommus; i++) |
531 | if (iommus[i].nid == nid) | |
532 | return &iommus[i]; | |
533 | return NULL; | |
534 | } | |
49d65b3a | 535 | |
f5d67bd5 ME |
536 | static unsigned long cell_dma_direct_offset; |
537 | ||
99e13912 | 538 | static unsigned long dma_iommu_fixed_base; |
1ed6af73 MN |
539 | |
540 | /* iommu_fixed_is_weak is set if booted with iommu_fixed=weak */ | |
541 | static int iommu_fixed_is_weak; | |
99e13912 | 542 | |
7e5f8105 | 543 | static struct iommu_table *cell_get_iommu_table(struct device *dev) |
165785e5 JK |
544 | { |
545 | struct iommu_window *window; | |
546 | struct cbe_iommu *iommu; | |
165785e5 | 547 | |
165785e5 JK |
548 | /* Current implementation uses the first window available in that |
549 | * node's iommu. We -might- do something smarter later though it may | |
550 | * never be necessary | |
551 | */ | |
8fae0353 | 552 | iommu = cell_iommu_for_node(dev_to_node(dev)); |
165785e5 JK |
553 | if (iommu == NULL || list_empty(&iommu->windows)) { |
554 | printk(KERN_ERR "iommu: missing iommu for %s (node %d)\n", | |
efd68e72 | 555 | of_node_full_name(dev->of_node), dev_to_node(dev)); |
7e5f8105 | 556 | return NULL; |
165785e5 JK |
557 | } |
558 | window = list_entry(iommu->windows.next, struct iommu_window, list); | |
49d65b3a | 559 | |
7e5f8105 | 560 | return &window->table; |
49d65b3a JO |
561 | } |
562 | ||
1ed6af73 MN |
563 | /* A coherent allocation implies strong ordering */ |
564 | ||
565 | static void *dma_fixed_alloc_coherent(struct device *dev, size_t size, | |
bfbf7d61 AP |
566 | dma_addr_t *dma_handle, gfp_t flag, |
567 | struct dma_attrs *attrs) | |
1ed6af73 MN |
568 | { |
569 | if (iommu_fixed_is_weak) | |
570 | return iommu_alloc_coherent(dev, cell_get_iommu_table(dev), | |
571 | size, dma_handle, | |
572 | device_to_mask(dev), flag, | |
8fae0353 | 573 | dev_to_node(dev)); |
1ed6af73 | 574 | else |
bfbf7d61 AP |
575 | return dma_direct_ops.alloc(dev, size, dma_handle, flag, |
576 | attrs); | |
1ed6af73 MN |
577 | } |
578 | ||
579 | static void dma_fixed_free_coherent(struct device *dev, size_t size, | |
bfbf7d61 AP |
580 | void *vaddr, dma_addr_t dma_handle, |
581 | struct dma_attrs *attrs) | |
1ed6af73 MN |
582 | { |
583 | if (iommu_fixed_is_weak) | |
584 | iommu_free_coherent(cell_get_iommu_table(dev), size, vaddr, | |
585 | dma_handle); | |
586 | else | |
bfbf7d61 | 587 | dma_direct_ops.free(dev, size, vaddr, dma_handle, attrs); |
1ed6af73 MN |
588 | } |
589 | ||
f9226d57 MN |
590 | static dma_addr_t dma_fixed_map_page(struct device *dev, struct page *page, |
591 | unsigned long offset, size_t size, | |
592 | enum dma_data_direction direction, | |
593 | struct dma_attrs *attrs) | |
1ed6af73 MN |
594 | { |
595 | if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) | |
f9226d57 MN |
596 | return dma_direct_ops.map_page(dev, page, offset, size, |
597 | direction, attrs); | |
1ed6af73 | 598 | else |
f9226d57 MN |
599 | return iommu_map_page(dev, cell_get_iommu_table(dev), page, |
600 | offset, size, device_to_mask(dev), | |
601 | direction, attrs); | |
1ed6af73 MN |
602 | } |
603 | ||
f9226d57 MN |
604 | static void dma_fixed_unmap_page(struct device *dev, dma_addr_t dma_addr, |
605 | size_t size, enum dma_data_direction direction, | |
606 | struct dma_attrs *attrs) | |
1ed6af73 MN |
607 | { |
608 | if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) | |
f9226d57 MN |
609 | dma_direct_ops.unmap_page(dev, dma_addr, size, direction, |
610 | attrs); | |
1ed6af73 | 611 | else |
f9226d57 MN |
612 | iommu_unmap_page(cell_get_iommu_table(dev), dma_addr, size, |
613 | direction, attrs); | |
1ed6af73 MN |
614 | } |
615 | ||
616 | static int dma_fixed_map_sg(struct device *dev, struct scatterlist *sg, | |
617 | int nents, enum dma_data_direction direction, | |
618 | struct dma_attrs *attrs) | |
619 | { | |
620 | if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) | |
621 | return dma_direct_ops.map_sg(dev, sg, nents, direction, attrs); | |
622 | else | |
623 | return iommu_map_sg(dev, cell_get_iommu_table(dev), sg, nents, | |
624 | device_to_mask(dev), direction, attrs); | |
625 | } | |
626 | ||
627 | static void dma_fixed_unmap_sg(struct device *dev, struct scatterlist *sg, | |
628 | int nents, enum dma_data_direction direction, | |
629 | struct dma_attrs *attrs) | |
630 | { | |
631 | if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) | |
632 | dma_direct_ops.unmap_sg(dev, sg, nents, direction, attrs); | |
633 | else | |
634 | iommu_unmap_sg(cell_get_iommu_table(dev), sg, nents, direction, | |
635 | attrs); | |
636 | } | |
637 | ||
638 | static int dma_fixed_dma_supported(struct device *dev, u64 mask) | |
639 | { | |
6a35528a | 640 | return mask == DMA_BIT_MASK(64); |
1ed6af73 MN |
641 | } |
642 | ||
643 | static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask); | |
644 | ||
45223c54 | 645 | struct dma_map_ops dma_iommu_fixed_ops = { |
bfbf7d61 AP |
646 | .alloc = dma_fixed_alloc_coherent, |
647 | .free = dma_fixed_free_coherent, | |
1ed6af73 MN |
648 | .map_sg = dma_fixed_map_sg, |
649 | .unmap_sg = dma_fixed_unmap_sg, | |
650 | .dma_supported = dma_fixed_dma_supported, | |
651 | .set_dma_mask = dma_set_mask_and_switch, | |
f9226d57 MN |
652 | .map_page = dma_fixed_map_page, |
653 | .unmap_page = dma_fixed_unmap_page, | |
1ed6af73 MN |
654 | }; |
655 | ||
f9660e8a | 656 | static void cell_dma_dev_setup_fixed(struct device *dev); |
99e13912 | 657 | |
86865771 ME |
658 | static void cell_dma_dev_setup(struct device *dev) |
659 | { | |
99e13912 ME |
660 | /* Order is important here, these are not mutually exclusive */ |
661 | if (get_dma_ops(dev) == &dma_iommu_fixed_ops) | |
f9660e8a | 662 | cell_dma_dev_setup_fixed(dev); |
99e13912 | 663 | else if (get_pci_dma_ops() == &dma_iommu_ops) |
738ef42e | 664 | set_iommu_table_base(dev, cell_get_iommu_table(dev)); |
86865771 | 665 | else if (get_pci_dma_ops() == &dma_direct_ops) |
738ef42e | 666 | set_dma_offset(dev, cell_dma_direct_offset); |
86865771 ME |
667 | else |
668 | BUG(); | |
669 | } | |
670 | ||
165785e5 | 671 | static void cell_pci_dma_dev_setup(struct pci_dev *dev) |
49d65b3a | 672 | { |
165785e5 JK |
673 | cell_dma_dev_setup(&dev->dev); |
674 | } | |
49d65b3a | 675 | |
165785e5 JK |
676 | static int cell_of_bus_notify(struct notifier_block *nb, unsigned long action, |
677 | void *data) | |
678 | { | |
679 | struct device *dev = data; | |
49d65b3a | 680 | |
165785e5 JK |
681 | /* We are only intereted in device addition */ |
682 | if (action != BUS_NOTIFY_ADD_DEVICE) | |
683 | return 0; | |
49d65b3a | 684 | |
165785e5 | 685 | /* We use the PCI DMA ops */ |
57190708 | 686 | dev->archdata.dma_ops = get_pci_dma_ops(); |
49d65b3a | 687 | |
165785e5 | 688 | cell_dma_dev_setup(dev); |
49d65b3a | 689 | |
165785e5 JK |
690 | return 0; |
691 | } | |
49d65b3a | 692 | |
165785e5 JK |
693 | static struct notifier_block cell_of_bus_notifier = { |
694 | .notifier_call = cell_of_bus_notify | |
695 | }; | |
49d65b3a | 696 | |
165785e5 JK |
697 | static int __init cell_iommu_get_window(struct device_node *np, |
698 | unsigned long *base, | |
699 | unsigned long *size) | |
700 | { | |
701 | const void *dma_window; | |
702 | unsigned long index; | |
49d65b3a | 703 | |
165785e5 | 704 | /* Use ibm,dma-window if available, else, hard code ! */ |
e2eb6392 | 705 | dma_window = of_get_property(np, "ibm,dma-window", NULL); |
165785e5 JK |
706 | if (dma_window == NULL) { |
707 | *base = 0; | |
708 | *size = 0x80000000u; | |
709 | return -ENODEV; | |
710 | } | |
49d65b3a | 711 | |
165785e5 | 712 | of_parse_dma_window(np, dma_window, &index, base, size); |
49d65b3a | 713 | return 0; |
ae209cf1 AB |
714 | } |
715 | ||
209bfbb4 | 716 | static struct cbe_iommu * __init cell_iommu_alloc(struct device_node *np) |
49d65b3a | 717 | { |
165785e5 | 718 | struct cbe_iommu *iommu; |
165785e5 JK |
719 | int nid, i; |
720 | ||
721 | /* Get node ID */ | |
722 | nid = of_node_to_nid(np); | |
723 | if (nid < 0) { | |
724 | printk(KERN_ERR "iommu: failed to get node for %s\n", | |
725 | np->full_name); | |
209bfbb4 | 726 | return NULL; |
165785e5 JK |
727 | } |
728 | pr_debug("iommu: setting up iommu for node %d (%s)\n", | |
729 | nid, np->full_name); | |
730 | ||
731 | /* XXX todo: If we can have multiple windows on the same IOMMU, which | |
732 | * isn't the case today, we probably want here to check wether the | |
733 | * iommu for that node is already setup. | |
734 | * However, there might be issue with getting the size right so let's | |
735 | * ignore that for now. We might want to completely get rid of the | |
736 | * multiple window support since the cell iommu supports per-page ioids | |
737 | */ | |
738 | ||
739 | if (cbe_nr_iommus >= NR_IOMMUS) { | |
740 | printk(KERN_ERR "iommu: too many IOMMUs detected ! (%s)\n", | |
741 | np->full_name); | |
209bfbb4 | 742 | return NULL; |
165785e5 JK |
743 | } |
744 | ||
745 | /* Init base fields */ | |
746 | i = cbe_nr_iommus++; | |
747 | iommu = &iommus[i]; | |
9340b0d3 | 748 | iommu->stab = NULL; |
165785e5 JK |
749 | iommu->nid = nid; |
750 | snprintf(iommu->name, sizeof(iommu->name), "iommu%d", i); | |
751 | INIT_LIST_HEAD(&iommu->windows); | |
49d65b3a | 752 | |
209bfbb4 ME |
753 | return iommu; |
754 | } | |
755 | ||
756 | static void __init cell_iommu_init_one(struct device_node *np, | |
757 | unsigned long offset) | |
758 | { | |
759 | struct cbe_iommu *iommu; | |
760 | unsigned long base, size; | |
761 | ||
762 | iommu = cell_iommu_alloc(np); | |
763 | if (!iommu) | |
764 | return; | |
765 | ||
165785e5 JK |
766 | /* Obtain a window for it */ |
767 | cell_iommu_get_window(np, &base, &size); | |
49d65b3a | 768 | |
165785e5 JK |
769 | pr_debug("\ttranslating window 0x%lx...0x%lx\n", |
770 | base, base + size - 1); | |
49d65b3a | 771 | |
165785e5 | 772 | /* Initialize the hardware */ |
7fc67afc | 773 | cell_iommu_setup_hardware(iommu, base, size); |
49d65b3a | 774 | |
165785e5 JK |
775 | /* Setup the iommu_table */ |
776 | cell_iommu_setup_window(iommu, np, base, size, | |
777 | offset >> IOMMU_PAGE_SHIFT); | |
778 | } | |
49d65b3a | 779 | |
165785e5 JK |
780 | static void __init cell_disable_iommus(void) |
781 | { | |
782 | int node; | |
783 | unsigned long base, val; | |
784 | void __iomem *xregs, *cregs; | |
785 | ||
786 | /* Make sure IOC translation is disabled on all nodes */ | |
787 | for_each_online_node(node) { | |
788 | if (cell_iommu_find_ioc(node, &base)) | |
789 | continue; | |
790 | xregs = ioremap(base, IOC_Reg_Size); | |
791 | if (xregs == NULL) | |
792 | continue; | |
793 | cregs = xregs + IOC_IOCmd_Offset; | |
794 | ||
795 | pr_debug("iommu: cleaning up iommu on node %d\n", node); | |
796 | ||
797 | out_be64(xregs + IOC_IOST_Origin, 0); | |
798 | (void)in_be64(xregs + IOC_IOST_Origin); | |
799 | val = in_be64(cregs + IOC_IOCmd_Cfg); | |
800 | val &= ~IOC_IOCmd_Cfg_TE; | |
801 | out_be64(cregs + IOC_IOCmd_Cfg, val); | |
802 | (void)in_be64(cregs + IOC_IOCmd_Cfg); | |
803 | ||
804 | iounmap(xregs); | |
805 | } | |
806 | } | |
49d65b3a | 807 | |
165785e5 JK |
808 | static int __init cell_iommu_init_disabled(void) |
809 | { | |
810 | struct device_node *np = NULL; | |
811 | unsigned long base = 0, size; | |
49d65b3a | 812 | |
165785e5 | 813 | /* When no iommu is present, we use direct DMA ops */ |
98747770 | 814 | set_pci_dma_ops(&dma_direct_ops); |
49d65b3a | 815 | |
165785e5 JK |
816 | /* First make sure all IOC translation is turned off */ |
817 | cell_disable_iommus(); | |
818 | ||
819 | /* If we have no Axon, we set up the spider DMA magic offset */ | |
820 | if (of_find_node_by_name(NULL, "axon") == NULL) | |
f5d67bd5 | 821 | cell_dma_direct_offset = SPIDER_DMA_OFFSET; |
165785e5 JK |
822 | |
823 | /* Now we need to check to see where the memory is mapped | |
824 | * in PCI space. We assume that all busses use the same dma | |
825 | * window which is always the case so far on Cell, thus we | |
826 | * pick up the first pci-internal node we can find and check | |
827 | * the DMA window from there. | |
828 | */ | |
829 | for_each_node_by_name(np, "axon") { | |
830 | if (np->parent == NULL || np->parent->parent != NULL) | |
831 | continue; | |
832 | if (cell_iommu_get_window(np, &base, &size) == 0) | |
833 | break; | |
834 | } | |
835 | if (np == NULL) { | |
836 | for_each_node_by_name(np, "pci-internal") { | |
837 | if (np->parent == NULL || np->parent->parent != NULL) | |
838 | continue; | |
839 | if (cell_iommu_get_window(np, &base, &size) == 0) | |
840 | break; | |
841 | } | |
842 | } | |
843 | of_node_put(np); | |
844 | ||
845 | /* If we found a DMA window, we check if it's big enough to enclose | |
846 | * all of physical memory. If not, we force enable IOMMU | |
847 | */ | |
95f72d1e | 848 | if (np && size < memblock_end_of_DRAM()) { |
165785e5 | 849 | printk(KERN_WARNING "iommu: force-enabled, dma window" |
fe333321 | 850 | " (%ldMB) smaller than total memory (%lldMB)\n", |
95f72d1e | 851 | size >> 20, memblock_end_of_DRAM() >> 20); |
165785e5 | 852 | return -ENODEV; |
49d65b3a JO |
853 | } |
854 | ||
f5d67bd5 | 855 | cell_dma_direct_offset += base; |
165785e5 | 856 | |
f5d67bd5 | 857 | if (cell_dma_direct_offset != 0) |
110f95c9 ME |
858 | ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup; |
859 | ||
165785e5 | 860 | printk("iommu: disabled, direct DMA offset is 0x%lx\n", |
f5d67bd5 | 861 | cell_dma_direct_offset); |
165785e5 JK |
862 | |
863 | return 0; | |
49d65b3a JO |
864 | } |
865 | ||
99e13912 ME |
866 | /* |
867 | * Fixed IOMMU mapping support | |
868 | * | |
869 | * This code adds support for setting up a fixed IOMMU mapping on certain | |
870 | * cell machines. For 64-bit devices this avoids the performance overhead of | |
871 | * mapping and unmapping pages at runtime. 32-bit devices are unable to use | |
872 | * the fixed mapping. | |
873 | * | |
874 | * The fixed mapping is established at boot, and maps all of physical memory | |
875 | * 1:1 into device space at some offset. On machines with < 30 GB of memory | |
876 | * we setup the fixed mapping immediately above the normal IOMMU window. | |
877 | * | |
878 | * For example a machine with 4GB of memory would end up with the normal | |
879 | * IOMMU window from 0-2GB and the fixed mapping window from 2GB to 6GB. In | |
880 | * this case a 64-bit device wishing to DMA to 1GB would be told to DMA to | |
881 | * 3GB, plus any offset required by firmware. The firmware offset is encoded | |
882 | * in the "dma-ranges" property. | |
883 | * | |
884 | * On machines with 30GB or more of memory, we are unable to place the fixed | |
885 | * mapping above the normal IOMMU window as we would run out of address space. | |
886 | * Instead we move the normal IOMMU window to coincide with the hash page | |
887 | * table, this region does not need to be part of the fixed mapping as no | |
888 | * device should ever be DMA'ing to it. We then setup the fixed mapping | |
889 | * from 0 to 32GB. | |
890 | */ | |
891 | ||
892 | static u64 cell_iommu_get_fixed_address(struct device *dev) | |
893 | { | |
3a4295d1 | 894 | u64 cpu_addr, size, best_size, dev_addr = OF_BAD_ADDR; |
ccd05d08 | 895 | struct device_node *np; |
99e13912 | 896 | const u32 *ranges = NULL; |
3a4295d1 | 897 | int i, len, best, naddr, nsize, pna, range_size; |
99e13912 | 898 | |
58f9b0b0 | 899 | np = of_node_get(dev->of_node); |
3a4295d1 ME |
900 | while (1) { |
901 | naddr = of_n_addr_cells(np); | |
902 | nsize = of_n_size_cells(np); | |
903 | np = of_get_next_parent(np); | |
904 | if (!np) | |
905 | break; | |
906 | ||
99e13912 | 907 | ranges = of_get_property(np, "dma-ranges", &len); |
3a4295d1 ME |
908 | |
909 | /* Ignore empty ranges, they imply no translation required */ | |
910 | if (ranges && len > 0) | |
ccd05d08 | 911 | break; |
99e13912 ME |
912 | } |
913 | ||
914 | if (!ranges) { | |
915 | dev_dbg(dev, "iommu: no dma-ranges found\n"); | |
916 | goto out; | |
917 | } | |
918 | ||
919 | len /= sizeof(u32); | |
920 | ||
3a4295d1 ME |
921 | pna = of_n_addr_cells(np); |
922 | range_size = naddr + nsize + pna; | |
923 | ||
99e13912 | 924 | /* dma-ranges format: |
3a4295d1 ME |
925 | * child addr : naddr cells |
926 | * parent addr : pna cells | |
927 | * size : nsize cells | |
99e13912 | 928 | */ |
3a4295d1 ME |
929 | for (i = 0, best = -1, best_size = 0; i < len; i += range_size) { |
930 | cpu_addr = of_translate_dma_address(np, ranges + i + naddr); | |
931 | size = of_read_number(ranges + i + naddr + pna, nsize); | |
99e13912 ME |
932 | |
933 | if (cpu_addr == 0 && size > best_size) { | |
934 | best = i; | |
935 | best_size = size; | |
936 | } | |
937 | } | |
938 | ||
3a4295d1 ME |
939 | if (best >= 0) { |
940 | dev_addr = of_read_number(ranges + best, naddr); | |
941 | } else | |
99e13912 ME |
942 | dev_dbg(dev, "iommu: no suitable range found!\n"); |
943 | ||
944 | out: | |
945 | of_node_put(np); | |
946 | ||
3a4295d1 | 947 | return dev_addr; |
99e13912 ME |
948 | } |
949 | ||
950 | static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask) | |
951 | { | |
952 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
953 | return -EIO; | |
954 | ||
4a8df150 ME |
955 | if (dma_mask == DMA_BIT_MASK(64) && |
956 | cell_iommu_get_fixed_address(dev) != OF_BAD_ADDR) | |
957 | { | |
958 | dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n"); | |
959 | set_dma_ops(dev, &dma_iommu_fixed_ops); | |
99e13912 ME |
960 | } else { |
961 | dev_dbg(dev, "iommu: not 64-bit, using default ops\n"); | |
962 | set_dma_ops(dev, get_pci_dma_ops()); | |
963 | } | |
964 | ||
4a8df150 ME |
965 | cell_dma_dev_setup(dev); |
966 | ||
99e13912 ME |
967 | *dev->dma_mask = dma_mask; |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
f9660e8a | 972 | static void cell_dma_dev_setup_fixed(struct device *dev) |
99e13912 | 973 | { |
99e13912 ME |
974 | u64 addr; |
975 | ||
976 | addr = cell_iommu_get_fixed_address(dev) + dma_iommu_fixed_base; | |
738ef42e | 977 | set_dma_offset(dev, addr); |
99e13912 | 978 | |
fe333321 | 979 | dev_dbg(dev, "iommu: fixed addr = %llx\n", addr); |
99e13912 ME |
980 | } |
981 | ||
da40451b ME |
982 | static void insert_16M_pte(unsigned long addr, unsigned long *ptab, |
983 | unsigned long base_pte) | |
984 | { | |
985 | unsigned long segment, offset; | |
986 | ||
987 | segment = addr >> IO_SEGMENT_SHIFT; | |
988 | offset = (addr >> 24) - (segment << IO_PAGENO_BITS(24)); | |
989 | ptab = ptab + (segment * (1 << 12) / sizeof(unsigned long)); | |
990 | ||
991 | pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n", | |
992 | addr, ptab, segment, offset); | |
993 | ||
5c6fc8db | 994 | ptab[offset] = base_pte | (__pa(addr) & CBE_IOPTE_RPN_Mask); |
da40451b ME |
995 | } |
996 | ||
99e13912 ME |
997 | static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu, |
998 | struct device_node *np, unsigned long dbase, unsigned long dsize, | |
999 | unsigned long fbase, unsigned long fsize) | |
1000 | { | |
da40451b | 1001 | unsigned long base_pte, uaddr, ioaddr, *ptab; |
99e13912 | 1002 | |
da40451b | 1003 | ptab = cell_iommu_alloc_ptab(iommu, fbase, fsize, dbase, dsize, 24); |
99e13912 | 1004 | |
99e13912 | 1005 | dma_iommu_fixed_base = fbase; |
99e13912 ME |
1006 | |
1007 | pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase); | |
1008 | ||
5c6fc8db GU |
1009 | base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M | |
1010 | (cell_iommu_get_ioid(np) & CBE_IOPTE_IOID_Mask); | |
99e13912 | 1011 | |
1ed6af73 MN |
1012 | if (iommu_fixed_is_weak) |
1013 | pr_info("IOMMU: Using weak ordering for fixed mapping\n"); | |
1014 | else { | |
1015 | pr_info("IOMMU: Using strong ordering for fixed mapping\n"); | |
5c6fc8db | 1016 | base_pte |= CBE_IOPTE_SO_RW; |
1ed6af73 MN |
1017 | } |
1018 | ||
da40451b | 1019 | for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) { |
99e13912 | 1020 | /* Don't touch the dynamic region */ |
da40451b ME |
1021 | ioaddr = uaddr + fbase; |
1022 | if (ioaddr >= dbase && ioaddr < (dbase + dsize)) { | |
f9660e8a | 1023 | pr_debug("iommu: fixed/dynamic overlap, skipping\n"); |
99e13912 ME |
1024 | continue; |
1025 | } | |
da40451b ME |
1026 | |
1027 | insert_16M_pte(uaddr, ptab, base_pte); | |
99e13912 ME |
1028 | } |
1029 | ||
1030 | mb(); | |
1031 | } | |
1032 | ||
1033 | static int __init cell_iommu_fixed_mapping_init(void) | |
1034 | { | |
1035 | unsigned long dbase, dsize, fbase, fsize, hbase, hend; | |
1036 | struct cbe_iommu *iommu; | |
1037 | struct device_node *np; | |
1038 | ||
1039 | /* The fixed mapping is only supported on axon machines */ | |
1040 | np = of_find_node_by_name(NULL, "axon"); | |
dbfc189c JL |
1041 | of_node_put(np); |
1042 | ||
99e13912 ME |
1043 | if (!np) { |
1044 | pr_debug("iommu: fixed mapping disabled, no axons found\n"); | |
1045 | return -1; | |
1046 | } | |
1047 | ||
0e0b47ab | 1048 | /* We must have dma-ranges properties for fixed mapping to work */ |
ba82efbd | 1049 | np = of_find_node_with_property(NULL, "dma-ranges"); |
0e0b47ab ME |
1050 | of_node_put(np); |
1051 | ||
1052 | if (!np) { | |
1053 | pr_debug("iommu: no dma-ranges found, no fixed mapping\n"); | |
1054 | return -1; | |
1055 | } | |
1056 | ||
99e13912 ME |
1057 | /* The default setup is to have the fixed mapping sit after the |
1058 | * dynamic region, so find the top of the largest IOMMU window | |
1059 | * on any axon, then add the size of RAM and that's our max value. | |
1060 | * If that is > 32GB we have to do other shennanigans. | |
1061 | */ | |
1062 | fbase = 0; | |
1063 | for_each_node_by_name(np, "axon") { | |
1064 | cell_iommu_get_window(np, &dbase, &dsize); | |
1065 | fbase = max(fbase, dbase + dsize); | |
1066 | } | |
1067 | ||
1068 | fbase = _ALIGN_UP(fbase, 1 << IO_SEGMENT_SHIFT); | |
95f72d1e | 1069 | fsize = memblock_phys_mem_size(); |
99e13912 | 1070 | |
257d5698 | 1071 | if ((fbase + fsize) <= 0x800000000ul) |
99e13912 ME |
1072 | hbase = 0; /* use the device tree window */ |
1073 | else { | |
1074 | /* If we're over 32 GB we need to cheat. We can't map all of | |
1075 | * RAM with the fixed mapping, and also fit the dynamic | |
1076 | * region. So try to place the dynamic region where the hash | |
1077 | * table sits, drivers never need to DMA to it, we don't | |
1078 | * need a fixed mapping for that area. | |
1079 | */ | |
1080 | if (!htab_address) { | |
1081 | pr_debug("iommu: htab is NULL, on LPAR? Huh?\n"); | |
1082 | return -1; | |
1083 | } | |
1084 | hbase = __pa(htab_address); | |
1085 | hend = hbase + htab_size_bytes; | |
1086 | ||
1087 | /* The window must start and end on a segment boundary */ | |
1088 | if ((hbase != _ALIGN_UP(hbase, 1 << IO_SEGMENT_SHIFT)) || | |
1089 | (hend != _ALIGN_UP(hend, 1 << IO_SEGMENT_SHIFT))) { | |
1090 | pr_debug("iommu: hash window not segment aligned\n"); | |
1091 | return -1; | |
1092 | } | |
1093 | ||
1094 | /* Check the hash window fits inside the real DMA window */ | |
1095 | for_each_node_by_name(np, "axon") { | |
1096 | cell_iommu_get_window(np, &dbase, &dsize); | |
1097 | ||
1098 | if (hbase < dbase || (hend > (dbase + dsize))) { | |
1099 | pr_debug("iommu: hash window doesn't fit in" | |
1100 | "real DMA window\n"); | |
1101 | return -1; | |
1102 | } | |
1103 | } | |
1104 | ||
1105 | fbase = 0; | |
1106 | } | |
1107 | ||
1108 | /* Setup the dynamic regions */ | |
1109 | for_each_node_by_name(np, "axon") { | |
1110 | iommu = cell_iommu_alloc(np); | |
1111 | BUG_ON(!iommu); | |
1112 | ||
1113 | if (hbase == 0) | |
1114 | cell_iommu_get_window(np, &dbase, &dsize); | |
1115 | else { | |
1116 | dbase = hbase; | |
1117 | dsize = htab_size_bytes; | |
1118 | } | |
1119 | ||
44621be4 ME |
1120 | printk(KERN_DEBUG "iommu: node %d, dynamic window 0x%lx-0x%lx " |
1121 | "fixed window 0x%lx-0x%lx\n", iommu->nid, dbase, | |
99e13912 ME |
1122 | dbase + dsize, fbase, fbase + fsize); |
1123 | ||
7d432ff1 | 1124 | cell_iommu_setup_stab(iommu, dbase, dsize, fbase, fsize); |
225d4905 ME |
1125 | iommu->ptab = cell_iommu_alloc_ptab(iommu, dbase, dsize, 0, 0, |
1126 | IOMMU_PAGE_SHIFT); | |
99e13912 ME |
1127 | cell_iommu_setup_fixed_ptab(iommu, np, dbase, dsize, |
1128 | fbase, fsize); | |
1129 | cell_iommu_enable_hardware(iommu); | |
1130 | cell_iommu_setup_window(iommu, np, dbase, dsize, 0); | |
1131 | } | |
1132 | ||
99e13912 ME |
1133 | dma_iommu_ops.set_dma_mask = dma_set_mask_and_switch; |
1134 | set_pci_dma_ops(&dma_iommu_ops); | |
1135 | ||
99e13912 ME |
1136 | return 0; |
1137 | } | |
1138 | ||
1139 | static int iommu_fixed_disabled; | |
1140 | ||
1141 | static int __init setup_iommu_fixed(char *str) | |
1142 | { | |
7886250e MN |
1143 | struct device_node *pciep; |
1144 | ||
99e13912 ME |
1145 | if (strcmp(str, "off") == 0) |
1146 | iommu_fixed_disabled = 1; | |
1147 | ||
7886250e MN |
1148 | /* If we can find a pcie-endpoint in the device tree assume that |
1149 | * we're on a triblade or a CAB so by default the fixed mapping | |
1150 | * should be set to be weakly ordered; but only if the boot | |
1151 | * option WASN'T set for strong ordering | |
1152 | */ | |
1153 | pciep = of_find_node_by_type(NULL, "pcie-endpoint"); | |
1154 | ||
1155 | if (strcmp(str, "weak") == 0 || (pciep && strcmp(str, "strong") != 0)) | |
1ed6af73 MN |
1156 | iommu_fixed_is_weak = 1; |
1157 | ||
7886250e MN |
1158 | of_node_put(pciep); |
1159 | ||
99e13912 ME |
1160 | return 1; |
1161 | } | |
1162 | __setup("iommu_fixed=", setup_iommu_fixed); | |
1163 | ||
6a5c7be5 MM |
1164 | static u64 cell_dma_get_required_mask(struct device *dev) |
1165 | { | |
d24f9c69 MM |
1166 | struct dma_map_ops *dma_ops; |
1167 | ||
6a5c7be5 MM |
1168 | if (!dev->dma_mask) |
1169 | return 0; | |
1170 | ||
d24f9c69 MM |
1171 | if (!iommu_fixed_disabled && |
1172 | cell_iommu_get_fixed_address(dev) != OF_BAD_ADDR) | |
1173 | return DMA_BIT_MASK(64); | |
1174 | ||
1175 | dma_ops = get_dma_ops(dev); | |
1176 | if (dma_ops->get_required_mask) | |
1177 | return dma_ops->get_required_mask(dev); | |
1178 | ||
1179 | WARN_ONCE(1, "no get_required_mask in %p ops", dma_ops); | |
6a5c7be5 MM |
1180 | |
1181 | return DMA_BIT_MASK(64); | |
1182 | } | |
1183 | ||
165785e5 | 1184 | static int __init cell_iommu_init(void) |
ae209cf1 | 1185 | { |
165785e5 JK |
1186 | struct device_node *np; |
1187 | ||
165785e5 JK |
1188 | /* If IOMMU is disabled or we have little enough RAM to not need |
1189 | * to enable it, we setup a direct mapping. | |
1190 | * | |
1191 | * Note: should we make sure we have the IOMMU actually disabled ? | |
1192 | */ | |
1193 | if (iommu_is_off || | |
95f72d1e | 1194 | (!iommu_force_on && memblock_end_of_DRAM() <= 0x80000000ull)) |
165785e5 JK |
1195 | if (cell_iommu_init_disabled() == 0) |
1196 | goto bail; | |
1197 | ||
1198 | /* Setup various ppc_md. callbacks */ | |
1199 | ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup; | |
6a5c7be5 | 1200 | ppc_md.dma_get_required_mask = cell_dma_get_required_mask; |
165785e5 JK |
1201 | ppc_md.tce_build = tce_build_cell; |
1202 | ppc_md.tce_free = tce_free_cell; | |
1203 | ||
99e13912 ME |
1204 | if (!iommu_fixed_disabled && cell_iommu_fixed_mapping_init() == 0) |
1205 | goto bail; | |
1206 | ||
165785e5 JK |
1207 | /* Create an iommu for each /axon node. */ |
1208 | for_each_node_by_name(np, "axon") { | |
1209 | if (np->parent == NULL || np->parent->parent != NULL) | |
1210 | continue; | |
1211 | cell_iommu_init_one(np, 0); | |
49d65b3a | 1212 | } |
ae209cf1 | 1213 | |
165785e5 JK |
1214 | /* Create an iommu for each toplevel /pci-internal node for |
1215 | * old hardware/firmware | |
1216 | */ | |
1217 | for_each_node_by_name(np, "pci-internal") { | |
1218 | if (np->parent == NULL || np->parent->parent != NULL) | |
1219 | continue; | |
1220 | cell_iommu_init_one(np, SPIDER_DMA_OFFSET); | |
1221 | } | |
1222 | ||
1223 | /* Setup default PCI iommu ops */ | |
98747770 | 1224 | set_pci_dma_ops(&dma_iommu_ops); |
165785e5 JK |
1225 | |
1226 | bail: | |
1227 | /* Register callbacks on OF platform device addition/removal | |
1228 | * to handle linking them to the right DMA operations | |
1229 | */ | |
eca39301 | 1230 | bus_register_notifier(&platform_bus_type, &cell_of_bus_notifier); |
165785e5 JK |
1231 | |
1232 | return 0; | |
ae209cf1 | 1233 | } |
e25c47ff GL |
1234 | machine_arch_initcall(cell, cell_iommu_init); |
1235 | machine_arch_initcall(celleb_native, cell_iommu_init); | |
165785e5 | 1236 |