[deliverable/linux.git] / arch / powerpc / platforms / cell / spu_base.c

/*
 * Low-level SPU handling
 *
 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
 *
 * Author: Arnd Bergmann <arndb@de.ibm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#undef DEBUG

#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/poll.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/wait.h>

#include <asm/io.h>
#include <asm/prom.h>
#include <linux/mutex.h>
#include <asm/spu.h>
#include <asm/mmu_context.h>

#include "interrupt.h"

static int __spu_trap_invalid_dma(struct spu *spu)
{
	pr_debug("%s\n", __FUNCTION__);
	force_sig(SIGBUS, /* info, */ current);
	return 0;
}

static int __spu_trap_dma_align(struct spu *spu)
{
	pr_debug("%s\n", __FUNCTION__);
	force_sig(SIGBUS, /* info, */ current);
	return 0;
}

static int __spu_trap_error(struct spu *spu)
{
	pr_debug("%s\n", __FUNCTION__);
	force_sig(SIGILL, /* info, */ current);
	return 0;
}

static void spu_restart_dma(struct spu *spu)
{
	struct spu_priv2 __iomem *priv2 = spu->priv2;

	if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))
		out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
}

static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
{
	struct spu_priv2 __iomem *priv2 = spu->priv2;
	struct mm_struct *mm = spu->mm;
	u64 esid, vsid;

	pr_debug("%s\n", __FUNCTION__);

	if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
		/* SLBs are pre-loaded for context switch, so
		 * we should never get here!
		 */
		printk("%s: invalid access during switch!\n", __func__);
		return 1;
	}
	if (!mm || (REGION_ID(ea) != USER_REGION_ID)) {
		/* Future: support kernel segments so that drivers
		 * can use SPUs.
		 */
		pr_debug("invalid region access at %016lx\n", ea);
		return 1;
	}

	esid = (ea & ESID_MASK) | SLB_ESID_V;
	vsid = (get_vsid(mm->context.id, ea) << SLB_VSID_SHIFT) | SLB_VSID_USER;
	if (in_hugepage_area(mm->context, ea))
		vsid |= SLB_VSID_L;

	out_be64(&priv2->slb_index_W, spu->slb_replace);
	out_be64(&priv2->slb_vsid_RW, vsid);
	out_be64(&priv2->slb_esid_RW, esid);

	spu->slb_replace++;
	if (spu->slb_replace >= 8)
		spu->slb_replace = 0;

	spu_restart_dma(spu);

	return 0;
}

extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX
static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
{
	pr_debug("%s, %lx, %lx\n", __FUNCTION__, dsisr, ea);

	/* Handle kernel space hash faults immediately.
	   User hash faults need to be deferred to process context. */
	if ((dsisr & MFC_DSISR_PTE_NOT_FOUND)
	    && REGION_ID(ea) != USER_REGION_ID
	    && hash_page(ea, _PAGE_PRESENT, 0x300) == 0) {
		spu_restart_dma(spu);
		return 0;
	}

	if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
		printk("%s: invalid access during switch!\n", __func__);
		return 1;
	}

	spu->dar = ea;
	spu->dsisr = dsisr;
	mb();
	if (spu->stop_callback)
		spu->stop_callback(spu);
	return 0;
}

static int __spu_trap_mailbox(struct spu *spu)
{
	if (spu->ibox_callback)
		spu->ibox_callback(spu);

	/* atomically disable SPU mailbox interrupts */
	spin_lock(&spu->register_lock);
	spu_int_mask_and(spu, 2, ~0x1);
	spin_unlock(&spu->register_lock);
	return 0;
}

static int __spu_trap_stop(struct spu *spu)
{
	pr_debug("%s\n", __FUNCTION__);
	spu->stop_code = in_be32(&spu->problem->spu_status_R);
	if (spu->stop_callback)
		spu->stop_callback(spu);
	return 0;
}

static int __spu_trap_halt(struct spu *spu)
{
	pr_debug("%s\n", __FUNCTION__);
	spu->stop_code = in_be32(&spu->problem->spu_status_R);
	if (spu->stop_callback)
		spu->stop_callback(spu);
	return 0;
}

static int __spu_trap_tag_group(struct spu *spu)
{
	pr_debug("%s\n", __FUNCTION__);
	spu->mfc_callback(spu);
	return 0;
}

static int __spu_trap_spubox(struct spu *spu)
{
	if (spu->wbox_callback)
		spu->wbox_callback(spu);

	/* atomically disable SPU mailbox interrupts */
	spin_lock(&spu->register_lock);
	spu_int_mask_and(spu, 2, ~0x10);
	spin_unlock(&spu->register_lock);
	return 0;
}

static irqreturn_t
spu_irq_class_0(int irq, void *data, struct pt_regs *regs)
{
	struct spu *spu;

	spu = data;
	spu->class_0_pending = 1;
	if (spu->stop_callback)
		spu->stop_callback(spu);

	return IRQ_HANDLED;
}

int
spu_irq_class_0_bottom(struct spu *spu)
{
	unsigned long stat, mask;

	spu->class_0_pending = 0;

	mask = spu_int_mask_get(spu, 0);
	stat = spu_int_stat_get(spu, 0);

	stat &= mask;

	if (stat & 1) /* invalid MFC DMA */
		__spu_trap_invalid_dma(spu);

	if (stat & 2) /* invalid DMA alignment */
		__spu_trap_dma_align(spu);

	if (stat & 4) /* error on SPU */
		__spu_trap_error(spu);

	spu_int_stat_clear(spu, 0, stat);

	return (stat & 0x7) ? -EIO : 0;
}
EXPORT_SYMBOL_GPL(spu_irq_class_0_bottom);

static irqreturn_t
spu_irq_class_1(int irq, void *data, struct pt_regs *regs)
{
	struct spu *spu;
	unsigned long stat, mask, dar, dsisr;

	spu = data;

	/* atomically read & clear class1 status. */
	spin_lock(&spu->register_lock);
	mask  = spu_int_mask_get(spu, 1);
	stat  = spu_int_stat_get(spu, 1) & mask;
	dar   = spu_mfc_dar_get(spu);
	dsisr = spu_mfc_dsisr_get(spu);
	if (stat & 2) /* mapping fault */
		spu_mfc_dsisr_set(spu, 0ul);
	spu_int_stat_clear(spu, 1, stat);
	spin_unlock(&spu->register_lock);
	pr_debug("%s: %lx %lx %lx %lx\n", __FUNCTION__, mask, stat,
			dar, dsisr);

	if (stat & 1) /* segment fault */
		__spu_trap_data_seg(spu, dar);

	if (stat & 2) { /* mapping fault */
		__spu_trap_data_map(spu, dar, dsisr);
	}

	if (stat & 4) /* ls compare & suspend on get */
		;

	if (stat & 8) /* ls compare & suspend on put */
		;

	return stat ? IRQ_HANDLED : IRQ_NONE;
}
EXPORT_SYMBOL_GPL(spu_irq_class_1_bottom);

static irqreturn_t
spu_irq_class_2(int irq, void *data, struct pt_regs *regs)
{
	struct spu *spu;
	unsigned long stat;
	unsigned long mask;

	spu = data;
	stat = spu_int_stat_get(spu, 2);
	mask = spu_int_mask_get(spu, 2);

	pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);

	stat &= mask;

	if (stat & 1)  /* PPC core mailbox */
		__spu_trap_mailbox(spu);

	if (stat & 2) /* SPU stop-and-signal */
		__spu_trap_stop(spu);

	if (stat & 4) /* SPU halted */
		__spu_trap_halt(spu);

	if (stat & 8) /* DMA tag group complete */
		__spu_trap_tag_group(spu);

	if (stat & 0x10) /* SPU mailbox threshold */
		__spu_trap_spubox(spu);

	spu_int_stat_clear(spu, 2, stat);
	return stat ? IRQ_HANDLED : IRQ_NONE;
}

static int
spu_request_irqs(struct spu *spu)
{
	int ret;
	int irq_base;

	irq_base = IIC_NODE_STRIDE * spu->node + IIC_SPE_OFFSET;

	snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0", spu->number);
	ret = request_irq(irq_base + spu->isrc,
		 spu_irq_class_0, 0, spu->irq_c0, spu);
	if (ret)
		goto out;

	snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1", spu->number);
	ret = request_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc,
		 spu_irq_class_1, 0, spu->irq_c1, spu);
	if (ret)
		goto out1;

	snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2", spu->number);
	ret = request_irq(irq_base + 2*IIC_CLASS_STRIDE + spu->isrc,
		 spu_irq_class_2, 0, spu->irq_c2, spu);
	if (ret)
		goto out2;
	goto out;

out2:
	free_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc, spu);
out1:
	free_irq(irq_base + spu->isrc, spu);
out:
	return ret;
}

static void
spu_free_irqs(struct spu *spu)
{
	int irq_base;

	irq_base = IIC_NODE_STRIDE * spu->node + IIC_SPE_OFFSET;

	free_irq(irq_base + spu->isrc, spu);
	free_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc, spu);
	free_irq(irq_base + 2*IIC_CLASS_STRIDE + spu->isrc, spu);
}

static LIST_HEAD(spu_list);
static DEFINE_MUTEX(spu_mutex);

static void spu_init_channels(struct spu *spu)
{
	static const struct {
		 unsigned channel;
		 unsigned count;
	} zero_list[] = {
		{ 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
		{ 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
	}, count_list[] = {
		{ 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
		{ 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
		{ 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
	};
	struct spu_priv2 __iomem *priv2;
	int i;

	priv2 = spu->priv2;

	/* initialize all channel data to zero */
	for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
		int count;

		out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
		for (count = 0; count < zero_list[i].count; count++)
			out_be64(&priv2->spu_chnldata_RW, 0);
	}

	/* initialize channel counts to meaningful values */
	for (i = 0; i < ARRAY_SIZE(count_list); i++) {
		out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
		out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
	}
}

struct spu *spu_alloc(void)
{
	struct spu *spu;

	mutex_lock(&spu_mutex);
	if (!list_empty(&spu_list)) {
		spu = list_entry(spu_list.next, struct spu, list);
		list_del_init(&spu->list);
		pr_debug("Got SPU %x %d\n", spu->isrc, spu->number);
	} else {
		pr_debug("No SPU left\n");
		spu = NULL;
	}
	mutex_unlock(&spu_mutex);

	if (spu)
		spu_init_channels(spu);

	return spu;
}
EXPORT_SYMBOL_GPL(spu_alloc);

void spu_free(struct spu *spu)
{
	mutex_lock(&spu_mutex);
	list_add_tail(&spu->list, &spu_list);
	mutex_unlock(&spu_mutex);
}
EXPORT_SYMBOL_GPL(spu_free);

static int spu_handle_mm_fault(struct spu *spu)
{
	struct mm_struct *mm = spu->mm;
	struct vm_area_struct *vma;
	u64 ea, dsisr, is_write;
	int ret;

	ea = spu->dar;
	dsisr = spu->dsisr;
#if 0
	if (!IS_VALID_EA(ea)) {
		return -EFAULT;
	}
#endif /* XXX */
	if (mm == NULL) {
		return -EFAULT;
	}
	if (mm->pgd == NULL) {
		return -EFAULT;
	}

	down_read(&mm->mmap_sem);
	vma = find_vma(mm, ea);
	if (!vma)
		goto bad_area;
	if (vma->vm_start <= ea)
		goto good_area;
	if (!(vma->vm_flags & VM_GROWSDOWN))
		goto bad_area;
#if 0
	if (expand_stack(vma, ea))
		goto bad_area;
#endif /* XXX */
good_area:
	is_write = dsisr & MFC_DSISR_ACCESS_PUT;
	if (is_write) {
		if (!(vma->vm_flags & VM_WRITE))
			goto bad_area;
	} else {
		if (dsisr & MFC_DSISR_ACCESS_DENIED)
			goto bad_area;
		if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
			goto bad_area;
	}
	ret = 0;
	switch (handle_mm_fault(mm, vma, ea, is_write)) {
	case VM_FAULT_MINOR:
		current->min_flt++;
		break;
	case VM_FAULT_MAJOR:
		current->maj_flt++;
		break;
	case VM_FAULT_SIGBUS:
		ret = -EFAULT;
		goto bad_area;
	case VM_FAULT_OOM:
		ret = -ENOMEM;
		goto bad_area;
	default:
		BUG();
	}
	up_read(&mm->mmap_sem);
	return ret;

bad_area:
	up_read(&mm->mmap_sem);
	return -EFAULT;
}

int spu_irq_class_1_bottom(struct spu *spu)
{
	u64 ea, dsisr, access, error = 0UL;
	int ret = 0;

	ea = spu->dar;
	dsisr = spu->dsisr;
	if (dsisr & MFC_DSISR_PTE_NOT_FOUND) {
		access = (_PAGE_PRESENT | _PAGE_USER);
		access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_RW : 0UL;
		if (hash_page(ea, access, 0x300) != 0)
			error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
	}
	if ((error & CLASS1_ENABLE_STORAGE_FAULT_INTR) ||
	    (dsisr & MFC_DSISR_ACCESS_DENIED)) {
		if ((ret = spu_handle_mm_fault(spu)) != 0)
			error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
		else
			error &= ~CLASS1_ENABLE_STORAGE_FAULT_INTR;
	}
	spu->dar = 0UL;
	spu->dsisr = 0UL;
	if (!error) {
		spu_restart_dma(spu);
	} else {
		__spu_trap_invalid_dma(spu);
	}
	return ret;
}

void spu_irq_setaffinity(struct spu *spu, int cpu)
{
	u64 target = iic_get_target_id(cpu);
	u64 route = target << 48 | target << 32 | target << 16;
	spu_int_route_set(spu, route);
}
EXPORT_SYMBOL_GPL(spu_irq_setaffinity);

static void __iomem * __init map_spe_prop(struct device_node *n,
						 const char *name)
{
	struct address_prop {
		unsigned long address;
		unsigned int len;
	} __attribute__((packed)) *prop;

	void *p;
	int proplen;

	p = get_property(n, name, &proplen);
	if (proplen != sizeof (struct address_prop))
		return NULL;

	prop = p;

	return ioremap(prop->address, prop->len);
}

static void spu_unmap(struct spu *spu)
{
	iounmap(spu->priv2);
	iounmap(spu->priv1);
	iounmap(spu->problem);
	iounmap((u8 __iomem *)spu->local_store);
}

static int __init spu_map_device(struct spu *spu, struct device_node *spe)
{
	char *prop;
	int ret;

	ret = -ENODEV;
	prop = get_property(spe, "isrc", NULL);
	if (!prop)
		goto out;
	spu->isrc = *(unsigned int *)prop;

	spu->name = get_property(spe, "name", NULL);
	if (!spu->name)
		goto out;

	prop = get_property(spe, "local-store", NULL);
	if (!prop)
		goto out;
	spu->local_store_phys = *(unsigned long *)prop;

	/* we use local store as ram, not io memory */
	spu->local_store = (void __force *)map_spe_prop(spe, "local-store");
	if (!spu->local_store)
		goto out;

	spu->problem= map_spe_prop(spe, "problem");
	if (!spu->problem)
		goto out_unmap;

	spu->priv1= map_spe_prop(spe, "priv1");
	/* priv1 is not available on a hypervisor */

	spu->priv2= map_spe_prop(spe, "priv2");
	if (!spu->priv2)
		goto out_unmap;
	ret = 0;
	goto out;

out_unmap:
	spu_unmap(spu);
out:
	return ret;
}

static int __init find_spu_node_id(struct device_node *spe)
{
	unsigned int *id;
	struct device_node *cpu;

	cpu = spe->parent->parent;
	id = (unsigned int *)get_property(cpu, "node-id", NULL);

	return id ? *id : 0;
}

static int __init create_spu(struct device_node *spe)
{
	struct spu *spu;
	int ret;
	static int number;

	ret = -ENOMEM;
	spu = kmalloc(sizeof (*spu), GFP_KERNEL);
	if (!spu)
		goto out;

	ret = spu_map_device(spu, spe);
	if (ret)
		goto out_free;

	spu->node = find_spu_node_id(spe);
	spu->stop_code = 0;
	spu->slb_replace = 0;
	spu->mm = NULL;
	spu->ctx = NULL;
	spu->rq = NULL;
	spu->pid = 0;
	spu->class_0_pending = 0;
	spu->flags = 0UL;
	spu->dar = 0UL;
	spu->dsisr = 0UL;
	spin_lock_init(&spu->register_lock);

	spu_mfc_sdr_set(spu, mfspr(SPRN_SDR1));
	spu_mfc_sr1_set(spu, 0x33);

	spu->ibox_callback = NULL;
	spu->wbox_callback = NULL;
	spu->stop_callback = NULL;
	spu->mfc_callback = NULL;

	mutex_lock(&spu_mutex);
	spu->number = number++;
	ret = spu_request_irqs(spu);
	if (ret)
		goto out_unmap;

	list_add(&spu->list, &spu_list);
	mutex_unlock(&spu_mutex);

	pr_debug(KERN_DEBUG "Using SPE %s %02x %p %p %p %p %d\n",
		spu->name, spu->isrc, spu->local_store,
		spu->problem, spu->priv1, spu->priv2, spu->number);
	goto out;

out_unmap:
	mutex_unlock(&spu_mutex);
	spu_unmap(spu);
out_free:
	kfree(spu);
out:
	return ret;
}

static void destroy_spu(struct spu *spu)
{
	list_del_init(&spu->list);

	spu_free_irqs(spu);
	spu_unmap(spu);
	kfree(spu);
}

static void cleanup_spu_base(void)
{
	struct spu *spu, *tmp;
	mutex_lock(&spu_mutex);
	list_for_each_entry_safe(spu, tmp, &spu_list, list)
		destroy_spu(spu);
	mutex_unlock(&spu_mutex);
}
module_exit(cleanup_spu_base);

static int __init init_spu_base(void)
{
	struct device_node *node;
	int ret;

	ret = -ENODEV;
	for (node = of_find_node_by_type(NULL, "spe");
			node; node = of_find_node_by_type(node, "spe")) {
		ret = create_spu(node);
		if (ret) {
			printk(KERN_WARNING "%s: Error initializing %s\n",
				__FUNCTION__, node->name);
			cleanup_spu_base();
			break;
		}
	}
	/* in some old firmware versions, the spe is called 'spc', so we
	   look for that as well */
	for (node = of_find_node_by_type(NULL, "spc");
			node; node = of_find_node_by_type(node, "spc")) {
		ret = create_spu(node);
		if (ret) {
			printk(KERN_WARNING "%s: Error initializing %s\n",
				__FUNCTION__, node->name);
			cleanup_spu_base();
			break;
		}
	}
	return ret;
}
module_init(init_spu_base);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>");
Commit	Line	Data
67207b96 AB	1	/*
	2	* Low-level SPU handling
	3	*
	4	* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
	5	*
	6	* Author: Arnd Bergmann <arndb@de.ibm.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2, or (at your option)
	11	* any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
3b3d22cb	23	#undef DEBUG
67207b96 AB	24
	25	#include <linux/interrupt.h>
	26	#include <linux/list.h>
	27	#include <linux/module.h>
	28	#include <linux/poll.h>
	29	#include <linux/ptrace.h>
	30	#include <linux/slab.h>
	31	#include <linux/wait.h>
	32
	33	#include <asm/io.h>
	34	#include <asm/prom.h>
14cc3e2b	35	#include <linux/mutex.h>
67207b96 AB	36	#include <asm/spu.h>
	37	#include <asm/mmu_context.h>
	38
	39	#include "interrupt.h"
	40
	41	static int __spu_trap_invalid_dma(struct spu *spu)
	42	{
	43	pr_debug("%s\n", __FUNCTION__);
	44	force_sig(SIGBUS, /* info, */ current);
	45	return 0;
	46	}
	47
	48	static int __spu_trap_dma_align(struct spu *spu)
	49	{
	50	pr_debug("%s\n", __FUNCTION__);
	51	force_sig(SIGBUS, /* info, */ current);
	52	return 0;
	53	}
	54
	55	static int __spu_trap_error(struct spu *spu)
	56	{
	57	pr_debug("%s\n", __FUNCTION__);
	58	force_sig(SIGILL, /* info, */ current);
	59	return 0;
	60	}
	61
	62	static void spu_restart_dma(struct spu *spu)
	63	{
	64	struct spu_priv2 __iomem *priv2 = spu->priv2;
5473af04	65
8837d921	66	if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))
5473af04	67	out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
67207b96 AB	68	}
	69
	70	static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
	71	{
8b3d6663 AB	72	struct spu_priv2 __iomem *priv2 = spu->priv2;
	73	struct mm_struct *mm = spu->mm;
	74	u64 esid, vsid;
67207b96 AB	75
	76	pr_debug("%s\n", __FUNCTION__);
	77
8837d921	78	if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
8b3d6663 AB	79	/* SLBs are pre-loaded for context switch, so
	80	* we should never get here!
	81	*/
5473af04 MN	82	printk("%s: invalid access during switch!\n", __func__);
	83	return 1;
	84	}
8b3d6663 AB	85	if (!mm \|\| (REGION_ID(ea) != USER_REGION_ID)) {
	86	/* Future: support kernel segments so that drivers
	87	* can use SPUs.
	88	*/
67207b96 AB	89	pr_debug("invalid region access at %016lx\n", ea);
	90	return 1;
	91	}
	92
8b3d6663 AB	93	esid = (ea & ESID_MASK) \| SLB_ESID_V;
	94	vsid = (get_vsid(mm->context.id, ea) << SLB_VSID_SHIFT) \| SLB_VSID_USER;
	95	if (in_hugepage_area(mm->context, ea))
	96	vsid \|= SLB_VSID_L;
67207b96	97
8b3d6663 AB	98	out_be64(&priv2->slb_index_W, spu->slb_replace);
	99	out_be64(&priv2->slb_vsid_RW, vsid);
	100	out_be64(&priv2->slb_esid_RW, esid);
	101
	102	spu->slb_replace++;
67207b96 AB	103	if (spu->slb_replace >= 8)
	104	spu->slb_replace = 0;
	105
67207b96 AB	106	spu_restart_dma(spu);
67207b96 AB	107
67207b96 AB	108	return 0;
	109	}
	110
5473af04	111	extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX
8b3d6663	112	static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
67207b96	113	{
a33a7d73	114	pr_debug("%s, %lx, %lx\n", __FUNCTION__, dsisr, ea);
67207b96	115
5473af04 MN	116	/* Handle kernel space hash faults immediately.
	117	User hash faults need to be deferred to process context. */
	118	if ((dsisr & MFC_DSISR_PTE_NOT_FOUND)
	119	&& REGION_ID(ea) != USER_REGION_ID
	120	&& hash_page(ea, _PAGE_PRESENT, 0x300) == 0) {
	121	spu_restart_dma(spu);
	122	return 0;
	123	}
	124
8837d921	125	if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
5473af04 MN	126	printk("%s: invalid access during switch!\n", __func__);
	127	return 1;
	128	}
67207b96	129
8b3d6663 AB	130	spu->dar = ea;
	131	spu->dsisr = dsisr;
	132	mb();
5110459f AB	133	if (spu->stop_callback)
5110459f AB	134	spu->stop_callback(spu);
67207b96 AB	135	return 0;
	136	}
	137
	138	static int __spu_trap_mailbox(struct spu *spu)
	139	{
8b3d6663 AB	140	if (spu->ibox_callback)
8b3d6663 AB	141	spu->ibox_callback(spu);
67207b96 AB	142
	143	/* atomically disable SPU mailbox interrupts */
	144	spin_lock(&spu->register_lock);
f0831acc	145	spu_int_mask_and(spu, 2, ~0x1);
67207b96 AB	146	spin_unlock(&spu->register_lock);
	147	return 0;
	148	}
	149
	150	static int __spu_trap_stop(struct spu *spu)
	151	{
	152	pr_debug("%s\n", __FUNCTION__);
	153	spu->stop_code = in_be32(&spu->problem->spu_status_R);
5110459f AB	154	if (spu->stop_callback)
5110459f AB	155	spu->stop_callback(spu);
67207b96 AB	156	return 0;
	157	}
	158
	159	static int __spu_trap_halt(struct spu *spu)
	160	{
	161	pr_debug("%s\n", __FUNCTION__);
	162	spu->stop_code = in_be32(&spu->problem->spu_status_R);
5110459f AB	163	if (spu->stop_callback)
5110459f AB	164	spu->stop_callback(spu);
67207b96 AB	165	return 0;
	166	}
	167
	168	static int __spu_trap_tag_group(struct spu *spu)
	169	{
	170	pr_debug("%s\n", __FUNCTION__);
a33a7d73	171	spu->mfc_callback(spu);
67207b96 AB	172	return 0;
	173	}
	174
	175	static int __spu_trap_spubox(struct spu *spu)
	176	{
8b3d6663 AB	177	if (spu->wbox_callback)
8b3d6663 AB	178	spu->wbox_callback(spu);
67207b96 AB	179
	180	/* atomically disable SPU mailbox interrupts */
	181	spin_lock(&spu->register_lock);
f0831acc	182	spu_int_mask_and(spu, 2, ~0x10);
67207b96 AB	183	spin_unlock(&spu->register_lock);
	184	return 0;
	185	}
	186
	187	static irqreturn_t
	188	spu_irq_class_0(int irq, void data, struct pt_regs regs)
	189	{
	190	struct spu *spu;
	191
	192	spu = data;
	193	spu->class_0_pending = 1;
5110459f AB	194	if (spu->stop_callback)
5110459f AB	195	spu->stop_callback(spu);
67207b96 AB	196
	197	return IRQ_HANDLED;
	198	}
	199
5110459f	200	int
67207b96 AB	201	spu_irq_class_0_bottom(struct spu *spu)
67207b96 AB	202	{
3a843d7c	203	unsigned long stat, mask;
67207b96 AB	204
	205	spu->class_0_pending = 0;
	206
f0831acc AB	207	mask = spu_int_mask_get(spu, 0);
f0831acc AB	208	stat = spu_int_stat_get(spu, 0);
67207b96	209
3a843d7c AB	210	stat &= mask;
3a843d7c AB	211
67207b96 AB	212	if (stat & 1) /* invalid MFC DMA */
	213	__spu_trap_invalid_dma(spu);
	214
	215	if (stat & 2) /* invalid DMA alignment */
	216	__spu_trap_dma_align(spu);
	217
	218	if (stat & 4) /* error on SPU */
	219	__spu_trap_error(spu);
	220
f0831acc	221	spu_int_stat_clear(spu, 0, stat);
5110459f AB	222
5110459f AB	223	return (stat & 0x7) ? -EIO : 0;
67207b96	224	}
5110459f	225	EXPORT_SYMBOL_GPL(spu_irq_class_0_bottom);
67207b96 AB	226
	227	static irqreturn_t
	228	spu_irq_class_1(int irq, void data, struct pt_regs regs)
	229	{
	230	struct spu *spu;
8b3d6663	231	unsigned long stat, mask, dar, dsisr;
67207b96 AB	232
67207b96 AB	233	spu = data;
8b3d6663 AB	234
	235	/* atomically read & clear class1 status. */
	236	spin_lock(&spu->register_lock);
f0831acc AB	237	mask = spu_int_mask_get(spu, 1);
	238	stat = spu_int_stat_get(spu, 1) & mask;
	239	dar = spu_mfc_dar_get(spu);
	240	dsisr = spu_mfc_dsisr_get(spu);
38307341	241	if (stat & 2) /* mapping fault */
f0831acc AB	242	spu_mfc_dsisr_set(spu, 0ul);
f0831acc AB	243	spu_int_stat_clear(spu, 1, stat);
8b3d6663	244	spin_unlock(&spu->register_lock);
a33a7d73 AB	245	pr_debug("%s: %lx %lx %lx %lx\n", __FUNCTION__, mask, stat,
a33a7d73 AB	246	dar, dsisr);
67207b96 AB	247
	248	if (stat & 1) /* segment fault */
	249	__spu_trap_data_seg(spu, dar);
	250
	251	if (stat & 2) { /* mapping fault */
8b3d6663	252	__spu_trap_data_map(spu, dar, dsisr);
67207b96 AB	253	}
	254
	255	if (stat & 4) /* ls compare & suspend on get */
	256	;
	257
	258	if (stat & 8) /* ls compare & suspend on put */
	259	;
	260
67207b96 AB	261	return stat ? IRQ_HANDLED : IRQ_NONE;
67207b96 AB	262	}
5110459f	263	EXPORT_SYMBOL_GPL(spu_irq_class_1_bottom);
67207b96 AB	264
	265	static irqreturn_t
	266	spu_irq_class_2(int irq, void data, struct pt_regs regs)
	267	{
	268	struct spu *spu;
	269	unsigned long stat;
3a843d7c	270	unsigned long mask;
67207b96 AB	271
67207b96 AB	272	spu = data;
f0831acc AB	273	stat = spu_int_stat_get(spu, 2);
f0831acc AB	274	mask = spu_int_mask_get(spu, 2);
67207b96	275
3a843d7c	276	pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);
67207b96	277
3a843d7c	278	stat &= mask;
67207b96 AB	279
	280	if (stat & 1) /* PPC core mailbox */
	281	__spu_trap_mailbox(spu);
	282
	283	if (stat & 2) /* SPU stop-and-signal */
	284	__spu_trap_stop(spu);
	285
	286	if (stat & 4) /* SPU halted */
	287	__spu_trap_halt(spu);
	288
	289	if (stat & 8) /* DMA tag group complete */
	290	__spu_trap_tag_group(spu);
	291
	292	if (stat & 0x10) /* SPU mailbox threshold */
	293	__spu_trap_spubox(spu);
	294
f0831acc	295	spu_int_stat_clear(spu, 2, stat);
67207b96 AB	296	return stat ? IRQ_HANDLED : IRQ_NONE;
	297	}
	298
	299	static int
	300	spu_request_irqs(struct spu *spu)
	301	{
	302	int ret;
	303	int irq_base;
	304
	305	irq_base = IIC_NODE_STRIDE * spu->node + IIC_SPE_OFFSET;
	306
	307	snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0", spu->number);
	308	ret = request_irq(irq_base + spu->isrc,
	309	spu_irq_class_0, 0, spu->irq_c0, spu);
	310	if (ret)
	311	goto out;
67207b96 AB	312
	313	snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1", spu->number);
	314	ret = request_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc,
	315	spu_irq_class_1, 0, spu->irq_c1, spu);
	316	if (ret)
	317	goto out1;
67207b96 AB	318
	319	snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2", spu->number);
	320	ret = request_irq(irq_base + 2*IIC_CLASS_STRIDE + spu->isrc,
	321	spu_irq_class_2, 0, spu->irq_c2, spu);
	322	if (ret)
	323	goto out2;
67207b96 AB	324	goto out;
	325
	326	out2:
	327	free_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc, spu);
	328	out1:
	329	free_irq(irq_base + spu->isrc, spu);
	330	out:
	331	return ret;
	332	}
	333
	334	static void
	335	spu_free_irqs(struct spu *spu)
	336	{
	337	int irq_base;
	338
	339	irq_base = IIC_NODE_STRIDE * spu->node + IIC_SPE_OFFSET;
	340
	341	free_irq(irq_base + spu->isrc, spu);
	342	free_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc, spu);
	343	free_irq(irq_base + 2*IIC_CLASS_STRIDE + spu->isrc, spu);
	344	}
	345
	346	static LIST_HEAD(spu_list);
14cc3e2b	347	static DEFINE_MUTEX(spu_mutex);
67207b96 AB	348
	349	static void spu_init_channels(struct spu *spu)
	350	{
	351	static const struct {
	352	unsigned channel;
	353	unsigned count;
	354	} zero_list[] = {
	355	{ 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
	356	{ 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
	357	}, count_list[] = {
	358	{ 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
	359	{ 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
	360	{ 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
	361	};
6ff730c3	362	struct spu_priv2 __iomem *priv2;
67207b96 AB	363	int i;
	364
	365	priv2 = spu->priv2;
	366
	367	/* initialize all channel data to zero */
	368	for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
	369	int count;
	370
	371	out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
	372	for (count = 0; count < zero_list[i].count; count++)
	373	out_be64(&priv2->spu_chnldata_RW, 0);
	374	}
	375
	376	/* initialize channel counts to meaningful values */
	377	for (i = 0; i < ARRAY_SIZE(count_list); i++) {
	378	out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
	379	out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
	380	}
	381	}
	382
67207b96 AB	383	struct spu *spu_alloc(void)
	384	{
	385	struct spu *spu;
	386
14cc3e2b	387	mutex_lock(&spu_mutex);
67207b96 AB	388	if (!list_empty(&spu_list)) {
	389	spu = list_entry(spu_list.next, struct spu, list);
	390	list_del_init(&spu->list);
	391	pr_debug("Got SPU %x %d\n", spu->isrc, spu->number);
	392	} else {
	393	pr_debug("No SPU left\n");
	394	spu = NULL;
	395	}
14cc3e2b	396	mutex_unlock(&spu_mutex);
67207b96	397
f0831acc	398	if (spu)
67207b96	399	spu_init_channels(spu);
67207b96 AB	400
	401	return spu;
	402	}
39c73c33	403	EXPORT_SYMBOL_GPL(spu_alloc);
67207b96 AB	404
	405	void spu_free(struct spu *spu)
	406	{
14cc3e2b	407	mutex_lock(&spu_mutex);
67207b96	408	list_add_tail(&spu->list, &spu_list);
14cc3e2b	409	mutex_unlock(&spu_mutex);
67207b96	410	}
39c73c33	411	EXPORT_SYMBOL_GPL(spu_free);
67207b96	412
67207b96 AB	413	static int spu_handle_mm_fault(struct spu *spu)
67207b96 AB	414	{
67207b96 AB	415	struct mm_struct *mm = spu->mm;
	416	struct vm_area_struct *vma;
	417	u64 ea, dsisr, is_write;
	418	int ret;
	419
8b3d6663 AB	420	ea = spu->dar;
8b3d6663 AB	421	dsisr = spu->dsisr;
67207b96 AB	422	#if 0
	423	if (!IS_VALID_EA(ea)) {
	424	return -EFAULT;
	425	}
	426	#endif /* XXX */
	427	if (mm == NULL) {
	428	return -EFAULT;
	429	}
	430	if (mm->pgd == NULL) {
	431	return -EFAULT;
	432	}
	433
	434	down_read(&mm->mmap_sem);
	435	vma = find_vma(mm, ea);
	436	if (!vma)
	437	goto bad_area;
	438	if (vma->vm_start <= ea)
	439	goto good_area;
	440	if (!(vma->vm_flags & VM_GROWSDOWN))
	441	goto bad_area;
	442	#if 0
	443	if (expand_stack(vma, ea))
	444	goto bad_area;
	445	#endif /* XXX */
	446	good_area:
	447	is_write = dsisr & MFC_DSISR_ACCESS_PUT;
	448	if (is_write) {
	449	if (!(vma->vm_flags & VM_WRITE))
	450	goto bad_area;
	451	} else {
	452	if (dsisr & MFC_DSISR_ACCESS_DENIED)
	453	goto bad_area;
	454	if (!(vma->vm_flags & (VM_READ \| VM_EXEC)))
	455	goto bad_area;
	456	}
	457	ret = 0;
	458	switch (handle_mm_fault(mm, vma, ea, is_write)) {
	459	case VM_FAULT_MINOR:
	460	current->min_flt++;
	461	break;
	462	case VM_FAULT_MAJOR:
	463	current->maj_flt++;
	464	break;
	465	case VM_FAULT_SIGBUS:
	466	ret = -EFAULT;
	467	goto bad_area;
	468	case VM_FAULT_OOM:
	469	ret = -ENOMEM;
	470	goto bad_area;
	471	default:
	472	BUG();
	473	}
	474	up_read(&mm->mmap_sem);
	475	return ret;
	476
	477	bad_area:
	478	up_read(&mm->mmap_sem);
	479	return -EFAULT;
	480	}
	481
5110459f	482	int spu_irq_class_1_bottom(struct spu *spu)
67207b96	483	{
67207b96 AB	484	u64 ea, dsisr, access, error = 0UL;
	485	int ret = 0;
	486
8b3d6663 AB	487	ea = spu->dar;
8b3d6663 AB	488	dsisr = spu->dsisr;
67207b96	489	if (dsisr & MFC_DSISR_PTE_NOT_FOUND) {
8b3d6663 AB	490	access = (_PAGE_PRESENT \| _PAGE_USER);
8b3d6663 AB	491	access \|= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_RW : 0UL;
67207b96 AB	492	if (hash_page(ea, access, 0x300) != 0)
	493	error \|= CLASS1_ENABLE_STORAGE_FAULT_INTR;
	494	}
	495	if ((error & CLASS1_ENABLE_STORAGE_FAULT_INTR) \|\|
	496	(dsisr & MFC_DSISR_ACCESS_DENIED)) {
	497	if ((ret = spu_handle_mm_fault(spu)) != 0)
	498	error \|= CLASS1_ENABLE_STORAGE_FAULT_INTR;
	499	else
	500	error &= ~CLASS1_ENABLE_STORAGE_FAULT_INTR;
	501	}
8b3d6663 AB	502	spu->dar = 0UL;
	503	spu->dsisr = 0UL;
	504	if (!error) {
67207b96	505	spu_restart_dma(spu);
8b3d6663 AB	506	} else {
	507	__spu_trap_invalid_dma(spu);
	508	}
67207b96 AB	509	return ret;
	510	}
	511
2fb9d206 AB	512	void spu_irq_setaffinity(struct spu *spu, int cpu)
	513	{
	514	u64 target = iic_get_target_id(cpu);
	515	u64 route = target << 48 \| target << 32 \| target << 16;
	516	spu_int_route_set(spu, route);
	517	}
	518	EXPORT_SYMBOL_GPL(spu_irq_setaffinity);
	519
67207b96 AB	520	static void __iomem * __init map_spe_prop(struct device_node *n,
	521	const char *name)
	522	{
	523	struct address_prop {
	524	unsigned long address;
	525	unsigned int len;
	526	} __attribute__((packed)) *prop;
	527
	528	void *p;
	529	int proplen;
	530
	531	p = get_property(n, name, &proplen);
	532	if (proplen != sizeof (struct address_prop))
	533	return NULL;
	534
	535	prop = p;
	536
	537	return ioremap(prop->address, prop->len);
	538	}
	539
	540	static void spu_unmap(struct spu *spu)
	541	{
	542	iounmap(spu->priv2);
	543	iounmap(spu->priv1);
	544	iounmap(spu->problem);
	545	iounmap((u8 __iomem *)spu->local_store);
	546	}
	547
	548	static int __init spu_map_device(struct spu spu, struct device_node spe)
	549	{
	550	char *prop;
	551	int ret;
	552
	553	ret = -ENODEV;
	554	prop = get_property(spe, "isrc", NULL);
	555	if (!prop)
	556	goto out;
	557	spu->isrc = (unsigned int )prop;
	558
	559	spu->name = get_property(spe, "name", NULL);
	560	if (!spu->name)
	561	goto out;
	562
	563	prop = get_property(spe, "local-store", NULL);
	564	if (!prop)
	565	goto out;
	566	spu->local_store_phys = (unsigned long )prop;
	567
	568	/* we use local store as ram, not io memory */
	569	spu->local_store = (void __force *)map_spe_prop(spe, "local-store");
	570	if (!spu->local_store)
	571	goto out;
	572
	573	spu->problem= map_spe_prop(spe, "problem");
	574	if (!spu->problem)
	575	goto out_unmap;
	576
	577	spu->priv1= map_spe_prop(spe, "priv1");
f0831acc	578	/* priv1 is not available on a hypervisor */
67207b96 AB	579
	580	spu->priv2= map_spe_prop(spe, "priv2");
	581	if (!spu->priv2)
	582	goto out_unmap;
	583	ret = 0;
	584	goto out;
	585
	586	out_unmap:
	587	spu_unmap(spu);
	588	out:
	589	return ret;
	590	}
	591
	592	static int __init find_spu_node_id(struct device_node *spe)
	593	{
	594	unsigned int *id;
	595	struct device_node *cpu;
	596
	597	cpu = spe->parent->parent;
	598	id = (unsigned int *)get_property(cpu, "node-id", NULL);
	599
	600	return id ? *id : 0;
	601	}
	602
	603	static int __init create_spu(struct device_node *spe)
	604	{
	605	struct spu *spu;
	606	int ret;
	607	static int number;
	608
	609	ret = -ENOMEM;
	610	spu = kmalloc(sizeof (*spu), GFP_KERNEL);
	611	if (!spu)
	612	goto out;
	613
	614	ret = spu_map_device(spu, spe);
	615	if (ret)
	616	goto out_free;
	617
	618	spu->node = find_spu_node_id(spe);
	619	spu->stop_code = 0;
	620	spu->slb_replace = 0;
	621	spu->mm = NULL;
8b3d6663 AB	622	spu->ctx = NULL;
	623	spu->rq = NULL;
	624	spu->pid = 0;
67207b96	625	spu->class_0_pending = 0;
5473af04	626	spu->flags = 0UL;
8b3d6663 AB	627	spu->dar = 0UL;
8b3d6663 AB	628	spu->dsisr = 0UL;
67207b96 AB	629	spin_lock_init(&spu->register_lock);
67207b96 AB	630
f0831acc AB	631	spu_mfc_sdr_set(spu, mfspr(SPRN_SDR1));
f0831acc AB	632	spu_mfc_sr1_set(spu, 0x33);
67207b96	633
8b3d6663 AB	634	spu->ibox_callback = NULL;
8b3d6663 AB	635	spu->wbox_callback = NULL;
5110459f	636	spu->stop_callback = NULL;
a33a7d73	637	spu->mfc_callback = NULL;
67207b96	638
14cc3e2b	639	mutex_lock(&spu_mutex);
67207b96 AB	640	spu->number = number++;
	641	ret = spu_request_irqs(spu);
	642	if (ret)
	643	goto out_unmap;
	644
	645	list_add(&spu->list, &spu_list);
14cc3e2b	646	mutex_unlock(&spu_mutex);
67207b96 AB	647
	648	pr_debug(KERN_DEBUG "Using SPE %s %02x %p %p %p %p %d\n",
	649	spu->name, spu->isrc, spu->local_store,
	650	spu->problem, spu->priv1, spu->priv2, spu->number);
	651	goto out;
	652
	653	out_unmap:
14cc3e2b	654	mutex_unlock(&spu_mutex);
67207b96 AB	655	spu_unmap(spu);
	656	out_free:
	657	kfree(spu);
	658	out:
	659	return ret;
	660	}
	661
	662	static void destroy_spu(struct spu *spu)
	663	{
	664	list_del_init(&spu->list);
	665
	666	spu_free_irqs(spu);
	667	spu_unmap(spu);
	668	kfree(spu);
	669	}
	670
	671	static void cleanup_spu_base(void)
	672	{
	673	struct spu spu, tmp;
14cc3e2b	674	mutex_lock(&spu_mutex);
67207b96 AB	675	list_for_each_entry_safe(spu, tmp, &spu_list, list)
67207b96 AB	676	destroy_spu(spu);
14cc3e2b	677	mutex_unlock(&spu_mutex);
67207b96 AB	678	}
	679	module_exit(cleanup_spu_base);
	680
	681	static int __init init_spu_base(void)
	682	{
	683	struct device_node *node;
	684	int ret;
	685
	686	ret = -ENODEV;
	687	for (node = of_find_node_by_type(NULL, "spe");
	688	node; node = of_find_node_by_type(node, "spe")) {
	689	ret = create_spu(node);
	690	if (ret) {
	691	printk(KERN_WARNING "%s: Error initializing %s\n",
	692	__FUNCTION__, node->name);
	693	cleanup_spu_base();
	694	break;
	695	}
	696	}
	697	/* in some old firmware versions, the spe is called 'spc', so we
	698	look for that as well */
	699	for (node = of_find_node_by_type(NULL, "spc");
	700	node; node = of_find_node_by_type(node, "spc")) {
	701	ret = create_spu(node);
	702	if (ret) {
	703	printk(KERN_WARNING "%s: Error initializing %s\n",
	704	__FUNCTION__, node->name);
	705	cleanup_spu_base();
	706	break;
	707	}
	708	}
	709	return ret;
	710	}
	711	module_init(init_spu_base);
	712
	713	MODULE_LICENSE("GPL");
	714	MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>");