Commit | Line | Data |
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67207b96 AB |
1 | /* |
2 | * Low-level SPU handling | |
3 | * | |
4 | * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 | |
5 | * | |
6 | * Author: Arnd Bergmann <arndb@de.ibm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
3b3d22cb | 23 | #undef DEBUG |
67207b96 AB |
24 | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/list.h> | |
8038665f | 27 | #include <linux/init.h> |
67207b96 AB |
28 | #include <linux/ptrace.h> |
29 | #include <linux/slab.h> | |
30 | #include <linux/wait.h> | |
e28b0031 GL |
31 | #include <linux/mm.h> |
32 | #include <linux/io.h> | |
14cc3e2b | 33 | #include <linux/mutex.h> |
bce94513 | 34 | #include <linux/linux_logo.h> |
f5a592f7 | 35 | #include <linux/syscore_ops.h> |
67207b96 | 36 | #include <asm/spu.h> |
540270d8 | 37 | #include <asm/spu_priv1.h> |
58bd403c | 38 | #include <asm/spu_csa.h> |
ff8a8f25 | 39 | #include <asm/xmon.h> |
3ad216ca | 40 | #include <asm/prom.h> |
158d5b5e | 41 | #include <asm/kexec.h> |
67207b96 | 42 | |
e28b0031 | 43 | const struct spu_management_ops *spu_management_ops; |
ccf17e9d JK |
44 | EXPORT_SYMBOL_GPL(spu_management_ops); |
45 | ||
540270d8 | 46 | const struct spu_priv1_ops *spu_priv1_ops; |
24140594 | 47 | EXPORT_SYMBOL_GPL(spu_priv1_ops); |
540270d8 | 48 | |
24140594 CH |
49 | struct cbe_spu_info cbe_spu_info[MAX_NUMNODES]; |
50 | EXPORT_SYMBOL_GPL(cbe_spu_info); | |
94b2a439 | 51 | |
3ce2f62b JK |
52 | /* |
53 | * The spufs fault-handling code needs to call force_sig_info to raise signals | |
54 | * on DMA errors. Export it here to avoid general kernel-wide access to this | |
55 | * function | |
56 | */ | |
57 | EXPORT_SYMBOL_GPL(force_sig_info); | |
58 | ||
24140594 CH |
59 | /* |
60 | * Protects cbe_spu_info and spu->number. | |
61 | */ | |
62 | static DEFINE_SPINLOCK(spu_lock); | |
63 | ||
64 | /* | |
65 | * List of all spus in the system. | |
66 | * | |
67 | * This list is iterated by callers from irq context and callers that | |
68 | * want to sleep. Thus modifications need to be done with both | |
69 | * spu_full_list_lock and spu_full_list_mutex held, while iterating | |
70 | * through it requires either of these locks. | |
71 | * | |
027dfac6 | 72 | * In addition spu_full_list_lock protects all assignments to |
24140594 CH |
73 | * spu->mm. |
74 | */ | |
75 | static LIST_HEAD(spu_full_list); | |
76 | static DEFINE_SPINLOCK(spu_full_list_lock); | |
77 | static DEFINE_MUTEX(spu_full_list_mutex); | |
540270d8 | 78 | |
94b2a439 BH |
79 | void spu_invalidate_slbs(struct spu *spu) |
80 | { | |
81 | struct spu_priv2 __iomem *priv2 = spu->priv2; | |
c92a1acb | 82 | unsigned long flags; |
94b2a439 | 83 | |
c92a1acb | 84 | spin_lock_irqsave(&spu->register_lock, flags); |
94b2a439 BH |
85 | if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK) |
86 | out_be64(&priv2->slb_invalidate_all_W, 0UL); | |
c92a1acb | 87 | spin_unlock_irqrestore(&spu->register_lock, flags); |
94b2a439 BH |
88 | } |
89 | EXPORT_SYMBOL_GPL(spu_invalidate_slbs); | |
90 | ||
91 | /* This is called by the MM core when a segment size is changed, to | |
92 | * request a flush of all the SPEs using a given mm | |
93 | */ | |
94 | void spu_flush_all_slbs(struct mm_struct *mm) | |
95 | { | |
96 | struct spu *spu; | |
97 | unsigned long flags; | |
98 | ||
24140594 | 99 | spin_lock_irqsave(&spu_full_list_lock, flags); |
94b2a439 BH |
100 | list_for_each_entry(spu, &spu_full_list, full_list) { |
101 | if (spu->mm == mm) | |
102 | spu_invalidate_slbs(spu); | |
103 | } | |
24140594 | 104 | spin_unlock_irqrestore(&spu_full_list_lock, flags); |
94b2a439 BH |
105 | } |
106 | ||
107 | /* The hack below stinks... try to do something better one of | |
108 | * these days... Does it even work properly with NR_CPUS == 1 ? | |
109 | */ | |
110 | static inline void mm_needs_global_tlbie(struct mm_struct *mm) | |
111 | { | |
112 | int nr = (NR_CPUS > 1) ? NR_CPUS : NR_CPUS + 1; | |
113 | ||
114 | /* Global TLBIE broadcast required with SPEs. */ | |
56aa4129 | 115 | bitmap_fill(cpumask_bits(mm_cpumask(mm)), nr); |
94b2a439 BH |
116 | } |
117 | ||
118 | void spu_associate_mm(struct spu *spu, struct mm_struct *mm) | |
119 | { | |
120 | unsigned long flags; | |
121 | ||
24140594 | 122 | spin_lock_irqsave(&spu_full_list_lock, flags); |
94b2a439 | 123 | spu->mm = mm; |
24140594 | 124 | spin_unlock_irqrestore(&spu_full_list_lock, flags); |
94b2a439 BH |
125 | if (mm) |
126 | mm_needs_global_tlbie(mm); | |
127 | } | |
128 | EXPORT_SYMBOL_GPL(spu_associate_mm); | |
129 | ||
f6eb7d7f JK |
130 | int spu_64k_pages_available(void) |
131 | { | |
132 | return mmu_psize_defs[MMU_PAGE_64K].shift != 0; | |
133 | } | |
134 | EXPORT_SYMBOL_GPL(spu_64k_pages_available); | |
135 | ||
67207b96 AB |
136 | static void spu_restart_dma(struct spu *spu) |
137 | { | |
138 | struct spu_priv2 __iomem *priv2 = spu->priv2; | |
5473af04 | 139 | |
8837d921 | 140 | if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags)) |
5473af04 | 141 | out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); |
de102892 LB |
142 | else { |
143 | set_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags); | |
144 | mb(); | |
145 | } | |
67207b96 AB |
146 | } |
147 | ||
73d16a6e | 148 | static inline void spu_load_slb(struct spu *spu, int slbe, struct copro_slb *slb) |
58bd403c JK |
149 | { |
150 | struct spu_priv2 __iomem *priv2 = spu->priv2; | |
151 | ||
fe333321 | 152 | pr_debug("%s: adding SLB[%d] 0x%016llx 0x%016llx\n", |
58bd403c JK |
153 | __func__, slbe, slb->vsid, slb->esid); |
154 | ||
155 | out_be64(&priv2->slb_index_W, slbe); | |
cc4b7c18 AB |
156 | /* set invalid before writing vsid */ |
157 | out_be64(&priv2->slb_esid_RW, 0); | |
158 | /* now it's safe to write the vsid */ | |
58bd403c | 159 | out_be64(&priv2->slb_vsid_RW, slb->vsid); |
cc4b7c18 | 160 | /* setting the new esid makes the entry valid again */ |
58bd403c JK |
161 | out_be64(&priv2->slb_esid_RW, slb->esid); |
162 | } | |
163 | ||
67207b96 AB |
164 | static int __spu_trap_data_seg(struct spu *spu, unsigned long ea) |
165 | { | |
73d16a6e IM |
166 | struct copro_slb slb; |
167 | int ret; | |
168 | ||
169 | ret = copro_calculate_slb(spu->mm, ea, &slb); | |
170 | if (ret) | |
171 | return ret; | |
67207b96 | 172 | |
4d43466d | 173 | spu_load_slb(spu, spu->slb_replace, &slb); |
8b3d6663 AB |
174 | |
175 | spu->slb_replace++; | |
67207b96 AB |
176 | if (spu->slb_replace >= 8) |
177 | spu->slb_replace = 0; | |
178 | ||
67207b96 | 179 | spu_restart_dma(spu); |
e9f8a0b6 | 180 | spu->stats.slb_flt++; |
67207b96 AB |
181 | return 0; |
182 | } | |
183 | ||
aefa5688 AK |
184 | extern int hash_page(unsigned long ea, unsigned long access, |
185 | unsigned long trap, unsigned long dsisr); //XXX | |
8b3d6663 | 186 | static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr) |
67207b96 | 187 | { |
2c911a14 LB |
188 | int ret; |
189 | ||
fe333321 | 190 | pr_debug("%s, %llx, %lx\n", __func__, dsisr, ea); |
67207b96 | 191 | |
2c911a14 LB |
192 | /* |
193 | * Handle kernel space hash faults immediately. User hash | |
194 | * faults need to be deferred to process context. | |
195 | */ | |
196 | if ((dsisr & MFC_DSISR_PTE_NOT_FOUND) && | |
197 | (REGION_ID(ea) != USER_REGION_ID)) { | |
198 | ||
199 | spin_unlock(&spu->register_lock); | |
c7d54842 | 200 | ret = hash_page(ea, _PAGE_PRESENT | _PAGE_READ, 0x300, dsisr); |
2c911a14 LB |
201 | spin_lock(&spu->register_lock); |
202 | ||
203 | if (!ret) { | |
204 | spu_restart_dma(spu); | |
205 | return 0; | |
206 | } | |
5473af04 MN |
207 | } |
208 | ||
f3d69e05 LB |
209 | spu->class_1_dar = ea; |
210 | spu->class_1_dsisr = dsisr; | |
211 | ||
212 | spu->stop_callback(spu, 1); | |
d6ad39bc | 213 | |
f3d69e05 LB |
214 | spu->class_1_dar = 0; |
215 | spu->class_1_dsisr = 0; | |
d6ad39bc | 216 | |
67207b96 AB |
217 | return 0; |
218 | } | |
219 | ||
73d16a6e | 220 | static void __spu_kernel_slb(void *addr, struct copro_slb *slb) |
58bd403c JK |
221 | { |
222 | unsigned long ea = (unsigned long)addr; | |
223 | u64 llp; | |
224 | ||
225 | if (REGION_ID(ea) == KERNEL_REGION_ID) | |
226 | llp = mmu_psize_defs[mmu_linear_psize].sllp; | |
227 | else | |
228 | llp = mmu_psize_defs[mmu_virtual_psize].sllp; | |
229 | ||
230 | slb->vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) << SLB_VSID_SHIFT) | | |
231 | SLB_VSID_KERNEL | llp; | |
232 | slb->esid = (ea & ESID_MASK) | SLB_ESID_V; | |
233 | } | |
234 | ||
684bd614 JK |
235 | /** |
236 | * Given an array of @nr_slbs SLB entries, @slbs, return non-zero if the | |
237 | * address @new_addr is present. | |
238 | */ | |
73d16a6e | 239 | static inline int __slb_present(struct copro_slb *slbs, int nr_slbs, |
684bd614 JK |
240 | void *new_addr) |
241 | { | |
242 | unsigned long ea = (unsigned long)new_addr; | |
243 | int i; | |
244 | ||
245 | for (i = 0; i < nr_slbs; i++) | |
246 | if (!((slbs[i].esid ^ ea) & ESID_MASK)) | |
247 | return 1; | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
58bd403c JK |
252 | /** |
253 | * Setup the SPU kernel SLBs, in preparation for a context save/restore. We | |
254 | * need to map both the context save area, and the save/restore code. | |
684bd614 | 255 | * |
027dfac6 | 256 | * Because the lscsa and code may cross segment boundaries, we check to see |
684bd614 JK |
257 | * if mappings are required for the start and end of each range. We currently |
258 | * assume that the mappings are smaller that one segment - if not, something | |
259 | * is seriously wrong. | |
58bd403c | 260 | */ |
684bd614 JK |
261 | void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa, |
262 | void *code, int code_size) | |
58bd403c | 263 | { |
73d16a6e | 264 | struct copro_slb slbs[4]; |
684bd614 JK |
265 | int i, nr_slbs = 0; |
266 | /* start and end addresses of both mappings */ | |
267 | void *addrs[] = { | |
268 | lscsa, (void *)lscsa + sizeof(*lscsa) - 1, | |
269 | code, code + code_size - 1 | |
270 | }; | |
271 | ||
272 | /* check the set of addresses, and create a new entry in the slbs array | |
273 | * if there isn't already a SLB for that address */ | |
274 | for (i = 0; i < ARRAY_SIZE(addrs); i++) { | |
275 | if (__slb_present(slbs, nr_slbs, addrs[i])) | |
276 | continue; | |
277 | ||
278 | __spu_kernel_slb(addrs[i], &slbs[nr_slbs]); | |
279 | nr_slbs++; | |
280 | } | |
58bd403c | 281 | |
c92a1acb | 282 | spin_lock_irq(&spu->register_lock); |
684bd614 JK |
283 | /* Add the set of SLBs */ |
284 | for (i = 0; i < nr_slbs; i++) | |
285 | spu_load_slb(spu, i, &slbs[i]); | |
c92a1acb | 286 | spin_unlock_irq(&spu->register_lock); |
58bd403c JK |
287 | } |
288 | EXPORT_SYMBOL_GPL(spu_setup_kernel_slbs); | |
289 | ||
67207b96 | 290 | static irqreturn_t |
f5a92458 | 291 | spu_irq_class_0(int irq, void *data) |
67207b96 AB |
292 | { |
293 | struct spu *spu; | |
b7f90a40 | 294 | unsigned long stat, mask; |
67207b96 AB |
295 | |
296 | spu = data; | |
b7f90a40 | 297 | |
d6ad39bc | 298 | spin_lock(&spu->register_lock); |
b7f90a40 | 299 | mask = spu_int_mask_get(spu, 0); |
d6ad39bc | 300 | stat = spu_int_stat_get(spu, 0) & mask; |
b7f90a40 | 301 | |
b7f90a40 | 302 | spu->class_0_pending |= stat; |
f3d69e05 | 303 | spu->class_0_dar = spu_mfc_dar_get(spu); |
f3d69e05 | 304 | spu->stop_callback(spu, 0); |
f3d69e05 | 305 | spu->class_0_pending = 0; |
f3d69e05 | 306 | spu->class_0_dar = 0; |
67207b96 | 307 | |
b7f90a40 | 308 | spu_int_stat_clear(spu, 0, stat); |
2c911a14 | 309 | spin_unlock(&spu->register_lock); |
b7f90a40 | 310 | |
67207b96 AB |
311 | return IRQ_HANDLED; |
312 | } | |
313 | ||
67207b96 | 314 | static irqreturn_t |
f5a92458 | 315 | spu_irq_class_1(int irq, void *data) |
67207b96 AB |
316 | { |
317 | struct spu *spu; | |
8b3d6663 | 318 | unsigned long stat, mask, dar, dsisr; |
67207b96 AB |
319 | |
320 | spu = data; | |
8b3d6663 AB |
321 | |
322 | /* atomically read & clear class1 status. */ | |
323 | spin_lock(&spu->register_lock); | |
f0831acc AB |
324 | mask = spu_int_mask_get(spu, 1); |
325 | stat = spu_int_stat_get(spu, 1) & mask; | |
326 | dar = spu_mfc_dar_get(spu); | |
327 | dsisr = spu_mfc_dsisr_get(spu); | |
8af30675 | 328 | if (stat & CLASS1_STORAGE_FAULT_INTR) |
f0831acc AB |
329 | spu_mfc_dsisr_set(spu, 0ul); |
330 | spu_int_stat_clear(spu, 1, stat); | |
67207b96 | 331 | |
e48b1b45 | 332 | pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat, |
c92a1acb AB |
333 | dar, dsisr); |
334 | ||
2c911a14 LB |
335 | if (stat & CLASS1_SEGMENT_FAULT_INTR) |
336 | __spu_trap_data_seg(spu, dar); | |
337 | ||
8af30675 | 338 | if (stat & CLASS1_STORAGE_FAULT_INTR) |
8b3d6663 | 339 | __spu_trap_data_map(spu, dar, dsisr); |
67207b96 | 340 | |
8af30675 | 341 | if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR) |
67207b96 AB |
342 | ; |
343 | ||
8af30675 | 344 | if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR) |
67207b96 AB |
345 | ; |
346 | ||
f3d69e05 LB |
347 | spu->class_1_dsisr = 0; |
348 | spu->class_1_dar = 0; | |
349 | ||
2c911a14 LB |
350 | spin_unlock(&spu->register_lock); |
351 | ||
67207b96 AB |
352 | return stat ? IRQ_HANDLED : IRQ_NONE; |
353 | } | |
354 | ||
355 | static irqreturn_t | |
f5a92458 | 356 | spu_irq_class_2(int irq, void *data) |
67207b96 AB |
357 | { |
358 | struct spu *spu; | |
359 | unsigned long stat; | |
3a843d7c | 360 | unsigned long mask; |
8af30675 JK |
361 | const int mailbox_intrs = |
362 | CLASS2_MAILBOX_THRESHOLD_INTR | CLASS2_MAILBOX_INTR; | |
67207b96 AB |
363 | |
364 | spu = data; | |
ba723fe2 | 365 | spin_lock(&spu->register_lock); |
f0831acc AB |
366 | stat = spu_int_stat_get(spu, 2); |
367 | mask = spu_int_mask_get(spu, 2); | |
ba723fe2 MN |
368 | /* ignore interrupts we're not waiting for */ |
369 | stat &= mask; | |
8af30675 JK |
370 | /* mailbox interrupts are level triggered. mask them now before |
371 | * acknowledging */ | |
372 | if (stat & mailbox_intrs) | |
373 | spu_int_mask_and(spu, 2, ~(stat & mailbox_intrs)); | |
ba723fe2 MN |
374 | /* acknowledge all interrupts before the callbacks */ |
375 | spu_int_stat_clear(spu, 2, stat); | |
67207b96 | 376 | |
3a843d7c | 377 | pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask); |
67207b96 | 378 | |
8af30675 | 379 | if (stat & CLASS2_MAILBOX_INTR) |
ba723fe2 | 380 | spu->ibox_callback(spu); |
67207b96 | 381 | |
8af30675 | 382 | if (stat & CLASS2_SPU_STOP_INTR) |
f3d69e05 | 383 | spu->stop_callback(spu, 2); |
67207b96 | 384 | |
8af30675 | 385 | if (stat & CLASS2_SPU_HALT_INTR) |
f3d69e05 | 386 | spu->stop_callback(spu, 2); |
67207b96 | 387 | |
8af30675 | 388 | if (stat & CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR) |
ba723fe2 | 389 | spu->mfc_callback(spu); |
67207b96 | 390 | |
8af30675 | 391 | if (stat & CLASS2_MAILBOX_THRESHOLD_INTR) |
ba723fe2 | 392 | spu->wbox_callback(spu); |
67207b96 | 393 | |
e9f8a0b6 | 394 | spu->stats.class2_intr++; |
2c911a14 LB |
395 | |
396 | spin_unlock(&spu->register_lock); | |
397 | ||
67207b96 AB |
398 | return stat ? IRQ_HANDLED : IRQ_NONE; |
399 | } | |
400 | ||
0ebfff14 | 401 | static int spu_request_irqs(struct spu *spu) |
67207b96 | 402 | { |
0ebfff14 | 403 | int ret = 0; |
67207b96 | 404 | |
0ebfff14 BH |
405 | if (spu->irqs[0] != NO_IRQ) { |
406 | snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0", | |
407 | spu->number); | |
408 | ret = request_irq(spu->irqs[0], spu_irq_class_0, | |
a3a9f3b4 | 409 | 0, spu->irq_c0, spu); |
0ebfff14 BH |
410 | if (ret) |
411 | goto bail0; | |
412 | } | |
413 | if (spu->irqs[1] != NO_IRQ) { | |
414 | snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1", | |
415 | spu->number); | |
416 | ret = request_irq(spu->irqs[1], spu_irq_class_1, | |
a3a9f3b4 | 417 | 0, spu->irq_c1, spu); |
0ebfff14 BH |
418 | if (ret) |
419 | goto bail1; | |
420 | } | |
421 | if (spu->irqs[2] != NO_IRQ) { | |
422 | snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2", | |
423 | spu->number); | |
424 | ret = request_irq(spu->irqs[2], spu_irq_class_2, | |
a3a9f3b4 | 425 | 0, spu->irq_c2, spu); |
0ebfff14 BH |
426 | if (ret) |
427 | goto bail2; | |
428 | } | |
429 | return 0; | |
67207b96 | 430 | |
0ebfff14 BH |
431 | bail2: |
432 | if (spu->irqs[1] != NO_IRQ) | |
433 | free_irq(spu->irqs[1], spu); | |
434 | bail1: | |
435 | if (spu->irqs[0] != NO_IRQ) | |
436 | free_irq(spu->irqs[0], spu); | |
437 | bail0: | |
67207b96 AB |
438 | return ret; |
439 | } | |
440 | ||
0ebfff14 | 441 | static void spu_free_irqs(struct spu *spu) |
67207b96 | 442 | { |
0ebfff14 BH |
443 | if (spu->irqs[0] != NO_IRQ) |
444 | free_irq(spu->irqs[0], spu); | |
445 | if (spu->irqs[1] != NO_IRQ) | |
446 | free_irq(spu->irqs[1], spu); | |
447 | if (spu->irqs[2] != NO_IRQ) | |
448 | free_irq(spu->irqs[2], spu); | |
67207b96 AB |
449 | } |
450 | ||
486acd48 | 451 | void spu_init_channels(struct spu *spu) |
67207b96 AB |
452 | { |
453 | static const struct { | |
454 | unsigned channel; | |
455 | unsigned count; | |
456 | } zero_list[] = { | |
457 | { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, }, | |
458 | { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, }, | |
459 | }, count_list[] = { | |
460 | { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, }, | |
461 | { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, }, | |
462 | { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, }, | |
463 | }; | |
6ff730c3 | 464 | struct spu_priv2 __iomem *priv2; |
67207b96 AB |
465 | int i; |
466 | ||
467 | priv2 = spu->priv2; | |
468 | ||
469 | /* initialize all channel data to zero */ | |
470 | for (i = 0; i < ARRAY_SIZE(zero_list); i++) { | |
471 | int count; | |
472 | ||
473 | out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel); | |
474 | for (count = 0; count < zero_list[i].count; count++) | |
475 | out_be64(&priv2->spu_chnldata_RW, 0); | |
476 | } | |
477 | ||
478 | /* initialize channel counts to meaningful values */ | |
479 | for (i = 0; i < ARRAY_SIZE(count_list); i++) { | |
480 | out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel); | |
481 | out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count); | |
482 | } | |
483 | } | |
486acd48 | 484 | EXPORT_SYMBOL_GPL(spu_init_channels); |
67207b96 | 485 | |
8a25a2fd | 486 | static struct bus_type spu_subsys = { |
af5ca3f4 | 487 | .name = "spu", |
8a25a2fd | 488 | .dev_name = "spu", |
1d64093f JK |
489 | }; |
490 | ||
8a25a2fd | 491 | int spu_add_dev_attr(struct device_attribute *attr) |
e570beb6 CK |
492 | { |
493 | struct spu *spu; | |
e570beb6 | 494 | |
24140594 | 495 | mutex_lock(&spu_full_list_mutex); |
e570beb6 | 496 | list_for_each_entry(spu, &spu_full_list, full_list) |
8a25a2fd | 497 | device_create_file(&spu->dev, attr); |
24140594 | 498 | mutex_unlock(&spu_full_list_mutex); |
e570beb6 | 499 | |
e570beb6 CK |
500 | return 0; |
501 | } | |
8a25a2fd | 502 | EXPORT_SYMBOL_GPL(spu_add_dev_attr); |
e570beb6 | 503 | |
8a25a2fd | 504 | int spu_add_dev_attr_group(struct attribute_group *attrs) |
e570beb6 CK |
505 | { |
506 | struct spu *spu; | |
1e771039 | 507 | int rc = 0; |
e570beb6 | 508 | |
24140594 | 509 | mutex_lock(&spu_full_list_mutex); |
1e771039 | 510 | list_for_each_entry(spu, &spu_full_list, full_list) { |
8a25a2fd | 511 | rc = sysfs_create_group(&spu->dev.kobj, attrs); |
1e771039 JK |
512 | |
513 | /* we're in trouble here, but try unwinding anyway */ | |
514 | if (rc) { | |
515 | printk(KERN_ERR "%s: can't create sysfs group '%s'\n", | |
516 | __func__, attrs->name); | |
517 | ||
518 | list_for_each_entry_continue_reverse(spu, | |
519 | &spu_full_list, full_list) | |
8a25a2fd | 520 | sysfs_remove_group(&spu->dev.kobj, attrs); |
1e771039 JK |
521 | break; |
522 | } | |
523 | } | |
524 | ||
24140594 | 525 | mutex_unlock(&spu_full_list_mutex); |
e570beb6 | 526 | |
1e771039 | 527 | return rc; |
e570beb6 | 528 | } |
8a25a2fd | 529 | EXPORT_SYMBOL_GPL(spu_add_dev_attr_group); |
e570beb6 CK |
530 | |
531 | ||
8a25a2fd | 532 | void spu_remove_dev_attr(struct device_attribute *attr) |
e570beb6 CK |
533 | { |
534 | struct spu *spu; | |
e570beb6 | 535 | |
24140594 | 536 | mutex_lock(&spu_full_list_mutex); |
e570beb6 | 537 | list_for_each_entry(spu, &spu_full_list, full_list) |
8a25a2fd | 538 | device_remove_file(&spu->dev, attr); |
24140594 | 539 | mutex_unlock(&spu_full_list_mutex); |
e570beb6 | 540 | } |
8a25a2fd | 541 | EXPORT_SYMBOL_GPL(spu_remove_dev_attr); |
e570beb6 | 542 | |
8a25a2fd | 543 | void spu_remove_dev_attr_group(struct attribute_group *attrs) |
e570beb6 CK |
544 | { |
545 | struct spu *spu; | |
e570beb6 | 546 | |
24140594 | 547 | mutex_lock(&spu_full_list_mutex); |
e570beb6 | 548 | list_for_each_entry(spu, &spu_full_list, full_list) |
8a25a2fd | 549 | sysfs_remove_group(&spu->dev.kobj, attrs); |
24140594 | 550 | mutex_unlock(&spu_full_list_mutex); |
e570beb6 | 551 | } |
8a25a2fd | 552 | EXPORT_SYMBOL_GPL(spu_remove_dev_attr_group); |
e570beb6 | 553 | |
8a25a2fd | 554 | static int spu_create_dev(struct spu *spu) |
1d64093f JK |
555 | { |
556 | int ret; | |
557 | ||
8a25a2fd KS |
558 | spu->dev.id = spu->number; |
559 | spu->dev.bus = &spu_subsys; | |
560 | ret = device_register(&spu->dev); | |
1d64093f JK |
561 | if (ret) { |
562 | printk(KERN_ERR "Can't register SPU %d with sysfs\n", | |
563 | spu->number); | |
564 | return ret; | |
565 | } | |
566 | ||
8a25a2fd | 567 | sysfs_add_device_to_node(&spu->dev, spu->node); |
1d64093f JK |
568 | |
569 | return 0; | |
570 | } | |
571 | ||
e28b0031 | 572 | static int __init create_spu(void *data) |
67207b96 AB |
573 | { |
574 | struct spu *spu; | |
575 | int ret; | |
576 | static int number; | |
94b2a439 | 577 | unsigned long flags; |
67207b96 AB |
578 | |
579 | ret = -ENOMEM; | |
ecec2177 | 580 | spu = kzalloc(sizeof (*spu), GFP_KERNEL); |
67207b96 AB |
581 | if (!spu) |
582 | goto out; | |
583 | ||
486acd48 CH |
584 | spu->alloc_state = SPU_FREE; |
585 | ||
e28b0031 | 586 | spin_lock_init(&spu->register_lock); |
24140594 | 587 | spin_lock(&spu_lock); |
e28b0031 | 588 | spu->number = number++; |
24140594 | 589 | spin_unlock(&spu_lock); |
e28b0031 GL |
590 | |
591 | ret = spu_create_spu(spu, data); | |
e5267b4b | 592 | |
67207b96 AB |
593 | if (ret) |
594 | goto out_free; | |
595 | ||
24f43b33 | 596 | spu_mfc_sdr_setup(spu); |
f0831acc | 597 | spu_mfc_sr1_set(spu, 0x33); |
67207b96 AB |
598 | ret = spu_request_irqs(spu); |
599 | if (ret) | |
e28b0031 | 600 | goto out_destroy; |
67207b96 | 601 | |
8a25a2fd | 602 | ret = spu_create_dev(spu); |
1d64093f JK |
603 | if (ret) |
604 | goto out_free_irqs; | |
605 | ||
486acd48 | 606 | mutex_lock(&cbe_spu_info[spu->node].list_mutex); |
aa6d5b20 AB |
607 | list_add(&spu->cbe_list, &cbe_spu_info[spu->node].spus); |
608 | cbe_spu_info[spu->node].n_spus++; | |
486acd48 | 609 | mutex_unlock(&cbe_spu_info[spu->node].list_mutex); |
24140594 CH |
610 | |
611 | mutex_lock(&spu_full_list_mutex); | |
612 | spin_lock_irqsave(&spu_full_list_lock, flags); | |
e570beb6 | 613 | list_add(&spu->full_list, &spu_full_list); |
24140594 CH |
614 | spin_unlock_irqrestore(&spu_full_list_lock, flags); |
615 | mutex_unlock(&spu_full_list_mutex); | |
67207b96 | 616 | |
27ec41d3 | 617 | spu->stats.util_state = SPU_UTIL_IDLE_LOADED; |
f2dec1ea | 618 | spu->stats.tstamp = ktime_get_ns(); |
fe2f896d | 619 | |
9d92af62 AB |
620 | INIT_LIST_HEAD(&spu->aff_list); |
621 | ||
67207b96 AB |
622 | goto out; |
623 | ||
1d64093f JK |
624 | out_free_irqs: |
625 | spu_free_irqs(spu); | |
e28b0031 GL |
626 | out_destroy: |
627 | spu_destroy_spu(spu); | |
67207b96 AB |
628 | out_free: |
629 | kfree(spu); | |
630 | out: | |
631 | return ret; | |
632 | } | |
633 | ||
fe2f896d CH |
634 | static const char *spu_state_names[] = { |
635 | "user", "system", "iowait", "idle" | |
636 | }; | |
637 | ||
638 | static unsigned long long spu_acct_time(struct spu *spu, | |
639 | enum spu_utilization_state state) | |
640 | { | |
641 | unsigned long long time = spu->stats.times[state]; | |
642 | ||
27ec41d3 AD |
643 | /* |
644 | * If the spu is idle or the context is stopped, utilization | |
645 | * statistics are not updated. Apply the time delta from the | |
646 | * last recorded state of the spu. | |
647 | */ | |
f2dec1ea TG |
648 | if (spu->stats.util_state == state) |
649 | time += ktime_get_ns() - spu->stats.tstamp; | |
fe2f896d | 650 | |
27ec41d3 | 651 | return time / NSEC_PER_MSEC; |
fe2f896d CH |
652 | } |
653 | ||
654 | ||
8a25a2fd KS |
655 | static ssize_t spu_stat_show(struct device *dev, |
656 | struct device_attribute *attr, char *buf) | |
fe2f896d | 657 | { |
8a25a2fd | 658 | struct spu *spu = container_of(dev, struct spu, dev); |
fe2f896d CH |
659 | |
660 | return sprintf(buf, "%s %llu %llu %llu %llu " | |
661 | "%llu %llu %llu %llu %llu %llu %llu %llu\n", | |
27ec41d3 | 662 | spu_state_names[spu->stats.util_state], |
fe2f896d CH |
663 | spu_acct_time(spu, SPU_UTIL_USER), |
664 | spu_acct_time(spu, SPU_UTIL_SYSTEM), | |
665 | spu_acct_time(spu, SPU_UTIL_IOWAIT), | |
27ec41d3 | 666 | spu_acct_time(spu, SPU_UTIL_IDLE_LOADED), |
fe2f896d CH |
667 | spu->stats.vol_ctx_switch, |
668 | spu->stats.invol_ctx_switch, | |
669 | spu->stats.slb_flt, | |
670 | spu->stats.hash_flt, | |
671 | spu->stats.min_flt, | |
672 | spu->stats.maj_flt, | |
673 | spu->stats.class2_intr, | |
674 | spu->stats.libassist); | |
675 | } | |
676 | ||
96cf3f66 | 677 | static DEVICE_ATTR(stat, 0444, spu_stat_show, NULL); |
fe2f896d | 678 | |
158d5b5e AB |
679 | #ifdef CONFIG_KEXEC |
680 | ||
681 | struct crash_spu_info { | |
682 | struct spu *spu; | |
683 | u32 saved_spu_runcntl_RW; | |
684 | u32 saved_spu_status_R; | |
685 | u32 saved_spu_npc_RW; | |
686 | u64 saved_mfc_sr1_RW; | |
687 | u64 saved_mfc_dar; | |
688 | u64 saved_mfc_dsisr; | |
689 | }; | |
690 | ||
691 | #define CRASH_NUM_SPUS 16 /* Enough for current hardware */ | |
692 | static struct crash_spu_info crash_spu_info[CRASH_NUM_SPUS]; | |
693 | ||
694 | static void crash_kexec_stop_spus(void) | |
695 | { | |
696 | struct spu *spu; | |
697 | int i; | |
698 | u64 tmp; | |
699 | ||
700 | for (i = 0; i < CRASH_NUM_SPUS; i++) { | |
701 | if (!crash_spu_info[i].spu) | |
702 | continue; | |
703 | ||
704 | spu = crash_spu_info[i].spu; | |
705 | ||
706 | crash_spu_info[i].saved_spu_runcntl_RW = | |
707 | in_be32(&spu->problem->spu_runcntl_RW); | |
708 | crash_spu_info[i].saved_spu_status_R = | |
709 | in_be32(&spu->problem->spu_status_R); | |
710 | crash_spu_info[i].saved_spu_npc_RW = | |
711 | in_be32(&spu->problem->spu_npc_RW); | |
712 | ||
713 | crash_spu_info[i].saved_mfc_dar = spu_mfc_dar_get(spu); | |
714 | crash_spu_info[i].saved_mfc_dsisr = spu_mfc_dsisr_get(spu); | |
715 | tmp = spu_mfc_sr1_get(spu); | |
716 | crash_spu_info[i].saved_mfc_sr1_RW = tmp; | |
717 | ||
718 | tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; | |
719 | spu_mfc_sr1_set(spu, tmp); | |
720 | ||
721 | __delay(200); | |
722 | } | |
723 | } | |
724 | ||
725 | static void crash_register_spus(struct list_head *list) | |
726 | { | |
727 | struct spu *spu; | |
728 | int ret; | |
729 | ||
730 | list_for_each_entry(spu, list, full_list) { | |
731 | if (WARN_ON(spu->number >= CRASH_NUM_SPUS)) | |
732 | continue; | |
733 | ||
734 | crash_spu_info[spu->number].spu = spu; | |
735 | } | |
736 | ||
737 | ret = crash_shutdown_register(&crash_kexec_stop_spus); | |
738 | if (ret) | |
739 | printk(KERN_ERR "Could not register SPU crash handler"); | |
740 | } | |
741 | ||
742 | #else | |
743 | static inline void crash_register_spus(struct list_head *list) | |
744 | { | |
745 | } | |
746 | #endif | |
747 | ||
f5a592f7 RW |
748 | static void spu_shutdown(void) |
749 | { | |
750 | struct spu *spu; | |
751 | ||
752 | mutex_lock(&spu_full_list_mutex); | |
753 | list_for_each_entry(spu, &spu_full_list, full_list) { | |
754 | spu_free_irqs(spu); | |
755 | spu_destroy_spu(spu); | |
756 | } | |
757 | mutex_unlock(&spu_full_list_mutex); | |
758 | } | |
759 | ||
760 | static struct syscore_ops spu_syscore_ops = { | |
761 | .shutdown = spu_shutdown, | |
762 | }; | |
763 | ||
67207b96 AB |
764 | static int __init init_spu_base(void) |
765 | { | |
befdc746 | 766 | int i, ret = 0; |
67207b96 | 767 | |
aa6d5b20 | 768 | for (i = 0; i < MAX_NUMNODES; i++) { |
486acd48 | 769 | mutex_init(&cbe_spu_info[i].list_mutex); |
aa6d5b20 | 770 | INIT_LIST_HEAD(&cbe_spu_info[i].spus); |
aa6d5b20 | 771 | } |
ccf17e9d | 772 | |
da06aa08 | 773 | if (!spu_management_ops) |
befdc746 | 774 | goto out; |
da06aa08 | 775 | |
8a25a2fd KS |
776 | /* create system subsystem for spus */ |
777 | ret = subsys_system_register(&spu_subsys, NULL); | |
1d64093f | 778 | if (ret) |
befdc746 | 779 | goto out; |
1d64093f | 780 | |
e28b0031 GL |
781 | ret = spu_enumerate_spus(create_spu); |
782 | ||
bce94513 | 783 | if (ret < 0) { |
e28b0031 | 784 | printk(KERN_WARNING "%s: Error initializing spus\n", |
e48b1b45 | 785 | __func__); |
8a25a2fd | 786 | goto out_unregister_subsys; |
67207b96 | 787 | } |
ff8a8f25 | 788 | |
ae52bb23 | 789 | if (ret > 0) |
bce94513 | 790 | fb_append_extra_logo(&logo_spe_clut224, ret); |
bce94513 | 791 | |
24140594 | 792 | mutex_lock(&spu_full_list_mutex); |
ff8a8f25 | 793 | xmon_register_spus(&spu_full_list); |
8d2655e6 | 794 | crash_register_spus(&spu_full_list); |
24140594 | 795 | mutex_unlock(&spu_full_list_mutex); |
8a25a2fd | 796 | spu_add_dev_attr(&dev_attr_stat); |
f5a592f7 | 797 | register_syscore_ops(&spu_syscore_ops); |
fe2f896d | 798 | |
f5996449 | 799 | spu_init_affinity(); |
3ad216ca | 800 | |
befdc746 CH |
801 | return 0; |
802 | ||
8a25a2fd KS |
803 | out_unregister_subsys: |
804 | bus_unregister(&spu_subsys); | |
befdc746 | 805 | out: |
67207b96 AB |
806 | return ret; |
807 | } | |
8038665f | 808 | device_initcall(init_spu_base); |