Commit | Line | Data |
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f0831acc | 1 | /* |
540270d8 GL |
2 | * spu hypervisor abstraction for direct hardware access. |
3 | * | |
4 | * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 | |
5 | * Copyright 2006 Sony Corp. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
f0831acc | 19 | */ |
540270d8 | 20 | |
e28b0031 GL |
21 | #include <linux/interrupt.h> |
22 | #include <linux/list.h> | |
f0831acc | 23 | #include <linux/module.h> |
e28b0031 GL |
24 | #include <linux/ptrace.h> |
25 | #include <linux/slab.h> | |
26 | #include <linux/wait.h> | |
27 | #include <linux/mm.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/device.h> | |
7a214200 | 31 | #include <linux/sched.h> |
f0831acc | 32 | |
f0831acc | 33 | #include <asm/spu.h> |
540270d8 | 34 | #include <asm/spu_priv1.h> |
e28b0031 GL |
35 | #include <asm/firmware.h> |
36 | #include <asm/prom.h> | |
f0831acc | 37 | |
a91942ae | 38 | #include "interrupt.h" |
e28b0031 GL |
39 | #include "spu_priv1_mmio.h" |
40 | ||
540270d8 | 41 | static void int_mask_and(struct spu *spu, int class, u64 mask) |
f0831acc AB |
42 | { |
43 | u64 old_mask; | |
44 | ||
c9868fe0 IK |
45 | old_mask = in_be64(&spu->priv1->int_mask_RW[class]); |
46 | out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); | |
f0831acc | 47 | } |
f0831acc | 48 | |
540270d8 | 49 | static void int_mask_or(struct spu *spu, int class, u64 mask) |
f0831acc AB |
50 | { |
51 | u64 old_mask; | |
52 | ||
c9868fe0 IK |
53 | old_mask = in_be64(&spu->priv1->int_mask_RW[class]); |
54 | out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); | |
f0831acc | 55 | } |
f0831acc | 56 | |
540270d8 | 57 | static void int_mask_set(struct spu *spu, int class, u64 mask) |
f0831acc | 58 | { |
c9868fe0 | 59 | out_be64(&spu->priv1->int_mask_RW[class], mask); |
f0831acc | 60 | } |
f0831acc | 61 | |
540270d8 | 62 | static u64 int_mask_get(struct spu *spu, int class) |
f0831acc | 63 | { |
c9868fe0 | 64 | return in_be64(&spu->priv1->int_mask_RW[class]); |
f0831acc | 65 | } |
f0831acc | 66 | |
540270d8 | 67 | static void int_stat_clear(struct spu *spu, int class, u64 stat) |
f0831acc | 68 | { |
c9868fe0 | 69 | out_be64(&spu->priv1->int_stat_RW[class], stat); |
f0831acc | 70 | } |
f0831acc | 71 | |
540270d8 | 72 | static u64 int_stat_get(struct spu *spu, int class) |
f0831acc | 73 | { |
c9868fe0 | 74 | return in_be64(&spu->priv1->int_stat_RW[class]); |
f0831acc | 75 | } |
f0831acc | 76 | |
a91942ae | 77 | static void cpu_affinity_set(struct spu *spu, int cpu) |
f0831acc | 78 | { |
7a214200 LB |
79 | u64 target; |
80 | u64 route; | |
81 | ||
82 | if (nr_cpus_node(spu->node)) { | |
86c6f274 RR |
83 | const struct cpumask *spumask = cpumask_of_node(spu->node), |
84 | *cpumask = cpumask_of_node(cpu_to_node(cpu)); | |
7a214200 | 85 | |
86c6f274 | 86 | if (!cpumask_intersects(spumask, cpumask)) |
7a214200 LB |
87 | return; |
88 | } | |
89 | ||
90 | target = iic_get_target_id(cpu); | |
91 | route = target << 48 | target << 32 | target << 16; | |
c9868fe0 | 92 | out_be64(&spu->priv1->int_route_RW, route); |
f0831acc | 93 | } |
f0831acc | 94 | |
540270d8 | 95 | static u64 mfc_dar_get(struct spu *spu) |
f0831acc | 96 | { |
c9868fe0 | 97 | return in_be64(&spu->priv1->mfc_dar_RW); |
f0831acc | 98 | } |
f0831acc | 99 | |
540270d8 | 100 | static u64 mfc_dsisr_get(struct spu *spu) |
f0831acc | 101 | { |
c9868fe0 | 102 | return in_be64(&spu->priv1->mfc_dsisr_RW); |
f0831acc | 103 | } |
f0831acc | 104 | |
540270d8 | 105 | static void mfc_dsisr_set(struct spu *spu, u64 dsisr) |
f0831acc | 106 | { |
c9868fe0 | 107 | out_be64(&spu->priv1->mfc_dsisr_RW, dsisr); |
f0831acc | 108 | } |
f0831acc | 109 | |
24f43b33 | 110 | static void mfc_sdr_setup(struct spu *spu) |
f0831acc | 111 | { |
c9868fe0 | 112 | out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1)); |
f0831acc | 113 | } |
f0831acc | 114 | |
540270d8 | 115 | static void mfc_sr1_set(struct spu *spu, u64 sr1) |
f0831acc | 116 | { |
c9868fe0 | 117 | out_be64(&spu->priv1->mfc_sr1_RW, sr1); |
f0831acc | 118 | } |
f0831acc | 119 | |
540270d8 | 120 | static u64 mfc_sr1_get(struct spu *spu) |
f0831acc | 121 | { |
c9868fe0 | 122 | return in_be64(&spu->priv1->mfc_sr1_RW); |
f0831acc | 123 | } |
f0831acc | 124 | |
540270d8 | 125 | static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id) |
f0831acc | 126 | { |
c9868fe0 | 127 | out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id); |
f0831acc | 128 | } |
f0831acc | 129 | |
540270d8 | 130 | static u64 mfc_tclass_id_get(struct spu *spu) |
f0831acc | 131 | { |
c9868fe0 | 132 | return in_be64(&spu->priv1->mfc_tclass_id_RW); |
f0831acc | 133 | } |
f0831acc | 134 | |
540270d8 | 135 | static void tlb_invalidate(struct spu *spu) |
f0831acc | 136 | { |
c9868fe0 | 137 | out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul); |
f0831acc | 138 | } |
f0831acc | 139 | |
540270d8 | 140 | static void resource_allocation_groupID_set(struct spu *spu, u64 id) |
f0831acc | 141 | { |
c9868fe0 | 142 | out_be64(&spu->priv1->resource_allocation_groupID_RW, id); |
f0831acc | 143 | } |
f0831acc | 144 | |
540270d8 | 145 | static u64 resource_allocation_groupID_get(struct spu *spu) |
f0831acc | 146 | { |
c9868fe0 | 147 | return in_be64(&spu->priv1->resource_allocation_groupID_RW); |
f0831acc | 148 | } |
f0831acc | 149 | |
540270d8 | 150 | static void resource_allocation_enable_set(struct spu *spu, u64 enable) |
f0831acc | 151 | { |
c9868fe0 | 152 | out_be64(&spu->priv1->resource_allocation_enable_RW, enable); |
f0831acc | 153 | } |
f0831acc | 154 | |
540270d8 | 155 | static u64 resource_allocation_enable_get(struct spu *spu) |
f0831acc | 156 | { |
c9868fe0 | 157 | return in_be64(&spu->priv1->resource_allocation_enable_RW); |
f0831acc | 158 | } |
540270d8 GL |
159 | |
160 | const struct spu_priv1_ops spu_priv1_mmio_ops = | |
161 | { | |
162 | .int_mask_and = int_mask_and, | |
163 | .int_mask_or = int_mask_or, | |
164 | .int_mask_set = int_mask_set, | |
165 | .int_mask_get = int_mask_get, | |
166 | .int_stat_clear = int_stat_clear, | |
167 | .int_stat_get = int_stat_get, | |
a91942ae | 168 | .cpu_affinity_set = cpu_affinity_set, |
540270d8 GL |
169 | .mfc_dar_get = mfc_dar_get, |
170 | .mfc_dsisr_get = mfc_dsisr_get, | |
171 | .mfc_dsisr_set = mfc_dsisr_set, | |
24f43b33 | 172 | .mfc_sdr_setup = mfc_sdr_setup, |
540270d8 GL |
173 | .mfc_sr1_set = mfc_sr1_set, |
174 | .mfc_sr1_get = mfc_sr1_get, | |
175 | .mfc_tclass_id_set = mfc_tclass_id_set, | |
176 | .mfc_tclass_id_get = mfc_tclass_id_get, | |
177 | .tlb_invalidate = tlb_invalidate, | |
178 | .resource_allocation_groupID_set = resource_allocation_groupID_set, | |
179 | .resource_allocation_groupID_get = resource_allocation_groupID_get, | |
180 | .resource_allocation_enable_set = resource_allocation_enable_set, | |
181 | .resource_allocation_enable_get = resource_allocation_enable_get, | |
182 | }; |