[deliverable/linux.git] / arch / powerpc / platforms / celleb / scc_epci.c

/*
 * Support for SCC external PCI
 *
 * (C) Copyright 2004-2007 TOSHIBA CORPORATION
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#undef DEBUG

#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/pci_regs.h>
#include <linux/bootmem.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/ppc-pci.h>

#include "scc.h"
#include "pci.h"
#include "interrupt.h"

#define MAX_PCI_DEVICES   32
#define MAX_PCI_FUNCTIONS  8

#define iob()  __asm__ __volatile__("eieio; sync":::"memory")


#if 0 /* test code for epci dummy read */
static void celleb_epci_dummy_read(struct pci_dev *dev)
{
	void *epci_base;
	struct device_node *node;
	struct pci_controller *hose;
	u32 val;

	node = (struct device_node *)dev->bus->sysdata;
	hose = pci_find_hose_for_OF_device(node);

	if (!hose)
		return;

	epci_base = (void *)hose->cfg_addr;

	val = in_be32(epci_base + SCC_EPCI_WATRP);
	iosync();

	return;
}
#endif

static inline void clear_and_disable_master_abort_interrupt(
					struct pci_controller *hose)
{
	void __iomem *addr;
	addr = (void *)hose->cfg_addr + PCI_COMMAND;
	out_be32(addr, in_be32(addr) | (PCI_STATUS_REC_MASTER_ABORT << 16));
}

static int celleb_epci_check_abort(struct pci_controller *hose,
				   unsigned long addr)
{
	void __iomem *reg, *epci_base;
	u32 val;

	iob();
	epci_base = (void *)hose->cfg_addr;

	reg = epci_base + PCI_COMMAND;
	val = in_be32(reg);

	if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
		out_be32(reg,
			 (val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));

		/* clear PCI Controller error, FRE, PMFE */
		reg = epci_base + SCC_EPCI_STATUS;
		out_be32(reg, SCC_EPCI_INT_PAI);

		reg = epci_base + SCC_EPCI_VCSR;
		val = in_be32(reg) & 0xffff;
		val |= SCC_EPCI_VCSR_FRE;
		out_be32(reg, val);

		reg = epci_base + SCC_EPCI_VISTAT;
		out_be32(reg, SCC_EPCI_VISTAT_PMFE);
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	return PCIBIOS_SUCCESSFUL;
}

static unsigned long celleb_epci_make_config_addr(struct pci_controller *hose,
					unsigned int devfn, int where)
{
	unsigned long addr;
	struct pci_bus *bus = hose->bus;

	if (bus->self)
		addr = (unsigned long)hose->cfg_data +
		       (((bus->number & 0xff) << 16)
		        | ((devfn & 0xff) << 8)
		        | (where & 0xff)
		        | 0x01000000);
	else
		addr = (unsigned long)hose->cfg_data +
		       (((devfn & 0xff) << 8) | (where & 0xff));

	pr_debug("EPCI: config_addr = 0x%016lx\n", addr);

	return addr;
}

static int celleb_epci_read_config(struct pci_bus *bus,
			unsigned int devfn, int where, int size, u32 * val)
{
	unsigned long addr;
	struct device_node *node;
	struct pci_controller *hose;

	/* allignment check */
	BUG_ON(where % size);

	node = (struct device_node *)bus->sysdata;
	hose = pci_find_hose_for_OF_device(node);

	if (!hose->cfg_data)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (bus->number == hose->first_busno && devfn == 0) {
		/* EPCI controller self */

		addr = (unsigned long)hose->cfg_addr + where;

		switch (size) {
		case 1:
			*val = in_8((u8 *)addr);
			break;
		case 2:
			*val = in_be16((u16 *)addr);
			break;
		case 4:
			*val = in_be32((u32 *)addr);
			break;
		default:
			return PCIBIOS_DEVICE_NOT_FOUND;
		}

	} else {

		clear_and_disable_master_abort_interrupt(hose);
		addr = celleb_epci_make_config_addr(hose, devfn, where);

		switch (size) {
		case 1:
			*val = in_8((u8 *)addr);
			break;
		case 2:
			*val = in_le16((u16 *)addr);
			break;
		case 4:
			*val = in_le32((u32 *)addr);
			break;
		default:
			return PCIBIOS_DEVICE_NOT_FOUND;
		}
	}

	pr_debug("EPCI: "
		 "addr=0x%lx, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
		 addr, devfn, where, size, *val);

	return celleb_epci_check_abort(hose, 0);
}

static int celleb_epci_write_config(struct pci_bus *bus,
			unsigned int devfn, int where, int size, u32 val)
{
	unsigned long addr;
	struct device_node *node;
	struct pci_controller *hose;

	/* allignment check */
	BUG_ON(where % size);

	node = (struct device_node *)bus->sysdata;
	hose = pci_find_hose_for_OF_device(node);

	if (!hose->cfg_data)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (bus->number == hose->first_busno && devfn == 0) {
		/* EPCI controller self */

		addr = (unsigned long)hose->cfg_addr + where;

		switch (size) {
		case 1:
			out_8((u8 *)addr, val);
			break;
		case 2:
			out_be16((u16 *)addr, val);
			break;
		case 4:
			out_be32((u32 *)addr, val);
			break;
		default:
			return PCIBIOS_DEVICE_NOT_FOUND;
		}

	} else {

		clear_and_disable_master_abort_interrupt(hose);
		addr = celleb_epci_make_config_addr(hose, devfn, where);

		switch (size) {
		case 1:
			out_8((u8 *)addr, val);
			break;
		case 2:
			out_le16((u16 *)addr, val);
			break;
		case 4:
			out_le32((u32 *)addr, val);
			break;
		default:
			return PCIBIOS_DEVICE_NOT_FOUND;
		}
	}

	return celleb_epci_check_abort(hose, addr);
}

struct pci_ops celleb_epci_ops = {
	celleb_epci_read_config,
	celleb_epci_write_config,
};

/* to be moved in FW */
static int __devinit celleb_epci_init(struct pci_controller *hose)
{
	u32 val;
	void __iomem *reg, *epci_base;
	int hwres = 0;

	epci_base = (void *)hose->cfg_addr;

	/* PCI core reset(Internal bus and PCI clock) */
	reg = epci_base + SCC_EPCI_CKCTRL;
	val = in_be32(reg);
	if (val == 0x00030101)
		hwres = 1;
	else {
		val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
		out_be32(reg, val);

		/* set PCI core clock */
		val = in_be32(reg);
		val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
		out_be32(reg, val);

		/* release PCI core reset (internal bus) */
		val = in_be32(reg);
		val |= SCC_EPCI_CKCTRL_CRST0;
		out_be32(reg, val);

		/* set PCI clock select */
		reg = epci_base + SCC_EPCI_CLKRST;
		val = in_be32(reg);
		val &= ~SCC_EPCI_CLKRST_CKS_MASK;
		val |= SCC_EPCI_CLKRST_CKS_2;
		out_be32(reg, val);

		/* set arbiter */
		reg = epci_base + SCC_EPCI_ABTSET;
		out_be32(reg, 0x0f1f001f);	/* temporary value */

		/* buffer on */
		reg = epci_base + SCC_EPCI_CLKRST;
		val = in_be32(reg);
		val |= SCC_EPCI_CLKRST_BC;
		out_be32(reg, val);

		/* PCI clock enable */
		val = in_be32(reg);
		val |= SCC_EPCI_CLKRST_PCKEN;
		out_be32(reg, val);

		/* release PCI core reset (all) */
		reg = epci_base + SCC_EPCI_CKCTRL;
		val = in_be32(reg);
		val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
		out_be32(reg, val);

		/* set base translation registers. (already set by Beat) */

		/* set base address masks. (already set by Beat) */
	}

	/* release interrupt masks and clear all interrupts */
	reg = epci_base + SCC_EPCI_INTSET;
	out_be32(reg, 0x013f011f);	/* all interrupts enable */
	reg = epci_base + SCC_EPCI_VIENAB;
	val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
	out_be32(reg, val);
	reg = epci_base + SCC_EPCI_STATUS;
	out_be32(reg, 0xffffffff);
	reg = epci_base + SCC_EPCI_VISTAT;
	out_be32(reg, 0xffffffff);

	/* disable PCI->IB address translation */
	reg = epci_base + SCC_EPCI_VCSR;
	val = in_be32(reg);
	val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
	out_be32(reg, val);

	/* set base addresses. (no need to set?) */

	/* memory space, bus master enable */
	reg = epci_base + PCI_COMMAND;
	val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
	out_be32(reg, val);

	/* endian mode setup */
	reg = epci_base + SCC_EPCI_ECMODE;
	val = 0x00550155;
	out_be32(reg, val);

	/* set control option */
	reg = epci_base + SCC_EPCI_CNTOPT;
	val = in_be32(reg);
	val |= SCC_EPCI_CNTOPT_O2PMB;
	out_be32(reg, val);

	/* XXX: temporay: set registers for address conversion setup */
	reg = epci_base + SCC_EPCI_CNF10_REG;
	out_be32(reg, 0x80000008);
	reg = epci_base + SCC_EPCI_CNF14_REG;
	out_be32(reg, 0x40000008);

	reg = epci_base + SCC_EPCI_BAM0;
	out_be32(reg, 0x80000000);
	reg = epci_base + SCC_EPCI_BAM1;
	out_be32(reg, 0xe0000000);

	reg = epci_base + SCC_EPCI_PVBAT;
	out_be32(reg, 0x80000000);

	if (!hwres) {
		/* release external PCI reset */
		reg = epci_base + SCC_EPCI_CLKRST;
		val = in_be32(reg);
		val |= SCC_EPCI_CLKRST_PCIRST;
		out_be32(reg, val);
	}

	return 0;
}

int __devinit celleb_setup_epci(struct device_node *node,
				struct pci_controller *hose)
{
	struct resource r;

	pr_debug("PCI: celleb_setup_epci()\n");

	if (of_address_to_resource(node, 0, &r))
		goto error;
	hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
	if (!hose->cfg_addr)
		goto error;
	pr_debug("EPCI: cfg_addr map 0x%016lx->0x%016lx + 0x%016lx\n",
		 r.start, (unsigned long)hose->cfg_addr,
		(r.end - r.start + 1));

	if (of_address_to_resource(node, 2, &r))
		goto error;
	hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
	if (!hose->cfg_data)
		goto error;
	pr_debug("EPCI: cfg_data map 0x%016lx->0x%016lx + 0x%016lx\n",
		 r.start, (unsigned long)hose->cfg_data,
		(r.end - r.start + 1));

	celleb_epci_init(hose);

	return 0;

error:
	return 1;
}
Commit	Line	Data
551a3d87 IK	1	/*
	2	* Support for SCC external PCI
	3	*
	4	* (C) Copyright 2004-2007 TOSHIBA CORPORATION
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along
	17	* with this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	19	*/
	20
	21	#undef DEBUG
	22
	23	#include <linux/kernel.h>
	24	#include <linux/threads.h>
	25	#include <linux/pci.h>
	26	#include <linux/init.h>
	27	#include <linux/pci_regs.h>
	28	#include <linux/bootmem.h>
	29
	30	#include <asm/io.h>
	31	#include <asm/irq.h>
	32	#include <asm/prom.h>
	33	#include <asm/machdep.h>
	34	#include <asm/pci-bridge.h>
	35	#include <asm/ppc-pci.h>
	36
	37	#include "scc.h"
	38	#include "pci.h"
	39	#include "interrupt.h"
	40
	41	#define MAX_PCI_DEVICES 32
	42	#define MAX_PCI_FUNCTIONS 8
	43
	44	#define iob() __asm__ __volatile__("eieio; sync":::"memory")
	45
	46
	47	#if 0 /* test code for epci dummy read */
	48	static void celleb_epci_dummy_read(struct pci_dev *dev)
	49	{
	50	void *epci_base;
	51	struct device_node *node;
	52	struct pci_controller *hose;
	53	u32 val;
	54
	55	node = (struct device_node *)dev->bus->sysdata;
	56	hose = pci_find_hose_for_OF_device(node);
	57
	58	if (!hose)
	59	return;
	60
	61	epci_base = (void *)hose->cfg_addr;
	62
	63	val = in_be32(epci_base + SCC_EPCI_WATRP);
	64	iosync();
65
66	return;
67	}
68	#endif
69
70	static inline void clear_and_disable_master_abort_interrupt(
71	struct pci_controller *hose)
72	{
73	void __iomem *addr;
74	addr = (void *)hose->cfg_addr + PCI_COMMAND;
75	out_be32(addr, in_be32(addr) \| (PCI_STATUS_REC_MASTER_ABORT << 16));
76	}
77
78	static int celleb_epci_check_abort(struct pci_controller *hose,
79	unsigned long addr)
80	{
81	void __iomem reg, epci_base;
82	u32 val;
83
84	iob();
85	epci_base = (void *)hose->cfg_addr;
86
87	reg = epci_base + PCI_COMMAND;
88	val = in_be32(reg);
89
90	if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
91	out_be32(reg,
92	(val & 0xffff) \| (PCI_STATUS_REC_MASTER_ABORT << 16));
93
94	/* clear PCI Controller error, FRE, PMFE */
95	reg = epci_base + SCC_EPCI_STATUS;
96	out_be32(reg, SCC_EPCI_INT_PAI);
97
98	reg = epci_base + SCC_EPCI_VCSR;
99	val = in_be32(reg) & 0xffff;
100	val \|= SCC_EPCI_VCSR_FRE;
101	out_be32(reg, val);
102
103	reg = epci_base + SCC_EPCI_VISTAT;
104	out_be32(reg, SCC_EPCI_VISTAT_PMFE);
105	return PCIBIOS_DEVICE_NOT_FOUND;
106	}
107
108	return PCIBIOS_SUCCESSFUL;
109	}
110
111	static unsigned long celleb_epci_make_config_addr(struct pci_controller *hose,
112	unsigned int devfn, int where)
113	{
114	unsigned long addr;
115	struct pci_bus *bus = hose->bus;
116
117	if (bus->self)
118	addr = (unsigned long)hose->cfg_data +
119	(((bus->number & 0xff) << 16)
120	\| ((devfn & 0xff) << 8)
121	\| (where & 0xff)
122	\| 0x01000000);
123	else
124	addr = (unsigned long)hose->cfg_data +
125	(((devfn & 0xff) << 8) \| (where & 0xff));
126
127	pr_debug("EPCI: config_addr = 0x%016lx\n", addr);
128
129	return addr;
130	}
131
132	static int celleb_epci_read_config(struct pci_bus *bus,
133	unsigned int devfn, int where, int size, u32 * val)
134	{
135	unsigned long addr;
136	struct device_node *node;
137	struct pci_controller *hose;
138
139	/* allignment check */
140	BUG_ON(where % size);
141
142	node = (struct device_node *)bus->sysdata;
143	hose = pci_find_hose_for_OF_device(node);
144
145	if (!hose->cfg_data)
146	return PCIBIOS_DEVICE_NOT_FOUND;
147
148	if (bus->number == hose->first_busno && devfn == 0) {
149	/* EPCI controller self */
150
151	addr = (unsigned long)hose->cfg_addr + where;
152
153	switch (size) {
154	case 1:
155	val = in_8((u8 )addr);
156	break;
157	case 2:
158	val = in_be16((u16 )addr);
159	break;
160	case 4:
161	val = in_be32((u32 )addr);
162	break;
163	default:
164	return PCIBIOS_DEVICE_NOT_FOUND;
165	}
166
167	} else {
168
169	clear_and_disable_master_abort_interrupt(hose);
170	addr = celleb_epci_make_config_addr(hose, devfn, where);
171
172	switch (size) {
173	case 1:
174	val = in_8((u8 )addr);
175	break;
176	case 2:
177	val = in_le16((u16 )addr);
178	break;
179	case 4:
180	val = in_le32((u32 )addr);
181	break;
182	default:
183	return PCIBIOS_DEVICE_NOT_FOUND;
184	}
185	}
186
187	pr_debug("EPCI: "
188	"addr=0x%lx, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
189	addr, devfn, where, size, *val);
190
191	return celleb_epci_check_abort(hose, 0);
192	}
193
194	static int celleb_epci_write_config(struct pci_bus *bus,
195	unsigned int devfn, int where, int size, u32 val)
196	{
197	unsigned long addr;
198	struct device_node *node;
199	struct pci_controller *hose;
200
201	/* allignment check */
202	BUG_ON(where % size);
203
204	node = (struct device_node *)bus->sysdata;
205	hose = pci_find_hose_for_OF_device(node);
206
207	if (!hose->cfg_data)
208	return PCIBIOS_DEVICE_NOT_FOUND;
209
210	if (bus->number == hose->first_busno && devfn == 0) {
211	/* EPCI controller self */
212
213	addr = (unsigned long)hose->cfg_addr + where;
214
215	switch (size) {
216	case 1:
217	out_8((u8 *)addr, val);
218	break;
219	case 2:
220	out_be16((u16 *)addr, val);
221	break;
222	case 4:
223	out_be32((u32 *)addr, val);
224	break;
225	default:
226	return PCIBIOS_DEVICE_NOT_FOUND;
227	}
228
229	} else {
230
231	clear_and_disable_master_abort_interrupt(hose);
232	addr = celleb_epci_make_config_addr(hose, devfn, where);
233
234	switch (size) {
235	case 1:
236	out_8((u8 *)addr, val);
237	break;
238	case 2:
239	out_le16((u16 *)addr, val);
240	break;
241	case 4:
242	out_le32((u32 *)addr, val);
243	break;
244	default:
245	return PCIBIOS_DEVICE_NOT_FOUND;
246	}
247	}
248
249	return celleb_epci_check_abort(hose, addr);
250	}
251
252	struct pci_ops celleb_epci_ops = {
253	celleb_epci_read_config,
254	celleb_epci_write_config,
255	};
256
257	/* to be moved in FW */
258	static int __devinit celleb_epci_init(struct pci_controller *hose)
259	{
260	u32 val;
261	void __iomem reg, epci_base;
262	int hwres = 0;
263
264	epci_base = (void *)hose->cfg_addr;
265
266	/* PCI core reset(Internal bus and PCI clock) */
267	reg = epci_base + SCC_EPCI_CKCTRL;
268	val = in_be32(reg);
269	if (val == 0x00030101)
270	hwres = 1;
271	else {
272	val &= ~(SCC_EPCI_CKCTRL_CRST0 \| SCC_EPCI_CKCTRL_CRST1);
273	out_be32(reg, val);
274
275	/* set PCI core clock */
276	val = in_be32(reg);
277	val \|= (SCC_EPCI_CKCTRL_OCLKEN \| SCC_EPCI_CKCTRL_LCLKEN);
278	out_be32(reg, val);
279
280	/* release PCI core reset (internal bus) */
281	val = in_be32(reg);
282	val \|= SCC_EPCI_CKCTRL_CRST0;
283	out_be32(reg, val);
284
285	/* set PCI clock select */
286	reg = epci_base + SCC_EPCI_CLKRST;
287	val = in_be32(reg);
288	val &= ~SCC_EPCI_CLKRST_CKS_MASK;
289	val \|= SCC_EPCI_CLKRST_CKS_2;
290	out_be32(reg, val);
291
292	/* set arbiter */
293	reg = epci_base + SCC_EPCI_ABTSET;
294	out_be32(reg, 0x0f1f001f); /* temporary value */
295
296	/* buffer on */
297	reg = epci_base + SCC_EPCI_CLKRST;
298	val = in_be32(reg);
299	val \|= SCC_EPCI_CLKRST_BC;
300	out_be32(reg, val);
301
302	/* PCI clock enable */
303	val = in_be32(reg);
304	val \|= SCC_EPCI_CLKRST_PCKEN;
305	out_be32(reg, val);
306
307	/* release PCI core reset (all) */
308	reg = epci_base + SCC_EPCI_CKCTRL;
309	val = in_be32(reg);
310	val \|= (SCC_EPCI_CKCTRL_CRST0 \| SCC_EPCI_CKCTRL_CRST1);
311	out_be32(reg, val);
312
313	/* set base translation registers. (already set by Beat) */
314
315	/* set base address masks. (already set by Beat) */
316	}
317
318	/* release interrupt masks and clear all interrupts */
319	reg = epci_base + SCC_EPCI_INTSET;
320	out_be32(reg, 0x013f011f); /* all interrupts enable */
321	reg = epci_base + SCC_EPCI_VIENAB;
322	val = SCC_EPCI_VIENAB_PMPEE \| SCC_EPCI_VIENAB_PMFEE;
323	out_be32(reg, val);
324	reg = epci_base + SCC_EPCI_STATUS;
325	out_be32(reg, 0xffffffff);
326	reg = epci_base + SCC_EPCI_VISTAT;
327	out_be32(reg, 0xffffffff);
328
329	/* disable PCI->IB address translation */
330	reg = epci_base + SCC_EPCI_VCSR;
331	val = in_be32(reg);
332	val &= ~(SCC_EPCI_VCSR_DR \| SCC_EPCI_VCSR_AT);
333	out_be32(reg, val);
334
335	/* set base addresses. (no need to set?) */
336
337	/* memory space, bus master enable */
338	reg = epci_base + PCI_COMMAND;
339	val = PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER;
340	out_be32(reg, val);
341
342	/* endian mode setup */
343	reg = epci_base + SCC_EPCI_ECMODE;
344	val = 0x00550155;
345	out_be32(reg, val);
346
347	/* set control option */
348	reg = epci_base + SCC_EPCI_CNTOPT;
349	val = in_be32(reg);
350	val \|= SCC_EPCI_CNTOPT_O2PMB;
351	out_be32(reg, val);
352
353	/* XXX: temporay: set registers for address conversion setup */
354	reg = epci_base + SCC_EPCI_CNF10_REG;
355	out_be32(reg, 0x80000008);
356	reg = epci_base + SCC_EPCI_CNF14_REG;
357	out_be32(reg, 0x40000008);
358
359	reg = epci_base + SCC_EPCI_BAM0;
360	out_be32(reg, 0x80000000);
361	reg = epci_base + SCC_EPCI_BAM1;
362	out_be32(reg, 0xe0000000);
363
364	reg = epci_base + SCC_EPCI_PVBAT;
365	out_be32(reg, 0x80000000);
366
367	if (!hwres) {
368	/* release external PCI reset */
369	reg = epci_base + SCC_EPCI_CLKRST;
370	val = in_be32(reg);
371	val \|= SCC_EPCI_CLKRST_PCIRST;
372	out_be32(reg, val);
373	}
374
375	return 0;
376	}
377
378	int __devinit celleb_setup_epci(struct device_node *node,
379	struct pci_controller *hose)
380	{
381	struct resource r;
382
383	pr_debug("PCI: celleb_setup_epci()\n");
384
385	if (of_address_to_resource(node, 0, &r))
386	goto error;
387	hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
388	if (!hose->cfg_addr)
389	goto error;
390	pr_debug("EPCI: cfg_addr map 0x%016lx->0x%016lx + 0x%016lx\n",
391	r.start, (unsigned long)hose->cfg_addr,
392	(r.end - r.start + 1));
393
394	if (of_address_to_resource(node, 2, &r))
395	goto error;
396	hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
397	if (!hose->cfg_data)
398	goto error;
399	pr_debug("EPCI: cfg_data map 0x%016lx->0x%016lx + 0x%016lx\n",
400	r.start, (unsigned long)hose->cfg_data,
401	(r.end - r.start + 1));
402
403	celleb_epci_init(hose);
404
405	return 0;
406
407	error:
408	return 1;
409	}