[deliverable/linux.git] / arch / powerpc / platforms / celleb / scc_epci.c

/*
 * Support for SCC external PCI
 *
 * (C) Copyright 2004-2007 TOSHIBA CORPORATION
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#undef DEBUG

#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/pci_regs.h>
#include <linux/bootmem.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/ppc-pci.h>

#include "scc.h"
#include "pci.h"
#include "interrupt.h"

#define MAX_PCI_DEVICES   32
#define MAX_PCI_FUNCTIONS  8

#define iob()  __asm__ __volatile__("eieio; sync":::"memory")

static inline volatile void __iomem *celleb_epci_get_epci_base(
					struct pci_controller *hose)
{
	/*
	 * Note:
	 * Celleb epci uses cfg_addr as a base address for
	 * epci control registers.
	 */

	return hose->cfg_addr;
}

static inline volatile void __iomem *celleb_epci_get_epci_cfg(
					struct pci_controller *hose)
{
	/*
	 * Note:
	 * Celleb epci uses cfg_data as a base address for
	 * configuration area for epci devices.
	 */

	return hose->cfg_data;
}

#if 0 /* test code for epci dummy read */
static void celleb_epci_dummy_read(struct pci_dev *dev)
{
	volatile void __iomem *epci_base;
	struct device_node *node;
	struct pci_controller *hose;
	u32 val;

	node = (struct device_node *)dev->bus->sysdata;
	hose = pci_find_hose_for_OF_device(node);

	if (!hose)
		return;

	epci_base = celleb_epci_get_epci_base(hose);

	val = in_be32(epci_base + SCC_EPCI_WATRP);
	iosync();

	return;
}
#endif

static inline void clear_and_disable_master_abort_interrupt(
					struct pci_controller *hose)
{
	volatile void __iomem *epci_base, *reg;
	epci_base = celleb_epci_get_epci_base(hose);
	reg = epci_base + PCI_COMMAND;
	out_be32(reg, in_be32(reg) | (PCI_STATUS_REC_MASTER_ABORT << 16));
}

static int celleb_epci_check_abort(struct pci_controller *hose,
				   volatile void __iomem *addr)
{
	volatile void __iomem *reg, *epci_base;
	u32 val;

	iob();
	epci_base = celleb_epci_get_epci_base(hose);

	reg = epci_base + PCI_COMMAND;
	val = in_be32(reg);

	if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
		out_be32(reg,
			 (val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));

		/* clear PCI Controller error, FRE, PMFE */
		reg = epci_base + SCC_EPCI_STATUS;
		out_be32(reg, SCC_EPCI_INT_PAI);

		reg = epci_base + SCC_EPCI_VCSR;
		val = in_be32(reg) & 0xffff;
		val |= SCC_EPCI_VCSR_FRE;
		out_be32(reg, val);

		reg = epci_base + SCC_EPCI_VISTAT;
		out_be32(reg, SCC_EPCI_VISTAT_PMFE);
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	return PCIBIOS_SUCCESSFUL;
}

static volatile void __iomem *celleb_epci_make_config_addr(
					struct pci_bus *bus,
					struct pci_controller *hose,
					unsigned int devfn, int where)
{
	volatile void __iomem *addr;

	if (bus != hose->bus)
		addr = celleb_epci_get_epci_cfg(hose) +
		       (((bus->number & 0xff) << 16)
		        | ((devfn & 0xff) << 8)
		        | (where & 0xff)
		        | 0x01000000);
	else
		addr = celleb_epci_get_epci_cfg(hose) +
		       (((devfn & 0xff) << 8) | (where & 0xff));

	pr_debug("EPCI: config_addr = 0x%p\n", addr);

	return addr;
}

static int celleb_epci_read_config(struct pci_bus *bus,
			unsigned int devfn, int where, int size, u32 * val)
{
	volatile void __iomem *epci_base, *addr;
	struct device_node *node;
	struct pci_controller *hose;

	/* allignment check */
	BUG_ON(where % size);

	node = (struct device_node *)bus->sysdata;
	hose = pci_find_hose_for_OF_device(node);

	if (!celleb_epci_get_epci_cfg(hose))
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (bus->number == hose->first_busno && devfn == 0) {
		/* EPCI controller self */

		epci_base = celleb_epci_get_epci_base(hose);
		addr = epci_base + where;

		switch (size) {
		case 1:
			*val = in_8(addr);
			break;
		case 2:
			*val = in_be16(addr);
			break;
		case 4:
			*val = in_be32(addr);
			break;
		default:
			return PCIBIOS_DEVICE_NOT_FOUND;
		}

	} else {

		clear_and_disable_master_abort_interrupt(hose);
		addr = celleb_epci_make_config_addr(bus, hose, devfn, where);

		switch (size) {
		case 1:
			*val = in_8(addr);
			break;
		case 2:
			*val = in_le16(addr);
			break;
		case 4:
			*val = in_le32(addr);
			break;
		default:
			return PCIBIOS_DEVICE_NOT_FOUND;
		}
	}

	pr_debug("EPCI: "
		 "addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
		 addr, devfn, where, size, *val);

	return celleb_epci_check_abort(hose, NULL);
}

static int celleb_epci_write_config(struct pci_bus *bus,
			unsigned int devfn, int where, int size, u32 val)
{
	volatile void __iomem *epci_base, *addr;
	struct device_node *node;
	struct pci_controller *hose;

	/* allignment check */
	BUG_ON(where % size);

	node = (struct device_node *)bus->sysdata;
	hose = pci_find_hose_for_OF_device(node);


	if (!celleb_epci_get_epci_cfg(hose))
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (bus->number == hose->first_busno && devfn == 0) {
		/* EPCI controller self */

		epci_base = celleb_epci_get_epci_base(hose);
		addr = epci_base + where;

		switch (size) {
		case 1:
			out_8(addr, val);
			break;
		case 2:
			out_be16(addr, val);
			break;
		case 4:
			out_be32(addr, val);
			break;
		default:
			return PCIBIOS_DEVICE_NOT_FOUND;
		}

	} else {

		clear_and_disable_master_abort_interrupt(hose);
		addr = celleb_epci_make_config_addr(bus, hose, devfn, where);

		switch (size) {
		case 1:
			out_8(addr, val);
			break;
		case 2:
			out_le16(addr, val);
			break;
		case 4:
			out_le32(addr, val);
			break;
		default:
			return PCIBIOS_DEVICE_NOT_FOUND;
		}
	}

	return celleb_epci_check_abort(hose, addr);
}

struct pci_ops celleb_epci_ops = {
	celleb_epci_read_config,
	celleb_epci_write_config,
};

/* to be moved in FW */
static int __init celleb_epci_init(struct pci_controller *hose)
{
	u32 val;
	volatile void __iomem *reg, *epci_base;
	int hwres = 0;

	epci_base = celleb_epci_get_epci_base(hose);

	/* PCI core reset(Internal bus and PCI clock) */
	reg = epci_base + SCC_EPCI_CKCTRL;
	val = in_be32(reg);
	if (val == 0x00030101)
		hwres = 1;
	else {
		val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
		out_be32(reg, val);

		/* set PCI core clock */
		val = in_be32(reg);
		val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
		out_be32(reg, val);

		/* release PCI core reset (internal bus) */
		val = in_be32(reg);
		val |= SCC_EPCI_CKCTRL_CRST0;
		out_be32(reg, val);

		/* set PCI clock select */
		reg = epci_base + SCC_EPCI_CLKRST;
		val = in_be32(reg);
		val &= ~SCC_EPCI_CLKRST_CKS_MASK;
		val |= SCC_EPCI_CLKRST_CKS_2;
		out_be32(reg, val);

		/* set arbiter */
		reg = epci_base + SCC_EPCI_ABTSET;
		out_be32(reg, 0x0f1f001f);	/* temporary value */

		/* buffer on */
		reg = epci_base + SCC_EPCI_CLKRST;
		val = in_be32(reg);
		val |= SCC_EPCI_CLKRST_BC;
		out_be32(reg, val);

		/* PCI clock enable */
		val = in_be32(reg);
		val |= SCC_EPCI_CLKRST_PCKEN;
		out_be32(reg, val);

		/* release PCI core reset (all) */
		reg = epci_base + SCC_EPCI_CKCTRL;
		val = in_be32(reg);
		val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
		out_be32(reg, val);

		/* set base translation registers. (already set by Beat) */

		/* set base address masks. (already set by Beat) */
	}

	/* release interrupt masks and clear all interrupts */
	reg = epci_base + SCC_EPCI_INTSET;
	out_be32(reg, 0x013f011f);	/* all interrupts enable */
	reg = epci_base + SCC_EPCI_VIENAB;
	val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
	out_be32(reg, val);
	reg = epci_base + SCC_EPCI_STATUS;
	out_be32(reg, 0xffffffff);
	reg = epci_base + SCC_EPCI_VISTAT;
	out_be32(reg, 0xffffffff);

	/* disable PCI->IB address translation */
	reg = epci_base + SCC_EPCI_VCSR;
	val = in_be32(reg);
	val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
	out_be32(reg, val);

	/* set base addresses. (no need to set?) */

	/* memory space, bus master enable */
	reg = epci_base + PCI_COMMAND;
	val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
	out_be32(reg, val);

	/* endian mode setup */
	reg = epci_base + SCC_EPCI_ECMODE;
	val = 0x00550155;
	out_be32(reg, val);

	/* set control option */
	reg = epci_base + SCC_EPCI_CNTOPT;
	val = in_be32(reg);
	val |= SCC_EPCI_CNTOPT_O2PMB;
	out_be32(reg, val);

	/* XXX: temporay: set registers for address conversion setup */
	reg = epci_base + SCC_EPCI_CNF10_REG;
	out_be32(reg, 0x80000008);
	reg = epci_base + SCC_EPCI_CNF14_REG;
	out_be32(reg, 0x40000008);

	reg = epci_base + SCC_EPCI_BAM0;
	out_be32(reg, 0x80000000);
	reg = epci_base + SCC_EPCI_BAM1;
	out_be32(reg, 0xe0000000);

	reg = epci_base + SCC_EPCI_PVBAT;
	out_be32(reg, 0x80000000);

	if (!hwres) {
		/* release external PCI reset */
		reg = epci_base + SCC_EPCI_CLKRST;
		val = in_be32(reg);
		val |= SCC_EPCI_CLKRST_PCIRST;
		out_be32(reg, val);
	}

	return 0;
}

int __init celleb_setup_epci(struct device_node *node,
				struct pci_controller *hose)
{
	struct resource r;

	pr_debug("PCI: celleb_setup_epci()\n");

	/*
	 * Note:
	 * Celleb epci uses cfg_addr and cfg_data member of
	 * pci_controller structure in irregular way.
	 *
	 * cfg_addr is used to map for control registers of
	 * celleb epci.
	 *
	 * cfg_data is used for configuration area of devices
	 * on Celleb epci buses.
	 */

	if (of_address_to_resource(node, 0, &r))
		goto error;
	hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
	if (!hose->cfg_addr)
		goto error;
	pr_debug("EPCI: cfg_addr map 0x%016lx->0x%016lx + 0x%016lx\n",
		 r.start, (unsigned long)hose->cfg_addr,
		(r.end - r.start + 1));

	if (of_address_to_resource(node, 2, &r))
		goto error;
	hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
	if (!hose->cfg_data)
		goto error;
	pr_debug("EPCI: cfg_data map 0x%016lx->0x%016lx + 0x%016lx\n",
		 r.start, (unsigned long)hose->cfg_data,
		(r.end - r.start + 1));

	celleb_epci_init(hose);

	return 0;

error:
	return 1;
}
Commit	Line	Data
551a3d87 IK	1	/*
	2	* Support for SCC external PCI
	3	*
	4	* (C) Copyright 2004-2007 TOSHIBA CORPORATION
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along
	17	* with this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	19	*/
	20
	21	#undef DEBUG
	22
	23	#include <linux/kernel.h>
	24	#include <linux/threads.h>
	25	#include <linux/pci.h>
	26	#include <linux/init.h>
	27	#include <linux/pci_regs.h>
	28	#include <linux/bootmem.h>
	29
	30	#include <asm/io.h>
	31	#include <asm/irq.h>
	32	#include <asm/prom.h>
	33	#include <asm/machdep.h>
	34	#include <asm/pci-bridge.h>
	35	#include <asm/ppc-pci.h>
	36
	37	#include "scc.h"
	38	#include "pci.h"
	39	#include "interrupt.h"
	40
	41	#define MAX_PCI_DEVICES 32
	42	#define MAX_PCI_FUNCTIONS 8
	43
	44	#define iob() __asm__ __volatile__("eieio; sync":::"memory")
	45
8388374f IK	46	static inline volatile void __iomem *celleb_epci_get_epci_base(
	47	struct pci_controller *hose)
	48	{
	49	/*
	50	* Note:
	51	* Celleb epci uses cfg_addr as a base address for
	52	* epci control registers.
	53	*/
	54
	55	return hose->cfg_addr;
	56	}
	57
	58	static inline volatile void __iomem *celleb_epci_get_epci_cfg(
	59	struct pci_controller *hose)
	60	{
	61	/*
	62	* Note:
	63	* Celleb epci uses cfg_data as a base address for
	64	* configuration area for epci devices.
	65	*/
	66
	67	return hose->cfg_data;
	68	}
551a3d87 IK	69
	70	#if 0 /* test code for epci dummy read */
	71	static void celleb_epci_dummy_read(struct pci_dev *dev)
	72	{
8388374f	73	volatile void __iomem *epci_base;
551a3d87 IK	74	struct device_node *node;
	75	struct pci_controller *hose;
	76	u32 val;
	77
	78	node = (struct device_node *)dev->bus->sysdata;
	79	hose = pci_find_hose_for_OF_device(node);
	80
	81	if (!hose)
	82	return;
	83
8388374f	84	epci_base = celleb_epci_get_epci_base(hose);
551a3d87 IK	85
	86	val = in_be32(epci_base + SCC_EPCI_WATRP);
	87	iosync();
	88
	89	return;
	90	}
	91	#endif
	92
	93	static inline void clear_and_disable_master_abort_interrupt(
	94	struct pci_controller *hose)
	95	{
8388374f IK	96	volatile void __iomem epci_base, reg;
	97	epci_base = celleb_epci_get_epci_base(hose);
	98	reg = epci_base + PCI_COMMAND;
	99	out_be32(reg, in_be32(reg) \| (PCI_STATUS_REC_MASTER_ABORT << 16));
551a3d87 IK	100	}
	101
	102	static int celleb_epci_check_abort(struct pci_controller *hose,
8388374f	103	volatile void __iomem *addr)
551a3d87	104	{
8388374f	105	volatile void __iomem reg, epci_base;
551a3d87 IK	106	u32 val;
	107
	108	iob();
8388374f	109	epci_base = celleb_epci_get_epci_base(hose);
551a3d87 IK	110
	111	reg = epci_base + PCI_COMMAND;
	112	val = in_be32(reg);
	113
	114	if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
	115	out_be32(reg,
	116	(val & 0xffff) \| (PCI_STATUS_REC_MASTER_ABORT << 16));
	117
	118	/* clear PCI Controller error, FRE, PMFE */
	119	reg = epci_base + SCC_EPCI_STATUS;
	120	out_be32(reg, SCC_EPCI_INT_PAI);
	121
	122	reg = epci_base + SCC_EPCI_VCSR;
	123	val = in_be32(reg) & 0xffff;
	124	val \|= SCC_EPCI_VCSR_FRE;
	125	out_be32(reg, val);
	126
	127	reg = epci_base + SCC_EPCI_VISTAT;
	128	out_be32(reg, SCC_EPCI_VISTAT_PMFE);
	129	return PCIBIOS_DEVICE_NOT_FOUND;
	130	}
	131
	132	return PCIBIOS_SUCCESSFUL;
	133	}
	134
8388374f	135	static volatile void __iomem *celleb_epci_make_config_addr(
0f6e74a3	136	struct pci_bus *bus,
8388374f	137	struct pci_controller *hose,
551a3d87 IK	138	unsigned int devfn, int where)
551a3d87 IK	139	{
8388374f	140	volatile void __iomem *addr;
551a3d87	141
0f6e74a3	142	if (bus != hose->bus)
8388374f	143	addr = celleb_epci_get_epci_cfg(hose) +
551a3d87 IK	144	(((bus->number & 0xff) << 16)
	145	\| ((devfn & 0xff) << 8)
	146	\| (where & 0xff)
	147	\| 0x01000000);
	148	else
8388374f	149	addr = celleb_epci_get_epci_cfg(hose) +
551a3d87 IK	150	(((devfn & 0xff) << 8) \| (where & 0xff));
551a3d87 IK	151
f1fda895	152	pr_debug("EPCI: config_addr = 0x%p\n", addr);
551a3d87 IK	153
	154	return addr;
	155	}
	156
	157	static int celleb_epci_read_config(struct pci_bus *bus,
	158	unsigned int devfn, int where, int size, u32 * val)
	159	{
8388374f	160	volatile void __iomem epci_base, addr;
551a3d87 IK	161	struct device_node *node;
	162	struct pci_controller *hose;
	163
	164	/* allignment check */
	165	BUG_ON(where % size);
	166
	167	node = (struct device_node *)bus->sysdata;
	168	hose = pci_find_hose_for_OF_device(node);
	169
8388374f	170	if (!celleb_epci_get_epci_cfg(hose))
551a3d87 IK	171	return PCIBIOS_DEVICE_NOT_FOUND;
	172
	173	if (bus->number == hose->first_busno && devfn == 0) {
	174	/* EPCI controller self */
	175
8388374f IK	176	epci_base = celleb_epci_get_epci_base(hose);
8388374f IK	177	addr = epci_base + where;
551a3d87 IK	178
	179	switch (size) {
	180	case 1:
f1fda895	181	*val = in_8(addr);
551a3d87 IK	182	break;
551a3d87 IK	183	case 2:
f1fda895	184	*val = in_be16(addr);
551a3d87 IK	185	break;
551a3d87 IK	186	case 4:
f1fda895	187	*val = in_be32(addr);
551a3d87 IK	188	break;
	189	default:
	190	return PCIBIOS_DEVICE_NOT_FOUND;
	191	}
	192
	193	} else {
	194
	195	clear_and_disable_master_abort_interrupt(hose);
0f6e74a3	196	addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
551a3d87 IK	197
	198	switch (size) {
	199	case 1:
f1fda895	200	*val = in_8(addr);
551a3d87 IK	201	break;
551a3d87 IK	202	case 2:
f1fda895	203	*val = in_le16(addr);
551a3d87 IK	204	break;
551a3d87 IK	205	case 4:
f1fda895	206	*val = in_le32(addr);
551a3d87 IK	207	break;
	208	default:
	209	return PCIBIOS_DEVICE_NOT_FOUND;
	210	}
	211	}
	212
	213	pr_debug("EPCI: "
8388374f	214	"addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
551a3d87 IK	215	addr, devfn, where, size, *val);
551a3d87 IK	216
f1fda895	217	return celleb_epci_check_abort(hose, NULL);
551a3d87 IK	218	}
	219
	220	static int celleb_epci_write_config(struct pci_bus *bus,
	221	unsigned int devfn, int where, int size, u32 val)
	222	{
8388374f	223	volatile void __iomem epci_base, addr;
551a3d87 IK	224	struct device_node *node;
	225	struct pci_controller *hose;
	226
	227	/* allignment check */
	228	BUG_ON(where % size);
	229
	230	node = (struct device_node *)bus->sysdata;
	231	hose = pci_find_hose_for_OF_device(node);
	232
8388374f IK	233
8388374f IK	234	if (!celleb_epci_get_epci_cfg(hose))
551a3d87 IK	235	return PCIBIOS_DEVICE_NOT_FOUND;
	236
	237	if (bus->number == hose->first_busno && devfn == 0) {
	238	/* EPCI controller self */
	239
8388374f IK	240	epci_base = celleb_epci_get_epci_base(hose);
8388374f IK	241	addr = epci_base + where;
551a3d87 IK	242
	243	switch (size) {
	244	case 1:
f1fda895	245	out_8(addr, val);
551a3d87 IK	246	break;
551a3d87 IK	247	case 2:
f1fda895	248	out_be16(addr, val);
551a3d87 IK	249	break;
551a3d87 IK	250	case 4:
f1fda895	251	out_be32(addr, val);
551a3d87 IK	252	break;
	253	default:
	254	return PCIBIOS_DEVICE_NOT_FOUND;
	255	}
	256
	257	} else {
	258
	259	clear_and_disable_master_abort_interrupt(hose);
0f6e74a3	260	addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
551a3d87 IK	261
	262	switch (size) {
	263	case 1:
f1fda895	264	out_8(addr, val);
551a3d87 IK	265	break;
551a3d87 IK	266	case 2:
f1fda895	267	out_le16(addr, val);
551a3d87 IK	268	break;
551a3d87 IK	269	case 4:
f1fda895	270	out_le32(addr, val);
551a3d87 IK	271	break;
	272	default:
	273	return PCIBIOS_DEVICE_NOT_FOUND;
	274	}
	275	}
	276
	277	return celleb_epci_check_abort(hose, addr);
	278	}
	279
	280	struct pci_ops celleb_epci_ops = {
	281	celleb_epci_read_config,
	282	celleb_epci_write_config,
	283	};
	284
	285	/* to be moved in FW */
a4ebd017	286	static int __init celleb_epci_init(struct pci_controller *hose)
551a3d87 IK	287	{
551a3d87 IK	288	u32 val;
8388374f	289	volatile void __iomem reg, epci_base;
551a3d87 IK	290	int hwres = 0;
551a3d87 IK	291
8388374f	292	epci_base = celleb_epci_get_epci_base(hose);
551a3d87 IK	293
	294	/* PCI core reset(Internal bus and PCI clock) */
	295	reg = epci_base + SCC_EPCI_CKCTRL;
	296	val = in_be32(reg);
	297	if (val == 0x00030101)
	298	hwres = 1;
	299	else {
	300	val &= ~(SCC_EPCI_CKCTRL_CRST0 \| SCC_EPCI_CKCTRL_CRST1);
	301	out_be32(reg, val);
	302
	303	/* set PCI core clock */
	304	val = in_be32(reg);
	305	val \|= (SCC_EPCI_CKCTRL_OCLKEN \| SCC_EPCI_CKCTRL_LCLKEN);
	306	out_be32(reg, val);
	307
	308	/* release PCI core reset (internal bus) */
	309	val = in_be32(reg);
	310	val \|= SCC_EPCI_CKCTRL_CRST0;
	311	out_be32(reg, val);
	312
	313	/* set PCI clock select */
	314	reg = epci_base + SCC_EPCI_CLKRST;
	315	val = in_be32(reg);
	316	val &= ~SCC_EPCI_CLKRST_CKS_MASK;
	317	val \|= SCC_EPCI_CLKRST_CKS_2;
	318	out_be32(reg, val);
	319
	320	/* set arbiter */
	321	reg = epci_base + SCC_EPCI_ABTSET;
	322	out_be32(reg, 0x0f1f001f); /* temporary value */
	323
	324	/* buffer on */
	325	reg = epci_base + SCC_EPCI_CLKRST;
	326	val = in_be32(reg);
	327	val \|= SCC_EPCI_CLKRST_BC;
	328	out_be32(reg, val);
	329
	330	/* PCI clock enable */
	331	val = in_be32(reg);
	332	val \|= SCC_EPCI_CLKRST_PCKEN;
	333	out_be32(reg, val);
	334
	335	/* release PCI core reset (all) */
	336	reg = epci_base + SCC_EPCI_CKCTRL;
	337	val = in_be32(reg);
	338	val \|= (SCC_EPCI_CKCTRL_CRST0 \| SCC_EPCI_CKCTRL_CRST1);
	339	out_be32(reg, val);
	340
	341	/* set base translation registers. (already set by Beat) */
	342
	343	/* set base address masks. (already set by Beat) */
	344	}
	345
	346	/* release interrupt masks and clear all interrupts */
	347	reg = epci_base + SCC_EPCI_INTSET;
	348	out_be32(reg, 0x013f011f); /* all interrupts enable */
	349	reg = epci_base + SCC_EPCI_VIENAB;
	350	val = SCC_EPCI_VIENAB_PMPEE \| SCC_EPCI_VIENAB_PMFEE;
	351	out_be32(reg, val);
	352	reg = epci_base + SCC_EPCI_STATUS;
	353	out_be32(reg, 0xffffffff);
	354	reg = epci_base + SCC_EPCI_VISTAT;
	355	out_be32(reg, 0xffffffff);
	356
357	/* disable PCI->IB address translation */
358	reg = epci_base + SCC_EPCI_VCSR;
359	val = in_be32(reg);
360	val &= ~(SCC_EPCI_VCSR_DR \| SCC_EPCI_VCSR_AT);
361	out_be32(reg, val);
362
363	/* set base addresses. (no need to set?) */
364
365	/* memory space, bus master enable */
366	reg = epci_base + PCI_COMMAND;
367	val = PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER;
368	out_be32(reg, val);
369
370	/* endian mode setup */
371	reg = epci_base + SCC_EPCI_ECMODE;
372	val = 0x00550155;
373	out_be32(reg, val);
374
375	/* set control option */
376	reg = epci_base + SCC_EPCI_CNTOPT;
377	val = in_be32(reg);
378	val \|= SCC_EPCI_CNTOPT_O2PMB;
379	out_be32(reg, val);
380
381	/* XXX: temporay: set registers for address conversion setup */
382	reg = epci_base + SCC_EPCI_CNF10_REG;
383	out_be32(reg, 0x80000008);
384	reg = epci_base + SCC_EPCI_CNF14_REG;
385	out_be32(reg, 0x40000008);
386
387	reg = epci_base + SCC_EPCI_BAM0;
388	out_be32(reg, 0x80000000);
389	reg = epci_base + SCC_EPCI_BAM1;
390	out_be32(reg, 0xe0000000);
391
392	reg = epci_base + SCC_EPCI_PVBAT;
393	out_be32(reg, 0x80000000);
394
395	if (!hwres) {
396	/* release external PCI reset */
397	reg = epci_base + SCC_EPCI_CLKRST;
398	val = in_be32(reg);
399	val \|= SCC_EPCI_CLKRST_PCIRST;
400	out_be32(reg, val);
401	}
402
403	return 0;
404	}
405
a4ebd017	406	int __init celleb_setup_epci(struct device_node *node,
551a3d87 IK	407	struct pci_controller *hose)
	408	{
	409	struct resource r;
	410
	411	pr_debug("PCI: celleb_setup_epci()\n");
	412
8388374f IK	413	/*
	414	* Note:
	415	* Celleb epci uses cfg_addr and cfg_data member of
	416	* pci_controller structure in irregular way.
	417	*
	418	* cfg_addr is used to map for control registers of
	419	* celleb epci.
	420	*
	421	* cfg_data is used for configuration area of devices
	422	* on Celleb epci buses.
	423	*/
	424
551a3d87 IK	425	if (of_address_to_resource(node, 0, &r))
	426	goto error;
	427	hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
	428	if (!hose->cfg_addr)
	429	goto error;
	430	pr_debug("EPCI: cfg_addr map 0x%016lx->0x%016lx + 0x%016lx\n",
	431	r.start, (unsigned long)hose->cfg_addr,
	432	(r.end - r.start + 1));
	433
	434	if (of_address_to_resource(node, 2, &r))
	435	goto error;
	436	hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
	437	if (!hose->cfg_data)
	438	goto error;
	439	pr_debug("EPCI: cfg_data map 0x%016lx->0x%016lx + 0x%016lx\n",
	440	r.start, (unsigned long)hose->cfg_data,
	441	(r.end - r.start + 1));
	442
	443	celleb_epci_init(hose);
	444
	445	return 0;
	446
	447	error:
	448	return 1;
	449	}