[deliverable/linux.git] / arch / powerpc / platforms / chrp / pci.c

/*
 * CHRP pci routines.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/hydra.h>
#include <asm/prom.h>
#include <asm/gg2.h>
#include <asm/machdep.h>
#include <asm/sections.h>
#include <asm/pci-bridge.h>
#include <asm/grackle.h>
#include <asm/rtas.h>

#include "chrp.h"

/* LongTrail */
void __iomem *gg2_pci_config_base;

/*
 * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
 * limit the bus number to 3 bits
 */

int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
			   int len, u32 *val)
{
	volatile void __iomem *cfg_data;
	struct pci_controller *hose = bus->sysdata;

	if (bus->number > 7)
		return PCIBIOS_DEVICE_NOT_FOUND;
	/*
	 * Note: the caller has already checked that off is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
	switch (len) {
	case 1:
		*val =  in_8(cfg_data);
		break;
	case 2:
		*val = in_le16(cfg_data);
		break;
	default:
		*val = in_le32(cfg_data);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
			    int len, u32 val)
{
	volatile void __iomem *cfg_data;
	struct pci_controller *hose = bus->sysdata;

	if (bus->number > 7)
		return PCIBIOS_DEVICE_NOT_FOUND;
	/*
	 * Note: the caller has already checked that off is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
	switch (len) {
	case 1:
		out_8(cfg_data, val);
		break;
	case 2:
		out_le16(cfg_data, val);
		break;
	default:
		out_le32(cfg_data, val);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops gg2_pci_ops =
{
	gg2_read_config,
	gg2_write_config
};

/*
 * Access functions for PCI config space using RTAS calls.
 */
int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
		     int len, u32 *val)
{
	struct pci_controller *hose = bus->sysdata;
	unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
		| (((bus->number - hose->first_busno) & 0xff) << 16)
		| (hose->index << 24);
        int ret = -1;
	int rval;

	rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
	*val = ret;
	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
}

int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
		      int len, u32 val)
{
	struct pci_controller *hose = bus->sysdata;
	unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
		| (((bus->number - hose->first_busno) & 0xff) << 16)
		| (hose->index << 24);
	int rval;

	rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
			 addr, len, val);
	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
}

static struct pci_ops rtas_pci_ops =
{
	rtas_read_config,
	rtas_write_config
};

volatile struct Hydra __iomem *Hydra = NULL;

int __init
hydra_init(void)
{
	struct device_node *np;
	struct resource r;

	np = find_devices("mac-io");
	if (np == NULL || of_address_to_resource(np, 0, &r))
		return 0;
	Hydra = ioremap(r.start, r.end-r.start);
	printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start);
	printk("Hydra Feature_Control was %x",
	       in_le32(&Hydra->Feature_Control));
	out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
					   HYDRA_FC_SCSI_CELL_EN |
					   HYDRA_FC_SCCA_ENABLE |
					   HYDRA_FC_SCCB_ENABLE |
					   HYDRA_FC_ARB_BYPASS |
					   HYDRA_FC_MPIC_ENABLE |
					   HYDRA_FC_SLOW_SCC_PCLK |
					   HYDRA_FC_MPIC_IS_MASTER));
	printk(", now %x\n", in_le32(&Hydra->Feature_Control));
	return 1;
}

#define PRG_CL_RESET_VALID 0x00010000

static void __init
setup_python(struct pci_controller *hose, struct device_node *dev)
{
	u32 __iomem *reg;
	u32 val;
	struct resource r;

	if (of_address_to_resource(dev, 0, &r)) {
		printk(KERN_ERR "No address for Python PCI controller\n");
		return;
	}

	/* Clear the magic go-slow bit */
	reg = ioremap(r.start + 0xf6000, 0x40);
	BUG_ON(!reg); 
	val = in_be32(&reg[12]);
	if (val & PRG_CL_RESET_VALID) {
		out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
		in_be32(&reg[12]);
	}
	iounmap(reg);

	setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010);
}

/* Marvell Discovery II based Pegasos 2 */
static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
{
	struct device_node *root = find_path_device("/");
	struct device_node *rtas;

	of_node_get(root);
	rtas = of_find_node_by_name (root, "rtas");
	if (rtas) {
		hose->ops = &rtas_pci_ops;
		of_node_put(rtas);
	} else {
		printk ("RTAS supporting Pegasos OF not found, please upgrade"
			" your firmware\n");
	}
	pci_assign_all_buses = 1;
}

void __init
chrp_find_bridges(void)
{
	struct device_node *dev;
	const int *bus_range;
	int len, index = -1;
	struct pci_controller *hose;
	const unsigned int *dma;
	const char *model, *machine;
	int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
	struct device_node *root = find_path_device("/");
	struct resource r;
	/*
	 * The PCI host bridge nodes on some machines don't have
	 * properties to adequately identify them, so we have to
	 * look at what sort of machine this is as well.
	 */
	machine = of_get_property(root, "model", NULL);
	if (machine != NULL) {
		is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
		is_mot = strncmp(machine, "MOT", 3) == 0;
		if (strncmp(machine, "Pegasos2", 8) == 0)
			is_pegasos = 2;
		else if (strncmp(machine, "Pegasos", 7) == 0)
			is_pegasos = 1;
	}
	for (dev = root->child; dev != NULL; dev = dev->sibling) {
		if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
			continue;
		++index;
		/* The GG2 bridge on the LongTrail doesn't have an address */
		if (of_address_to_resource(dev, 0, &r) && !is_longtrail) {
			printk(KERN_WARNING "Can't use %s: no address\n",
			       dev->full_name);
			continue;
		}
		bus_range = of_get_property(dev, "bus-range", &len);
		if (bus_range == NULL || len < 2 * sizeof(int)) {
			printk(KERN_WARNING "Can't get bus-range for %s\n",
				dev->full_name);
			continue;
		}
		if (bus_range[1] == bus_range[0])
			printk(KERN_INFO "PCI bus %d", bus_range[0]);
		else
			printk(KERN_INFO "PCI buses %d..%d",
			       bus_range[0], bus_range[1]);
		printk(" controlled by %s", dev->full_name);
		if (!is_longtrail)
			printk(" at %llx", (unsigned long long)r.start);
		printk("\n");

		hose = pcibios_alloc_controller();
		if (!hose) {
			printk("Can't allocate PCI controller structure for %s\n",
				dev->full_name);
			continue;
		}
		hose->arch_data = dev;
		hose->first_busno = bus_range[0];
		hose->last_busno = bus_range[1];

		model = of_get_property(dev, "model", NULL);
		if (model == NULL)
			model = "<none>";
		if (device_is_compatible(dev, "IBM,python")) {
			setup_python(hose, dev);
		} else if (is_mot
			   || strncmp(model, "Motorola, Grackle", 17) == 0) {
			setup_grackle(hose);
		} else if (is_longtrail) {
			void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
			hose->ops = &gg2_pci_ops;
			hose->cfg_data = p;
			gg2_pci_config_base = p;
		} else if (is_pegasos == 1) {
			setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
		} else if (is_pegasos == 2) {
			setup_peg2(hose, dev);
		} else if (!strncmp(model, "IBM,CPC710", 10)) {
			setup_indirect_pci(hose,
					   r.start + 0x000f8000,
					   r.start + 0x000f8010);
			if (index == 0) {
				dma = of_get_property(dev, "system-dma-base",
							&len);
				if (dma && len >= sizeof(*dma)) {
					dma = (unsigned int *)
						(((unsigned long)dma) +
						len - sizeof(*dma));
						pci_dram_offset = *dma;
				}
			}
		} else {
			printk("No methods for %s (model %s), using RTAS\n",
			       dev->full_name, model);
			hose->ops = &rtas_pci_ops;
		}

		pci_process_bridge_OF_ranges(hose, dev, index == 0);

		/* check the first bridge for a property that we can
		   use to set pci_dram_offset */
		dma = of_get_property(dev, "ibm,dma-ranges", &len);
		if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
			pci_dram_offset = dma[2] - dma[3];
			printk("pci_dram_offset = %lx\n", pci_dram_offset);
		}
	}
}

/* SL82C105 IDE Control/Status Register */
#define SL82C105_IDECSR                0x40

/* Fixup for Winbond ATA quirk, required for briq */
void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
{
	u8 progif;

	/* If non-briq machines need that fixup too, please speak up */
	if (!machine_is(chrp) || _chrp_type != _CHRP_briq)
		return;

	if ((sl82c105->class & 5) != 5) {
		printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
		/* Enable SL82C105 PCI native IDE mode */
		pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
		pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05);
		sl82c105->class |= 0x05;
		/* Disable SL82C105 second port */
		pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
		chrp_pci_fixup_winbond_ata);
Commit	Line	Data
bbd0abda PM	1	/*
	2	* CHRP pci routines.
	3	*/
	4
bbd0abda PM	5	#include <linux/kernel.h>
	6	#include <linux/pci.h>
	7	#include <linux/delay.h>
	8	#include <linux/string.h>
	9	#include <linux/init.h>
bbd0abda PM	10
	11	#include <asm/io.h>
	12	#include <asm/pgtable.h>
	13	#include <asm/irq.h>
	14	#include <asm/hydra.h>
	15	#include <asm/prom.h>
	16	#include <asm/gg2.h>
	17	#include <asm/machdep.h>
	18	#include <asm/sections.h>
	19	#include <asm/pci-bridge.h>
bbd0abda PM	20	#include <asm/grackle.h>
	21	#include <asm/rtas.h>
	22
b86756ae PM	23	#include "chrp.h"
b86756ae PM	24
bbd0abda PM	25	/* LongTrail */
	26	void __iomem *gg2_pci_config_base;
	27
	28	/*
	29	* The VLSI Golden Gate II has only 512K of PCI configuration space, so we
	30	* limit the bus number to 3 bits
	31	*/
	32
	33	int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
	34	int len, u32 *val)
	35	{
	36	volatile void __iomem *cfg_data;
	37	struct pci_controller *hose = bus->sysdata;
	38
	39	if (bus->number > 7)
	40	return PCIBIOS_DEVICE_NOT_FOUND;
	41	/*
	42	* Note: the caller has already checked that off is
	43	* suitably aligned and that len is 1, 2 or 4.
	44	*/
	45	cfg_data = hose->cfg_data + ((bus->number<<16) \| (devfn<<8) \| off);
	46	switch (len) {
	47	case 1:
	48	*val = in_8(cfg_data);
	49	break;
	50	case 2:
	51	*val = in_le16(cfg_data);
	52	break;
	53	default:
	54	*val = in_le32(cfg_data);
	55	break;
	56	}
	57	return PCIBIOS_SUCCESSFUL;
	58	}
	59
	60	int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
	61	int len, u32 val)
	62	{
	63	volatile void __iomem *cfg_data;
	64	struct pci_controller *hose = bus->sysdata;
	65
	66	if (bus->number > 7)
	67	return PCIBIOS_DEVICE_NOT_FOUND;
	68	/*
	69	* Note: the caller has already checked that off is
	70	* suitably aligned and that len is 1, 2 or 4.
	71	*/
	72	cfg_data = hose->cfg_data + ((bus->number<<16) \| (devfn<<8) \| off);
	73	switch (len) {
	74	case 1:
	75	out_8(cfg_data, val);
	76	break;
	77	case 2:
	78	out_le16(cfg_data, val);
	79	break;
	80	default:
	81	out_le32(cfg_data, val);
	82	break;
	83	}
	84	return PCIBIOS_SUCCESSFUL;
	85	}
	86
	87	static struct pci_ops gg2_pci_ops =
	88	{
89	gg2_read_config,
90	gg2_write_config
91	};
92
93	/*
94	* Access functions for PCI config space using RTAS calls.
95	*/
96	int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
97	int len, u32 *val)
98	{
99	struct pci_controller *hose = bus->sysdata;
100	unsigned long addr = (offset & 0xff) \| ((devfn & 0xff) << 8)
101	\| (((bus->number - hose->first_busno) & 0xff) << 16)
102	\| (hose->index << 24);
103	int ret = -1;
104	int rval;
105
106	rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
107	*val = ret;
108	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
109	}
110
111	int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
112	int len, u32 val)
113	{
114	struct pci_controller *hose = bus->sysdata;
115	unsigned long addr = (offset & 0xff) \| ((devfn & 0xff) << 8)
116	\| (((bus->number - hose->first_busno) & 0xff) << 16)
117	\| (hose->index << 24);
118	int rval;
119
120	rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
121	addr, len, val);
122	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
123	}
124
125	static struct pci_ops rtas_pci_ops =
126	{
127	rtas_read_config,
128	rtas_write_config
129	};
130
131	volatile struct Hydra __iomem *Hydra = NULL;
132
133	int __init
134	hydra_init(void)
135	{
136	struct device_node *np;
575e3216	137	struct resource r;
bbd0abda PM	138
bbd0abda PM	139	np = find_devices("mac-io");
575e3216	140	if (np == NULL \|\| of_address_to_resource(np, 0, &r))
bbd0abda	141	return 0;
575e3216	142	Hydra = ioremap(r.start, r.end-r.start);
685143ac	143	printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start);
bbd0abda PM	144	printk("Hydra Feature_Control was %x",
	145	in_le32(&Hydra->Feature_Control));
	146	out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN \|
	147	HYDRA_FC_SCSI_CELL_EN \|
	148	HYDRA_FC_SCCA_ENABLE \|
	149	HYDRA_FC_SCCB_ENABLE \|
	150	HYDRA_FC_ARB_BYPASS \|
	151	HYDRA_FC_MPIC_ENABLE \|
	152	HYDRA_FC_SLOW_SCC_PCLK \|
	153	HYDRA_FC_MPIC_IS_MASTER));
	154	printk(", now %x\n", in_le32(&Hydra->Feature_Control));
	155	return 1;
	156	}
	157
bbd0abda PM	158	#define PRG_CL_RESET_VALID 0x00010000
	159
	160	static void __init
	161	setup_python(struct pci_controller hose, struct device_node dev)
	162	{
	163	u32 __iomem *reg;
	164	u32 val;
575e3216	165	struct resource r;
bbd0abda	166
575e3216 DW	167	if (of_address_to_resource(dev, 0, &r)) {
	168	printk(KERN_ERR "No address for Python PCI controller\n");
	169	return;
	170	}
bbd0abda PM	171
bbd0abda PM	172	/* Clear the magic go-slow bit */
575e3216 DW	173	reg = ioremap(r.start + 0xf6000, 0x40);
575e3216 DW	174	BUG_ON(!reg);
bbd0abda PM	175	val = in_be32(&reg[12]);
	176	if (val & PRG_CL_RESET_VALID) {
	177	out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
	178	in_be32(&reg[12]);
	179	}
	180	iounmap(reg);
575e3216 DW	181
575e3216 DW	182	setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010);
bbd0abda PM	183	}
	184
	185	/* Marvell Discovery II based Pegasos 2 */
	186	static void __init setup_peg2(struct pci_controller hose, struct device_node dev)
	187	{
	188	struct device_node *root = find_path_device("/");
	189	struct device_node *rtas;
	190
d60dcd94	191	of_node_get(root);
bbd0abda PM	192	rtas = of_find_node_by_name (root, "rtas");
	193	if (rtas) {
	194	hose->ops = &rtas_pci_ops;
d60dcd94	195	of_node_put(rtas);
bbd0abda PM	196	} else {
	197	printk ("RTAS supporting Pegasos OF not found, please upgrade"
	198	" your firmware\n");
	199	}
	200	pci_assign_all_buses = 1;
	201	}
	202
	203	void __init
	204	chrp_find_bridges(void)
	205	{
	206	struct device_node *dev;
ae6b4101	207	const int *bus_range;
bbd0abda PM	208	int len, index = -1;
bbd0abda PM	209	struct pci_controller *hose;
ae6b4101 JK	210	const unsigned int *dma;
ae6b4101 JK	211	const char model, machine;
bbd0abda PM	212	int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
bbd0abda PM	213	struct device_node *root = find_path_device("/");
575e3216	214	struct resource r;
bbd0abda PM	215	/*
	216	* The PCI host bridge nodes on some machines don't have
	217	* properties to adequately identify them, so we have to
	218	* look at what sort of machine this is as well.
	219	*/
e2eb6392	220	machine = of_get_property(root, "model", NULL);
bbd0abda PM	221	if (machine != NULL) {
	222	is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
	223	is_mot = strncmp(machine, "MOT", 3) == 0;
	224	if (strncmp(machine, "Pegasos2", 8) == 0)
	225	is_pegasos = 2;
	226	else if (strncmp(machine, "Pegasos", 7) == 0)
	227	is_pegasos = 1;
	228	}
	229	for (dev = root->child; dev != NULL; dev = dev->sibling) {
	230	if (dev->type == NULL \|\| strcmp(dev->type, "pci") != 0)
	231	continue;
	232	++index;
	233	/* The GG2 bridge on the LongTrail doesn't have an address */
575e3216	234	if (of_address_to_resource(dev, 0, &r) && !is_longtrail) {
bbd0abda PM	235	printk(KERN_WARNING "Can't use %s: no address\n",
	236	dev->full_name);
	237	continue;
	238	}
e2eb6392	239	bus_range = of_get_property(dev, "bus-range", &len);
bbd0abda PM	240	if (bus_range == NULL \|\| len < 2 * sizeof(int)) {
	241	printk(KERN_WARNING "Can't get bus-range for %s\n",
	242	dev->full_name);
	243	continue;
	244	}
	245	if (bus_range[1] == bus_range[0])
	246	printk(KERN_INFO "PCI bus %d", bus_range[0]);
	247	else
	248	printk(KERN_INFO "PCI buses %d..%d",
	249	bus_range[0], bus_range[1]);
26c5032e	250	printk(" controlled by %s", dev->full_name);
575e3216	251	if (!is_longtrail)
685143ac	252	printk(" at %llx", (unsigned long long)r.start);
bbd0abda PM	253	printk("\n");
	254
	255	hose = pcibios_alloc_controller();
	256	if (!hose) {
	257	printk("Can't allocate PCI controller structure for %s\n",
	258	dev->full_name);
	259	continue;
	260	}
	261	hose->arch_data = dev;
	262	hose->first_busno = bus_range[0];
	263	hose->last_busno = bus_range[1];
	264
e2eb6392	265	model = of_get_property(dev, "model", NULL);
bbd0abda PM	266	if (model == NULL)
	267	model = "<none>";
	268	if (device_is_compatible(dev, "IBM,python")) {
	269	setup_python(hose, dev);
	270	} else if (is_mot
	271	\|\| strncmp(model, "Motorola, Grackle", 17) == 0) {
	272	setup_grackle(hose);
	273	} else if (is_longtrail) {
	274	void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
	275	hose->ops = &gg2_pci_ops;
	276	hose->cfg_data = p;
	277	gg2_pci_config_base = p;
	278	} else if (is_pegasos == 1) {
	279	setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
	280	} else if (is_pegasos == 2) {
	281	setup_peg2(hose, dev);
26c5032e BH	282	} else if (!strncmp(model, "IBM,CPC710", 10)) {
	283	setup_indirect_pci(hose,
	284	r.start + 0x000f8000,
	285	r.start + 0x000f8010);
	286	if (index == 0) {
e2eb6392 SR	287	dma = of_get_property(dev, "system-dma-base",
e2eb6392 SR	288	&len);
26c5032e BH	289	if (dma && len >= sizeof(*dma)) {
	290	dma = (unsigned int *)
	291	(((unsigned long)dma) +
	292	len - sizeof(*dma));
	293	pci_dram_offset = *dma;
	294	}
	295	}
bbd0abda PM	296	} else {
	297	printk("No methods for %s (model %s), using RTAS\n",
	298	dev->full_name, model);
	299	hose->ops = &rtas_pci_ops;
	300	}
	301
	302	pci_process_bridge_OF_ranges(hose, dev, index == 0);
	303
	304	/* check the first bridge for a property that we can
	305	use to set pci_dram_offset */
e2eb6392	306	dma = of_get_property(dev, "ibm,dma-ranges", &len);
bbd0abda PM	307	if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
	308	pci_dram_offset = dma[2] - dma[3];
	309	printk("pci_dram_offset = %lx\n", pci_dram_offset);
	310	}
	311	}
26c5032e BH	312	}
	313
	314	/* SL82C105 IDE Control/Status Register */
	315	#define SL82C105_IDECSR 0x40
	316
	317	/* Fixup for Winbond ATA quirk, required for briq */
	318	void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
	319	{
	320	u8 progif;
bbd0abda	321
26c5032e BH	322	/* If non-briq machines need that fixup too, please speak up */
	323	if (!machine_is(chrp) \|\| _chrp_type != _CHRP_briq)
	324	return;
	325
	326	if ((sl82c105->class & 5) != 5) {
	327	printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
	328	/* Enable SL82C105 PCI native IDE mode */
	329	pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
	330	pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif \| 0x05);
	331	sl82c105->class \|= 0x05;
	332	/* Disable SL82C105 second port */
	333	pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
	334	}
bbd0abda	335	}
26c5032e BH	336	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
26c5032e BH	337	chrp_pci_fixup_winbond_ata);